JPH0815154B2 - Bump for semiconductor element - Google Patents
Bump for semiconductor elementInfo
- Publication number
- JPH0815154B2 JPH0815154B2 JP62119421A JP11942187A JPH0815154B2 JP H0815154 B2 JPH0815154 B2 JP H0815154B2 JP 62119421 A JP62119421 A JP 62119421A JP 11942187 A JP11942187 A JP 11942187A JP H0815154 B2 JPH0815154 B2 JP H0815154B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- bumps
- lsi chip
- ito
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13344—Gold [Au] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13355—Nickel [Ni] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13364—Palladium [Pd] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13373—Rhodium [Rh] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13399—Coating material
- H01L2224/134—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13438—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13444—Gold [Au] as principal constituent
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Description
【発明の詳細な説明】 産業上の利用分野 本発明は液晶表示パネル等の駆動用半導体装置に係
り、液晶表示パネル上へ容易に実装できる半導体素子の
バンプに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving semiconductor device such as a liquid crystal display panel, and more particularly to a bump of a semiconductor element that can be easily mounted on a liquid crystal display panel.
従来の技術 透明電極（以下ITOという）が形成された２枚のガラ
ス板を、電極面を対向させて配置してなる液晶表示パネ
ルの引出し電極に、直接駆動用半導体素子（以下LSIチ
ップという）を実装する方法として、現在２つの方法が
提案されている。その一つは、半田バンプによるフリッ
プチップ方式、他の一つはワイヤボンディング方式であ
る。前者の方式はLSIチップのアルミ電極パッドに半田
バンプを形成し、ITO上はNi−Au,Cr−Auなどでメタライ
ジング処理をし、前記LSIチップをフェイスダウンによ
り位置合せした後、半田のリフローにより接続するもの
である。ワイヤボンディング方式は前者と同様にITOを
メタライジング処理し、Au線またはAl線によりLSIチッ
プとITOを接続するものである。前者の半田バンプは通
常、LSIウエハーの製造プロセスが完成した後、ウエハ
ー全面にCrまたはTiなどを蒸着し、さらにCu,Pd,Au,Pt
のいずれかを蒸着する。この金属層の上にフォトレジス
トを塗布し、アルミパッド上のみを除去した後、半田メ
ッキを必要量メッキする。その後不要な金属層をエッチ
ングで除去し、半田バンプを得るものである。2. Description of the Related Art A semiconductor element for driving (hereinafter referred to as an LSI chip) is directly connected to a lead-out electrode of a liquid crystal display panel in which two glass plates having transparent electrodes (hereinafter referred to as ITO) are arranged so that their electrode surfaces face each other. Currently, two methods are proposed as a method for implementing. One is a flip chip method using solder bumps, and the other is a wire bonding method. In the former method, solder bumps are formed on the aluminum electrode pads of the LSI chip, metallization is performed on the ITO with Ni-Au, Cr-Au, etc., and the LSI chip is aligned face down, and then solder reflow is performed. Are connected by. In the wire bonding method, ITO is metallized in the same manner as the former, and the LSI chip and ITO are connected by Au wire or Al wire. The former solder bump is usually formed by depositing Cr or Ti on the entire surface of the wafer after the manufacturing process of the LSI wafer is completed, and then adding Cu, Pd, Au, Pt.
Either of them is vapor-deposited. A photoresist is applied on this metal layer, and only the aluminum pad is removed, and then a necessary amount of solder is plated. After that, unnecessary metal layers are removed by etching to obtain solder bumps.
発明が解決しようとする問題点 この様に、ITOの引出し電極上へLSIチップを実装する
方式は、前述の通り現在では２つの方式が提案されてい
るが、いずれの方式ともITO上にメタライジング処理を
施さなければならないことと、LSIチップには特殊なバ
ンプを形成しなければならない等、複雑なプロセスが必
要であると共にこのプロセスを実施するためには高額な
設備投資を伴ない、製品の歩留低下やコストアップ等、
多くの問題点を有する。また近年、液晶表示パネルの大
型化に伴い、複数個のLSIチップを同一パネル上に実装
しなければならず、１個のLSIチップでも不良となれ
ば、パネル全体が不良となってしまう。すなわち、前述
の方式では不良LSIチップの交換が不可能に近く、また
交換が可能としても多大の時間を要し、製品コストのア
ップをまねく結果となる。Problems to be Solved by the Invention As described above, as the method of mounting the LSI chip on the extraction electrode of the ITO, two methods are currently proposed as described above, and both methods are metalized on the ITO. It requires complicated processing such as processing and special bumps to be formed on the LSI chip, and this process requires expensive capital investment, Yield reduction, cost increase, etc.
It has many problems. Further, in recent years, with the increase in size of liquid crystal display panels, a plurality of LSI chips must be mounted on the same panel, and if one LSI chip becomes defective, the entire panel becomes defective. That is, in the above-mentioned method, it is almost impossible to replace a defective LSI chip, and even if it can be replaced, it takes a lot of time, resulting in an increase in product cost.
また、ワイヤボンディング方式によるLSIチップの実
装においても前記方式と同様の問題点が残る。すなわ
ち、大型液晶パネルにおいてはワイヤ数が1000〜2000本
にもおよび、１箇所のボンディングミスが生じても交換
しなければならない結果となり、その交換作業に多大の
時間を要する。またワイヤボンディング方式はLSIチッ
プのアルミ電極パッドを全面覆うことができず、湿度の
介在によりアルミの腐食が発生する危険性もあり、信頼
性面でも問題点が残る。In addition, the same problem as in the above method remains in mounting the LSI chip by the wire bonding method. That is, in a large-sized liquid crystal panel, the number of wires is as large as 1000 to 2000, and even if a single bonding error occurs, it must be replaced, which requires a lot of time. In addition, the wire bonding method cannot completely cover the aluminum electrode pads of the LSI chip, and there is a risk that aluminum will corrode due to the presence of humidity, and there remains a problem in terms of reliability.
本発明は以上、述べたような問題点を解決するもので
ある。The present invention solves the problems as described above.
問題点を解決するための手段 上記問題点を解決するために本発明は、半導体素子の
アルミパッド上のバンプが感光性樹脂と導電性粉体から
なる導電性樹脂組成物からなり、液晶表示パネルのITO
引出し電極はメタライジング処理することなく、上記LS
Iチップを接着剤を介し、フエイスダウンで信頼性良
く、実装することが可能となるものである。Means for Solving the Problems In order to solve the above problems, the present invention provides a liquid crystal display panel in which bumps on aluminum pads of a semiconductor element are made of a conductive resin composition including a photosensitive resin and conductive powder. ITO
The extraction electrode is not subjected to metallizing treatment,
The I-chip can be mounted face-down with reliability via an adhesive.
作用 以上の構成により、LSIチップのアルミパッド上に導
電性樹脂バンプを形成することにより、ITO上にメタラ
イジング処理することなく、接着剤を介し熱圧着するの
みで確実な接続が可能となり、取付け、取外しが容易と
なる。With the above configuration, by forming conductive resin bumps on the aluminum pads of the LSI chip, reliable connection can be achieved simply by thermocompression bonding with an adhesive without metalizing the ITO. , Easy to remove.
実施例 本発明による半導体素子用バンプは、導電性樹脂組成
物により形成されるもので、樹脂組成物は感光性を有す
る樹脂、例えばエポキシアクリレート系樹脂，アクリレ
ート基を有するイミド樹脂などが使用できる。結合剤と
なる樹脂に感光性を持たせることは、LSIチップにバン
プを形成するプロセスにおいてファインパターンを作ら
なければならないことと、プロセスが簡素化できること
にある。すなわち本発明によるバンプはフォトリソ工程
により形成するものである。また導電性粉体としてはニ
ッケル粉あるいはニッケル粉に金メッキを施したもの
や、Au,Pd,Rhなどの貴金属粉を単独または複合して用い
ることができる。これらの金属粉として平均粒径が0.2
〜2.0μｍの範囲のものを用いると前述のようなバンプ
表面の凹凸が形成され導電性の面で良好な結果が得られ
る。上記ニッケル粉に0.1〜10wt％のAuメッキを施した
も良く、この場合は更に電気的な安定性が得られる。Au
メッキが0.1wt％以下であると導電性の点でメッキの効
果がなくニッケル粉と同程度となり、また感光性樹脂中
に分散させたとき均一な分散が困難となる。また10wt％
以上になると導電性，耐酸化性の点で優れたものとなる
が経済的に不利となり、適宜調整することが必要であ
る。また上記ニッケル粉は樹脂組成物100重量部に対
し、50〜120重量部の範囲で配合することができる。ニ
ッケル粉が50重量部以下になると導電性が悪くなると共
に、バンプ表面が平滑となりITO上への良好な接続に対
し不利となってくる。また120重量部以上になると塗料
化したときの性状（粘性，チクソトロピー）が悪く均一
な塗膜を得ることが困難となると同時に透光性が悪くな
り光解像度が充分得られなくなる。Example The bump for a semiconductor device according to the present invention is formed of a conductive resin composition, and the resin composition may be a resin having photosensitivity, such as an epoxy acrylate resin or an imide resin having an acrylate group. The photosensitivity of the binder resin means that a fine pattern must be created in the process of forming bumps on an LSI chip and that the process can be simplified. That is, the bump according to the present invention is formed by a photolithography process. As the conductive powder, nickel powder, nickel powder plated with gold, or precious metal powder such as Au, Pd, or Rh can be used alone or in combination. The average particle size of these metal powders is 0.2
If the thickness is in the range of up to 2.0 μm, the bump surface irregularities as described above are formed and good results are obtained in terms of conductivity. The nickel powder may be plated with 0.1 to 10 wt% of Au, in which case electrical stability can be obtained. Au
If the plating amount is 0.1 wt% or less, the effect of plating is not obtained in terms of conductivity, and it is almost the same as nickel powder, and it becomes difficult to disperse it uniformly in the photosensitive resin. Also 10 wt%
When it becomes the above, it becomes excellent in terms of conductivity and oxidation resistance, but it is economically disadvantageous, and it is necessary to adjust it appropriately. The nickel powder can be added in an amount of 50 to 120 parts by weight with respect to 100 parts by weight of the resin composition. When the amount of nickel powder is less than 50 parts by weight, the conductivity becomes poor and the bump surface becomes smooth, which is disadvantageous for a good connection on ITO. If it is more than 120 parts by weight, the properties (viscosity, thixotropy) when it is made into a coating are poor, and it becomes difficult to obtain a uniform coating film, and at the same time, the light-transmitting property deteriorates and the optical resolution cannot be obtained sufficiently.
また、導電粉であるニッケル粉は前述の通りバンプ表
面の凹凸を形成することと、導電性の面から樹枝状のも
のが良い。樹枝状粉は電解法により作られるもので、こ
れを使用することによって粒子同士のからみ合いが生
じ、電気的に接触点が多く導電性が改善される。また、
塗膜表面は凹凸が適度に生じ、本発明の目的でもあるIT
Oとの接触が良好となるものである。Further, it is preferable that the nickel powder, which is a conductive powder, has a dendritic shape in terms of forming bumps and dips on the bump surface as described above and having a conductive surface. Dendritic powder is produced by an electrolysis method, and by using it, entanglement of particles occurs, and there are many electrical contact points to improve conductivity. Also,
The surface of the coating film has some irregularities, which is also the object of the present invention.
Good contact with O.
図に本発明の実施例による半導体素子用バンプを示
す、感光性樹脂組成物と導電性粉体からなる導電性樹脂
組成物は半導体素子が形成されたシリコンウエハー４上
へ全面コーティングし、その厚みが５μｍ以上になるよ
う粘度やコーティング条件を決める。厚みが５μｍ以下
になるような条件を選ぶとバンプ１表面の凹凸ａが小さ
くなることと、ITO上へ熱圧着したときの垂直方向の歪
量が少なく信頼性面で不安定となっている。５μｍ以上
であれば上記問題はなく安定した接続が得られる。また
厚みの上限としては30μｍまでが好ましく、これ以上に
なると垂直方向の抵抗値が高くなり、実装後の電圧損失
が大きく実用的でない。一方、バンプ表面の凹凸ａは１
μｍ以上が好ましく、これ以下になると、熱圧着時に１
個のLSIチップ内のバンプ高さのばらつきを吸収するこ
とができず、接続不良のバンプが生ずる。凹凸ａの上限
は特になく、バンプ厚みまでの凹凸ａでも接続は可能で
あるが、実用上、１μｍ前後が好ましい結果となる。The bumps for semiconductor devices according to the examples of the present invention are shown in the drawings. A conductive resin composition comprising a photosensitive resin composition and conductive powder is coated on the entire surface of a silicon wafer 4 on which semiconductor devices are formed, and its thickness The viscosity and coating conditions are determined so that it becomes 5 μm or more. If the condition that the thickness is 5 μm or less is selected, the unevenness a on the surface of the bump 1 becomes small, and the amount of vertical strain when thermocompression-bonded onto the ITO is small and the reliability is unstable. If it is 5 μm or more, the above problem does not occur and a stable connection can be obtained. Also, the upper limit of the thickness is preferably 30 μm, and if it is more than 30 μm, the resistance value in the vertical direction becomes high, and the voltage loss after mounting is large, which is not practical. On the other hand, the unevenness a on the bump surface is 1
μm or more is preferable, and if it is less than 1 μm, it is 1 when thermocompression bonding.
Variations in bump height within individual LSI chips cannot be absorbed, resulting in bumps with poor connection. There is no particular upper limit to the unevenness a, and connection is possible even with the unevenness a up to the bump thickness, but in practice, a preferable result is around 1 μm.
次に本発明により形成されたバンプ付きLSIチップをI
TO上へメタライズすることなく実装する方法について述
べる。これまで一般に用いられている方法は例えば合成
樹脂（熱可塑性樹脂またはＢステージとなり得る熱硬化
性樹脂）中に導電性粉体を均一に分散させ、シート状に
した、いわゆる異方導電性接着剤（水平方向に絶縁性を
示し、垂直方向に導電性を示す）をITO上あるいはLSIチ
ップ上へ仮止めし、LSIチップの裏面から加圧，加熱す
ることによりバンプとITO間に導電性粉体の粒子が挾み
込まれ垂直方向に導通する。前記合成樹脂は冷却すると
固着または硬化によりガラス上へLSIチップが強固に接
続される。本発明によるバンプを使用すれば前述のよう
な異方導電性接着剤を使用しなくとも接続は可能であ
る。すなわち絶縁性樹脂であっても熱圧着時にバンプと
ITO間に介在する極く薄い絶縁被膜をLSIチップ上のバン
プ表面の凸部によって突き破り、凸部で電気的接触，凹
部に介在する樹脂により固着が十分おこなわれることに
よって、ITOと直接信頼性の高い接続がとれる。バンプ
表面に凹凸がなく平滑な場合は絶縁被膜が間に介在する
ことにより導通不良となる。Next, the bumped LSI chip formed according to the present invention is
The method to implement on TO without metallization is described. The method generally used so far is, for example, a so-called anisotropic conductive adhesive in which conductive powder is uniformly dispersed in a synthetic resin (thermoplastic resin or thermosetting resin that can be B stage) to form a sheet. Conductive powder is applied between the bumps and ITO by temporarily fixing (insulating in the horizontal direction and exhibiting conductivity in the vertical direction) onto the ITO or LSI chip, and pressing and heating from the back surface of the LSI chip. Particles are sandwiched and conduct in the vertical direction. When the synthetic resin is cooled, it is fixed or hardened to firmly connect the LSI chip onto the glass. If the bump according to the present invention is used, the connection can be made without using the anisotropic conductive adhesive as described above. That is, even if it is an insulating resin,
The ultra-thin insulating film interposed between ITOs is pierced by the bumps on the bump surface on the LSI chip, electrical contact is made at the bumps, and the resin intervening in the recesses is sufficiently fixed to ensure direct contact with ITO. High connection is possible. If the surface of the bump is smooth and has no irregularities, the insulating coating is interposed between the bumps, resulting in poor conduction.
表１に本発明による導電性樹脂組成物の配合を示す。
各実施例の組成物はセラミック三本ロール機により混練
し均質な塗料とした。これら各塗料をシリコンウエハー
上へスピンナーにより大体５μm,10μm,30μｍの厚みに
なるよう塗布した。アルミパッドは100μｍ角のものを
使用し、塗布面積がアルミパッド面積より大きくなるよ
うマスクを設計、使用した。全面コーティングされたウ
エハー上へ上記マスクを位置合せし紫外光により露光，
現像しバンプを得た。さらにウエハーはチップの所定寸
法にダイシングしバンプ付きLSIチップを得た。このLSI
チップを異方導電性接着剤（（株）スリーボンド製TB−
3370）を用い、ITO上へ位置合せし熱圧着した。熱圧着
はLSIチップ裏面よりほぼチップサイズと同一の加熱ツ
ールにより180℃,10秒,15kg/cm2の条件で圧着した。そ
れぞれの実施例で１チップ100パッドのものを10チップ
実施し、そのときの接続不良（電気的オープン）数を表
２に示す。 Table 1 shows the composition of the conductive resin composition according to the present invention.
The composition of each example was kneaded by a ceramic three-roll machine to obtain a homogeneous coating material. Each of these paints was applied onto a silicon wafer by a spinner so as to have a thickness of about 5 μm, 10 μm, and 30 μm. The aluminum pad used was 100 μm square, and the mask was designed and used so that the coating area was larger than the aluminum pad area. Align the above mask on the whole coated wafer and expose it with UV light.
It was developed to obtain bumps. Further, the wafer was diced to a predetermined chip size to obtain an LSI chip with bumps. This LSI
Anisotropic conductive adhesive for chips (TB- manufactured by ThreeBond Co., Ltd.)
3370) and aligned on the ITO and thermocompression bonded. The thermocompression bonding was performed from the backside of the LSI chip under the conditions of 180 ° C, 10 seconds, and 15 kg / cm 2 with the same heating tool as the chip size. In each example, 10 chips having 100 pads per chip were implemented, and the number of connection failures (electrical opens) at that time is shown in Table 2.
比較例１として、バンプ厚み３μｍとし、表面が平滑
（凹凸は0.3μｍ）なものを上記と同様に熱圧着した。
また比較例２としてバンプにAuを使用しその厚みが15μ
ｍで表面粗さ0.2μｍのものを同様に圧着した。その結
果を表２に示す。 As Comparative Example 1, a bump having a thickness of 3 μm and a smooth surface (irregularities of 0.3 μm) was thermocompression bonded in the same manner as above.
Also, as Comparative Example 2, Au was used for the bumps and the thickness was 15μ.
Similarly, a sample having a surface roughness of 0.2 μm was pressure-bonded. The results are shown in Table 2.
さらに、実施例５および６に示したLSIチップを実際
の液晶表示パネルの引出し電極へ前述の異方導電性接着
剤を用い接続し、液晶表示パネルを動作させ、完全動作
することを確認した。Further, the LSI chips shown in Examples 5 and 6 were connected to the extraction electrodes of the actual liquid crystal display panel using the above-mentioned anisotropic conductive adhesive, and the liquid crystal display panel was operated and confirmed to be fully operated.
発明の効果 以上のように本発明による半導体素子用バンプは従来
の半田バンプのように蒸着、メッキ、エッチングなどの
複雑なプロセスと設備を必要とせず単なるフォトリソ工
程のみで形成できる。また、本発明により得たバンプと
その実装方法は有機材料が構造体となっているため、熱
ストレスなどによるガラスとシリコンの熱膨張係数の差
を吸収できるため、半田バンプのようなクラックの発生
はない。さらにバンプ表面の凹凸により、熱圧着時に確
実な接続ができ複数個を同一パネル上へ実装する大型の
液晶表示パネルに対し、非常に大きな特徴を有するもの
である。しかも、もし実装不良となった場合でも局部的
に加熱することにより簡単に取外すことができ、再度圧
着するという部分的補修が可能となり高価な液晶表示パ
ネルを廃業することなく使用でき、製造上の効果大であ
る。EFFECTS OF THE INVENTION As described above, the bumps for semiconductor devices according to the present invention can be formed by a simple photolithography process without requiring complicated processes and equipment such as vapor deposition, plating, etching and the like unlike conventional solder bumps. Further, since the bumps obtained by the present invention and the mounting method thereof are made of an organic material as a structure, a difference in thermal expansion coefficient between glass and silicon due to thermal stress or the like can be absorbed, so that a crack such as a solder bump is generated. There is no. Further, due to the unevenness of the bump surface, a reliable connection can be made at the time of thermocompression bonding, which is a very large feature for a large liquid crystal display panel in which a plurality of them are mounted on the same panel. Moreover, even if the mounting becomes defective, it can be easily removed by locally heating it, and it can be partially repaired by crimping again, and an expensive liquid crystal display panel can be used without going out of business. It is very effective.
図は本発明の実施例を示す断面図である。 １……バンプ、２……アルミパッド、３……絶縁膜、４
……シリコンウエハー。FIG. 1 is a sectional view showing an embodiment of the present invention. 1 ... Bump, 2 ... Aluminum pad, 3 ... Insulating film, 4
...... Silicon wafer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大島 信正 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 特開 昭62−104142（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobumasa Oshima 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-62-104142 (JP, A)
Claims (1)
感光性樹脂と導電性粉体からなる導電性樹脂組成物から
なり、厚み５μｍ以上で表面の凹凸が１μｍ以上である
ことを特徴とする半導体素子用バンプ。1. A bump on an aluminum pad of a semiconductor device,
A bump for a semiconductor element, comprising a conductive resin composition comprising a photosensitive resin and a conductive powder, having a thickness of 5 μm or more and having surface irregularities of 1 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119421A JPH0815154B2 (en) | 1987-05-15 | 1987-05-15 | Bump for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119421A JPH0815154B2 (en) | 1987-05-15 | 1987-05-15 | Bump for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63283144A JPS63283144A (en) | 1988-11-21 |
| JPH0815154B2 true JPH0815154B2 (en) | 1996-02-14 |
Family
ID=14761041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62119421A Expired - Fee Related JPH0815154B2 (en) | 1987-05-15 | 1987-05-15 | Bump for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0815154B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5074947A (en) * | 1989-12-18 | 1991-12-24 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
| US5611140A (en) * | 1989-12-18 | 1997-03-18 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
| JPWO2005045919A1 (en) * | 2003-11-11 | 2007-05-24 | 東レエンジニアリング株式会社 | Non-contact ID card and manufacturing method thereof |
-
1987
- 1987-05-15 JP JP62119421A patent/JPH0815154B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63283144A (en) | 1988-11-21 |
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