JPS63281038A - Flaw detector for circuit board - Google Patents

Abstract

PURPOSE:To securely detect a minute flaw, as well by switching a slide level by two stages in real time corresponding to the conductor pattern part and clearance part of a circuit board being a body to be inspected. CONSTITUTION:Slide level generators 22a and 22b generate a slide level V1 a little bit higher than the normal signal level of the conductor pattern and a slide level V2 a little bit lower than the normal signal level of the clearance part and apply them to comparators 24a and 24b respectively. Normal image data on a circuit board which is not to be inspected are written previously in a template pattern memory 36 for pattern matching. Then an image signal from a camera 10 is compared by the comparators 24a and 24b with the slide levels V1 and V2 and converted into binarization data. One of those binarization data is selected according to an inspection place by controlling a switch circuit 32 with readout data from the pattern memory 36 and supplied to a serial/ parallel converter 26.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention combines image signals of a circuit board captured by a camera, etc.
Regarding a device that detects defects by converting it into digitized data and storing it in an image memory, more specifically, the slice level for binarization is divided into 2 levels between the conductor pattern part and the clearance part of the circuit board.
This invention relates to a circuit board defect detection device that can detect even minute cracks, slight dirt, etc. through step-by-step control.

[Prior Art] In an apparatus for optically inspecting the appearance of printed wiring boards, hybrid IC boards, etc., an image of a circuit board as an object to be inspected is provided as a two-dimensional intensity distribution of light. In order to perform digital image processing on this, it is necessary to perform photoelectric conversion and further convert the obtained analog image signal into binary data.

An example of a conventional technique for binarizing an image signal obtained from a circuit board as an object to be inspected is shown in FIG. 3. The conventional apparatus includes a camera 10, a slice level generator 12, and a camera 1o. Slice the image signal at a constant level (voltage)■
a comparator 14 that compares and converts the data into binary data, a serial/parallel converter 16 that converts the serial data from the comparator 14 into parallel data, an image memory 18 that stores the converted parallel data, and an address counter. 20
It is composed of etc. These are the clock signal CLK
It is synchronized and works.

As shown in FIG. 4, in the analog image signal regarding the circuit board obtained from the camera 10, a low level output indicating a conductor pattern portion and a high level output indicating a clearance portion appear alternately. This image signal is compared in a comparator 14 with a slice level V, which is preset as the center value of the above-mentioned high and low level outputs in a slice level generator 12, and depending on the magnitude relationship between the two, it indicates, for example, a conductor pattern section.
It is classified into binary data of 'OJ' indicating IJ or clearance part. This binary data is input as serial data to the serial/parallel converter 16, where it is converted into 8-bit or 1-bit data.
The data is converted into 6-bit parallel data and stored in the image memory 18.

[Problems to be Solved by the Invention] However, in such a device, large cracks a on the conductor pattern and obvious dirt b in the clearance part can be detected because they cross the slice level V, but fine cracks on the conductor pattern can be detected. In case C, the shadow was dark, and the minute dirt d on the clearance could not be detected due to the low contrast, resulting in low detection accuracy.

An object of the present invention is to eliminate the drawbacks of the prior art as described above, and to change the slice level to two levels in real time corresponding to the conductor pattern portion and clearance portion of a circuit board to be inspected.
An object of the present invention is to provide a circuit board defect detection device that can detect even minute defects reliably by changing the steps.

[Means for Solving the Problems] The present invention, which can achieve the above-mentioned objects, has a first slice level close to the normal signal level obtained from the conductor pattern portion on the circuit board and a clearance portion. a slice level generator that generates a second slice level close to the normal signal level obtained from the second slice level; a template pattern memory for pattern matching; This is a circuit board defect detection device equipped with a switch circuit that selectively controls one of the levels.

To switch the slice level here, it is also possible to provide two comparators, apply the image signal to each comparator, binarize it at a different slice level, and switch each output with a switch circuit, or use a single comparator. Alternatively, the slice level may be switched by a switch circuit and supplied to the comparator.

[Function] The template pattern memory for pattern matching stores the shapes of the conductor pattern portion and the clearance portion of the circuit board, and checks whether the analog image signal obtained from the camera indicates the conductor pattern portion or the clearance portion. It is read out whether it is the one indicated. The switch circuit is controlled by this read data, selects one slice level, takes out one piece of binary data from the comparator,
Store in image memory.

In the present invention, for example, when detecting a conductor pattern part, the reslicing level is lowered as much as possible, and when detecting a clearance part, the slicing level is raised as much as possible. The slice level is switched between two levels in real time according to the image input signal, and the image input signal is converted into binary data and stored in the image memory. This makes it possible to accurately and reliably detect even minute defects such as minute cracks in the conductor pattern section and small stains in the clearance section.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a circuit board defect detection apparatus according to the present invention. This device includes a camera 10 that converts an image of an RGJ road board, which is an object to be measured, into an electrical signal.
, first and second comparators 24a and 24b to which analog image signals obtained thereby are supplied in parallel, and first and second slices to which different slice levels (voltages) are respectively applied to both comparators 24a and 24b. Level generators 22a, 22b and both comparators 24
a switch circuit 32 that switches the outputs of 24a and 24b, a serial-parallel converter 26 that converts the serial binarized data selected by the switch circuit 32 into parallel data, and an image memory 28 that stores the converted parallel data. , an address counter 30 that controls the image memory 28, a preceding address counter 34, a template pattern memory 36 that can be accessed in parallel with the image memory 2B, and stores read data from the template pattern memory 36. A parallel-to-serial converter J8 that controls the switch circuit 32 is provided.

The difference between the present invention and the prior art is that, as shown in FIG. 2, the first slice level generator 22a generates a slice level vl that is slightly higher than the normal signal level of the conductor pattern on the circuit board. , the second slice level generator 22b generates a slice level (2) that is slightly lower than the normal signal level of the clearance portion on the circuit board, and controls the switch circuit 32 with data read from the template pattern memory 36; The point is that one of the slice levels is selected depending on the inspection location.

The actual operation is performed in the following steps. Regular image data of a circuit board, which is an object to be inspected, is written in the template pattern memory 36 in advance for pattern matching.

The image signal from the camera 10 is transmitted to both comparators 24a,
24b respectively slice level generators 22a, 2
The predetermined slice levels V, ,V, sent from 2b
'IJ or' depending on their size
It is converted into OJ binary data. These binarized data are stored in the image memory 28 and in parallel in the switch circuit 32.
Selection is controlled by a serial signal obtained by converting read data from the template pattern memory 36 accessed in a column by a parallel-to-serial converter 38. That is, if the part being inspected is a conductor pattern part, the output of the first comparator 24a is selected, and if the part being inspected is a clearance part, the output of the second comparator 24b is selected. In this way, only one piece of binary data is extracted and supplied to the serial/parallel converter 2G.

Note that the address counter 30 and the preceding address counter 34
A phase difference is provided for the operation. This means that the camera 10 is 1 when data is stored in the image memory 28.
This is because the image data of ~2 bytes ahead is output, and it is necessary to advance the image data by 1~2 bytes. The serial-to-parallel converter 26 converts the serially sent binary data into 8
The data is converted into bit or 16-bit parallel data and stored in the image memory 28.

As is clear from FIG. 2, according to the present invention, two slice levels V, , V! are controlled by the template pattern memory 36 corresponding to the matching pattern. is set close to the normal signal level, large cracks (a) and noticeable stains (b) are caused by heat, while minute cracks (C) in the conductor pattern and slight stains (d) in the clearance area are caused by heat.
Thus, even minute defects can be detected accurately and reliably.

Note that in the above embodiment, two comparators are installed in parallel, and the output from both corresponding slice level generators is 2.
Valued data is selected and controlled by a switch circuit, but a single comparator is used, the output of a slice level generator is supplied to the switch circuit, and one slice level selected by the switch circuit is The signal may be configured to be supplied to a comparator.

Although a camera is used to obtain image signals, an image input device such as a line image sensor may also be used.

[Effects of the Invention] As described above, the present invention provides two
The switch circuit is controlled by the read data from the template pattern memory, and the image signal is binarized by switching to one of the two slice levels. It has an excellent effect of accurately and reliably detecting even if there are large cracks or slight dirt in the clearance area.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the circuit board defect detection device according to the present invention, FIG. 2 is a waveform diagram showing its configuration operation, and FIG. 3 is a block diagram showing an example of the prior art. FIG. 4 is a waveform diagram showing the operation. lO...Camera, 22a, 22b...Slice level generator, 24a, 24b...Comparator, 26...Serial to parallel converter, 28...Image memory...
30...Address counter, 32...Switch circuit, 34...Preceding address counter, 36...Template pattern memory, 3rd...Parallel-serial converter. Patent applicant Iwaki Denshi Co., Ltd. Agent Shigeru Estimate Figure 1 6th Figure 2 Location of circuit board Figure 3 Figure 4 Location of circuit board

Claims (1)

[Claims] 1. In an apparatus equipped with a comparator that compares an image signal from a circuit board that is an object to be inspected with a predetermined slice level and converts it into binary data, and an image memory that stores the binary data from the comparator. , a slice level generator that generates a first slice level close to the normal signal level obtained from the conductor pattern portion on the circuit board and a second slice level close to the normal signal level obtained from the clearance portion; Defect detection for a circuit board, comprising a template pattern memory for pattern matching, and a switch circuit for selectively controlling one of the two slice levels according to data read from the template pattern memory. Device.