JP2821047B2 - Setting method of binarization threshold - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of setting a threshold value used for inspecting a wiring pattern of a printed circuit board and binarizing a board signal obtained by reading the wiring pattern.

[0002]

In the inspection of the Prior Art] printed circuit board, pudding
The images collected by the substrate and the binarization process by the image processing wiring path
In many cases, an image of the turn is obtained and various inspections are performed on the image. In this binarization process, distribution
It is particularly important to determine an appropriate binarization threshold value for discriminating a line pattern from other regions . Many methods have been proposed for determining the binarization threshold.
For example, a method is employed in which the number of pixels included in the grayscale image is obtained as a frequency distribution for each gradation value, and the gradation value that minimizes the frequency is determined as a binarization threshold.

FIG. 8 (a) shows an example thereof.
In the inspection of a wiring pattern of a printed circuit board, the intensity of light reflected from the board is converted into a signal having an 8-bit gradation value, and the frequency distribution for the gradation value of the pixel is examined (histogram). The peaks generated on the high gradation value side indicate the presence of a wiring pattern with high reflection intensity, and the peaks generated on the low side indicate the presence of through holes (through holes) and base materials with low reflection intensity. . And when it is desired wiring pattern to obtain a binarized data small tone value T ₁ of the frequency of the reflected intensity is employed as a binarization threshold.

[0004]

However, as will be described later, since the wiring pattern inspection is performed using light transmitted through the through holes of the substrate, the substrate is mounted on a transparent stage such as glass. Are often inspected. In such a case, not only from the substrate, but also at a portion where the substrate is not mounted, or through a through hole of the substrate,
Light may be reflected by the stage.

[0005] The reflection by this stage generates reflected light of a certain intensity, although not as much as that of the wiring pattern. Therefore, as shown in FIG. 8B, a mountain which is parasitic on the curve of FIG. 8A is observed. (The broken line shows the curve of FIG. 8A). Then gradation value frequency is less reflective intensity T _2, and the larger than the gradation value T ₁ to be originally set as the binarization threshold, to optimize the binary image of the wiring pattern on the substrate There was a problem that it was not possible.

Further, due to the configuration of the reading means, there is a phase shift between the data of the pattern image read using the reflected light and the data of the hole image read using the transmitted light.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain an optimal binarization threshold.

[0008]

According to the present invention, there is provided a method for setting a binarization threshold value comprising the steps of: (a) a substrate having first and second main surfaces and a through hole, having a relatively low reflectance and a light shielding property; A substrate having a pattern having a relatively high reflectance on the first main surface is placed on a stage having a light-transmitting property, and (b) a first light source receives the first main surface. Irradiating the first main surface with light, converting the intensity of the light reflected by the first main surface into an electric signal, and obtaining a substrate signal indicating an image of the first main surface, (c) The second light source irradiates the second main surface with the second light, and the intensity of the transmitted light of the second light transmitted through the area of the stage where the substrate is not mounted and the through hole. Is converted into an electric signal to obtain a hole signal indicating an image of the area and the through hole. Obtaining a binary Hall signal by binarizing the Le signal. (E) delaying the binarized Hall signal by a predetermined amount to obtain a delayed Hall signal; (f) logically synthesizing the substrate signal and the delayed Hall signal, and A correction signal obtained by masking the substrate signal is obtained. And (g) creating a histogram relating to the reflection intensity of the first main surface from the correction signal, and (h)
A binarization threshold for binarizing the substrate signal is set from the histogram.

Preferably, the steps (b) and (c) are performed by a plurality of reading means, and the predetermined amount of the delay in the step (e) is set for each of the reading means.

[0010]

According to the present invention, a correction signal is generated by masking the effect of light reflected on an area of the stage where the substrate is not mounted and the through hole on the substrate signal by the delay Hall signal. By creating a histogram using this correction signal, it is possible to obtain a binarization threshold almost equal to the case where there is no light reflected from the stage.

Further, since the delay Hall signal is binarized, it can be easily delayed by a predetermined amount, and the correction signal can be generated in the same phase as the substrate signal.

[0012]

【Example】

A. FIG. 2 is a schematic diagram of an optical wiring pattern reading device 100 used in an embodiment of the present invention.

The reading device 100 includes red LEDs 111 and 1
First light source 110 composed of 12, 113, infrared LED
A (second light source) 120, a lens system 140, a cold mirror 150, a reflected light image sensor 161, and a transmitted light image sensor 162 are provided.

On the other hand, a translucent stage 15 on which a substrate 20 to be inspected is mounted is interposed in the reading device 100. The stage 15 moves in the forward and reverse directions in two directions perpendicular to each other in a plane parallel to itself, so that the reading device 100 can read the entire upper surface of the substrate 20 placed on the stage 15. .

This will be described with reference to FIG. 3 which is a schematic plan view. By moving the stage 15 in the sub-scanning direction (± Y direction), the reading device 100 can relatively scan the printed circuit board 20 for reading.

When there are a plurality of reading devices 100, it is difficult to provide them adjacently without any gap, and they are located apart as shown in the figure. Further, when the number of the reading device 100 is one, the entire surface of the printed circuit board 20 cannot be read by one scan. Therefore, even the reader 100 is a plurality Even singular, in order to obtain a substrate signal PS ₀ over the entire surface of the printed circuit board 20, once the + Y direction (or the -Y direction) in the scanning ( After the forward scanning, the stage 15 is moved in the main scanning direction (± X direction). Then, scanning is performed in the −Y direction (or + Y direction) (backward scanning), and an area that cannot be read in the forward scanning is read. FIG. 3 exemplifies the relative strokes read by the third reading device 100 from the right with arrows.

Returning to FIG. 2, light emitted from the first light source 110 is reflected by the wiring pattern 22 and the base material 21 formed on the first main surface of the substrate 20, and passes through the lens system 140 to be cold. The mirror 150 is reached. Cold mirror 15
Since 0 transmits infrared light but does not transmit red light,
The light reflected on the first main surface side of the substrate 20 is further reflected by the cold mirror 150 and enters the reflected light image sensor 161 as reflected light LR. Image sensor for reflected light 1
61 converts the intensity of the reflected light LR into a substrate signal PS ₀ which is an electrical signal.

On the other hand, light emitted from the second light source 120 located on the second main surface side of the substrate 20 passes from the back surface 15a of the stage 15 to the front surface 15b, and passes through a through hole (through hole) 25 provided in the substrate 20. Through the lens system 1 or from an area (not shown) where the substrate 20 is not mounted.
Reaches 40. This light is infrared light.
The transmitted light 50 passes through the transmitted light LT and enters the transmitted light image sensor 162. The transmitted light image sensor 162 includes:
The intensity of the transmitted light LT is converted into a Hall signal HS which is an electrical signal.
Convert to ₀ . The board signal PS ₀ and the hole signal HS ₀ are used for detecting the wiring pattern 22 and the through hole 25, respectively.

However, the substrate signal PS ₀ and the hall signal HS
_{A value of 0} does not mean that the same location is always detected on the printed circuit board to be inspected. Image sensor 16
Due to the mounting error of 1,162, a certain reading device 100
In some cases, the substrate signal PS ₀ may precede the hall signal HS ₀ (the information in the direction opposite to the stage moving direction is preempted). In another reading apparatus 100, the hall signal HS ₀
There is sometimes precedes the substrate signal PS _0. Whichever comes first also reverses depending on whether the stage 15 is forward or backward in the sub-scanning direction, that is, whether it is forward scanning or backward scanning.

B. FIG. 1 shows a pattern 2 used in an embodiment of the present invention.
FIG. 3 is a block diagram of a value processing unit 200; The pattern binarization processing unit 200 generates a signal PIS obtained by binarizing the image of the substrate using an optimal binarization threshold based on the substrate signal PS ₀ and the hall signal HS ₀ obtained from the reading device 100. I do. The signal PIS is thereafter subjected to a pattern break inspection or the like depending on the purpose.

The A / D converter 210 and 220 respectively substrate signal PS _0, and a Hall signal HS ₀ converted A / D, digitize substrate is a digital signal having a tone value of the example 8 bits (= 256) A signal PS and a digitized hall signal HS are obtained.

The substrate signal PS is supplied to the mask processing units 230 and 2
It is sent to the value conversion circuit 270. In the binarization circuit 270,
The signal PIS is generated by binarizing the substrate signal PS with an optimal binarization threshold T obtained as described later.

The hall signal HS is binarized by the binarization processing section 240 to become a binarized hall signal HIS. This signal HIS is an image P generated by the substrate signal PS.
The hole portion H of I is designated, and is distinguished from other non-hole portions NH (FIG. 4). As will be described later in detail, in the mask processing unit 230, the hole H
Is set to a predetermined value, an unnecessary signal of a portion where light is reflected by the stage 15 in a portion where the substrate 20 is not mounted or through a through hole 25 of the substrate 20 is set. And the correction signal C
S can be generated.

Now, in the reading apparatus 100, the Hall signal HS is generated due to the mounting error of the image sensors 161, 162.
₀ precedes the substrate signal PS ₀ (reading device 10
When 0 is singular, scanning is performed in such a direction). The substrate signal PS ₀ to be masked is delayed from the hole signal HS ₀ , and even if the binarized hole signal HIS is sent to the mask processing unit 230 as it is, the portion of the substrate signal PS to be masked is correct. Not masked. Therefore, the binarized Hall signal HIS
Is once sent to the phase correction unit 280 to become a delayed Hall signal HDS whose phase is matched with the substrate signal PS, and then sent to the mask processing unit 230. The amount of phase to be delayed in the phase correction unit 280 can be easily set for each reading device 100 by measuring the attachment error in advance.

On the other hand, in the reading device 100, the substrate signal P
For those in which S ₀ precedes the hall signal HS ₀ (when the reading apparatus 100 is singular, scanning is performed in such a direction), the delayed hall signal HDS is not generated. This is because the phase cannot be matched with the substrate signal PS even if the delay is performed. In this case, the mask processing section 230 also does not generate the correction signal CS.

As described above, which of the substrate signal PS and the hall signal HS precedes, that is, whether the correction signal CS is generated or not depends on whether the moving direction of the stage 15 is normal or reverse. I do.

The histogram creating section 250 creates a histogram G by plotting the frequency of pixels for each gradation value from the correction signal CS. The binarization threshold setting unit 260 obtains, for example, a gradation value T that minimizes the frequency based on the histogram G, and sets this as a binarization threshold.

Next, the operation of the processing units 230 and 240 will be described in detail. First, the binarization processing unit 240 binarizes the Hall signal HS with a certain threshold TH _h. A region having a value greater than the threshold TH _h is determined that the hole portion H, to determine the other portions to be non-hole portions NH (hole portion H is not only part corresponding to the through hole 25, the substrate An area on the stage 15 where the stage 20 is not placed is also included.) FIG. 4 shows the relationship between the Hall signal HS read on the line AA ′ and the substrate 20.

FIG. 5 shows the relationship between the substrate signal PS and the substrate 20.
This is shown in the same manner as FIG. Through hole 25
Corresponding to the position, there is a reflected signal RF resulting from the reflection of light by the stage 15. Such a reflected signal RF
Is caused by the stage front surface 15b and the back surface 15a with respect to the first light source 110, and thus occurs in a region on the stage 15 where there is no light shielding, that is, a region determined to be the hole H. Therefore, in the delayed Hall signal HDS having information on whether the place of interest is the hole H or the non-hole NH, the reflected signal R
The region where F occurs can be masked.

More specifically, for example, in the mask processing section 230, the logical product of the substrate signal PS and the inverted signal of the delay Hall signal HDS may be obtained. In such a case, the mask processing unit 230 can be configured only by including the AND circuit 231 as shown in FIG. In the correction signal CS, the value of the signal corresponding to the hole portion H is “0”, and a signal indicating the wiring pattern 22 with the influence of the reflection signal RF suppressed can be obtained.

In the correction signal CS, the value of the signal corresponding to the hole portion H is not limited to "0", and takes another value that makes it easy to determine the binarization threshold T from the histogram G generated later. You can also do so. In this case, a predetermined value (corresponding to the gradation value) is output only when the delay hall signal HDS is “1” (corresponding to the hole portion H), and “0” (corresponding to the non-hole portion NH). In the case of ()), the mask processing unit 230 can be configured using a multiplexer that outputs the substrate signal PS.

C. Shows a histogram G of the reflection intensity when the Configuration Figure 7 Generation and binarization threshold histogram set the value at the hole part H of the correction signal CS to T _3. Such a histogram G is obtained by counting the frequency distribution of the reflection intensity for each gradation value. Since the gradation value at the hole H is set to T ₃ , the histogram G has the gradation value T
₃ has one peak, but if the gradation value T ₃ is kept sufficiently small, the shape of the histogram in the vicinity of the gradation value T ₁ will not be affected, and therefore, as shown in FIG. A gradation value T ₁ ′ almost equal to the gradation value (binarization threshold) T ₁ set for the ideal histogram can be set as the binarization threshold.

In many cases, the histogram G is not necessarily created over the entire printed circuit board to be inspected. This is because the data (correction signal CS) for creating the histogram G is given only when the hall signal HS ₀ precedes the substrate signal PS ₀ as described above. However, 2 determined from the histogram G created in this way.
Using the binarization threshold, the board signal P of the entire printed board 20
Even if a binarized signal for binarizing S is determined, the problem shown in FIG. 8B can be avoided. This is because the relationship between the reflection intensity distributions of the reflected light from the wiring pattern and the reflected light from the stage 15 does not greatly differ depending on the position of the printed circuit board 20.

[0034]

As described above, according to the method for setting the binarization threshold value of the present invention, the correction signal is obtained by masking the substrate signal with the delay hall signal delayed to match the phase with the substrate signal. Is generated, so that accurate mask processing can be performed. Further, a histogram relating to the reflection intensity of the first main surface is created based on the correction signal, and a binarization threshold value is set from this histogram, so that the image of the first main surface of the substrate on which the pattern is provided is set to 2. When the value is converted, the influence of light reflected by the stage from a region where the substrate is not mounted or through a through hole can be removed.
Further, in the present invention, since a binarized Hall signal is used to obtain a delayed Hall signal, a delayed Hall signal can be obtained more easily than when a multilevel signal is delayed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a pattern binarization processing unit 200 used in one embodiment of the present invention.

FIG. 2 is a schematic view of an optical wiring pattern reader 100 used in one embodiment of the present invention.

FIG. 3 is a schematic plan view showing a positional relationship between the reading device 100 and a substrate 20.

FIG. 4 is a diagram showing a relationship between a hall signal HS and a through hole 25;

FIG. 5 is a diagram showing a relationship between a substrate signal PS and a reflected signal RF due to reflection from a stage 15.

FIG. 6 is a circuit diagram showing a configuration of a mask processing unit 230.

FIG. 7 is a diagram showing a histogram G;

FIG. 8 is an explanatory diagram showing a conventional technique.

[Explanation of symbols]

Reference Signs List 15 Stage 20 Printed circuit board 22 Wiring pattern 25 Through hole 110 First light source 120 Second light source 210, 220 A / D conversion unit 230 Mask processing unit 240 Binarization processing unit 250 Histogram creation unit 260 Binarization threshold setting unit PS ₀ substrate signal PS Digitized substrate signal HS ₀ Hall signal HS Digitized Hall signal HIS Binary Hall signal HDS Delayed Hall signal CS Correction signal G Histogram T Binarization threshold

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H04N 1/403 H04N 1/40 103A (58) Fields investigated (Int.Cl. ⁶ , DB name) G06T 7/00 G06T 1 / 00 G06T 5/00 H04N 1/40 G01B 11/00 G01N 21/88

Claims (2)

(57) [Claims] (A) a substrate having first and second main surfaces and a through hole, having relatively low reflectivity and having a light-shielding property, and further having a relatively high reflectivity at the first main surface; Placing a substrate having a high pattern on a light-transmitting stage; and (b) irradiating the first main surface with first light from a first light source, Converting the intensity of the light reflected by the surface into an electrical signal to obtain a substrate signal indicating an image of the first main surface; and (c) applying a second light source from the second light source to the second main surface. And irradiating the area and the through hole by converting the intensity of the transmitted light of the second light transmitted through the area of the stage where the substrate is not mounted and the through hole into the electric signal. Obtaining a hall signal indicating an image of the hole; and (d) binarizing the hall signal to obtain a binarized hall signal. (E) delaying the binarized Hall signal by a predetermined amount to obtain a delayed Hall signal; (f) logically synthesizing the substrate signal and the delayed Hall signal, Obtaining a correction signal obtained by masking the substrate signal with the delay Hall signal; (g) generating a histogram relating to the reflection intensity of the first main surface from the correction signal; and (h) obtaining the histogram from the histogram. Setting a binarization threshold value for binarizing the substrate signal. 2. The method according to claim 1, wherein the steps (b) and (c) are performed by a plurality of reading units, and the predetermined amount in the step (e) is set for each of the reading units. How to set the value threshold.