JPS6327867B2 - - Google Patents
Info
- Publication number
- JPS6327867B2 JPS6327867B2 JP54169331A JP16933179A JPS6327867B2 JP S6327867 B2 JPS6327867 B2 JP S6327867B2 JP 54169331 A JP54169331 A JP 54169331A JP 16933179 A JP16933179 A JP 16933179A JP S6327867 B2 JPS6327867 B2 JP S6327867B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- mask
- layer
- conductivity type
- semiconductor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims description 18
- 239000003990 capacitor Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
Description
【発明の詳細な説明】
本発明は半導体接合可変容量装置（バリキヤツ
プ）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor junction variable capacitance devices (varicaps).
半導体の表面の超階段接合を利用した可変容量
装置を製造する場合、例えば第１図ａに示すよう
にn+Si（シリコン）基板（ウエハ）１の上にエピ
タキシヤルn-層２を形成し、このn-層表面に
SiO2マスク３を通してＰ（リン）、As（ヒ素）等の
ドナ不純物をイオン打込みしてn+領域４を形成
し、次いで同図ｂのように新たに形成したSiO2
マスク５を通してＢ（ホウ素）等のアクセプタを
拡散してp+領域６を形成する。このp+領域６は
n+領域４よりも拡散深さが浅くつくられ、両者
の間のpn接合が容量として利用される。この半
導体接合の断面における不純物濃度分布は第２図
のように示され、pn接合に対して逆バイアスを
かけた場合に超階段状のＣ−Ｖ特性を得ることに
なる。 When manufacturing a variable capacitance device using a superstep junction on the surface of a semiconductor, for example, as shown in FIG. 1a, an epitaxial n - layer 2 is formed on an n + Si (silicon) substrate (wafer) 1. , on this n - layer surface
Donor impurities such as P (phosphorous) and As (arsenic) are ion-implanted through the SiO 2 mask 3 to form the n + region 4, and then the newly formed SiO 2
A p + region 6 is formed by diffusing an acceptor such as B (boron) through a mask 5 . This p + region 6 is
The diffusion depth is made shallower than that of the n + region 4, and the pn junction between the two is used as a capacitor. The impurity concentration distribution in the cross section of this semiconductor junction is shown in FIG. 2, and when a reverse bias is applied to the pn junction, a super-step-like CV characteristic is obtained.
このような半導体接合容量装置において、p+
拡散領域６がn+拡散領域４よりも内側に形成さ
れるとその表面不純物濃度が高いために耐圧が小
さいものとなる。例えば1SV70の場合、第１図
ａ，ｂを参照し、窓穴の幅ａ＝180μmのマスクを
用いてn+拡散を行ない、その後ｂ＝190μmのマス
クの目合せを行なつてp+拡散を行なう。しかし
ながらマスク合せの誤差をなくすためｂ−ａの差
ｃを大きくするとn+領域からのp+領域のはみ出
し部分８が大きくなりその部分の容量はバリキヤ
ツプの容量変化比を減少させる浮遊容量であり、
このため高周波直列抵抗Rsが設計上不利になる
という結果を招くことになつた。 In such a semiconductor junction capacitor device, p +
If the diffusion region 6 is formed inside the n + diffusion region 4, its surface impurity concentration will be high, resulting in a low breakdown voltage. For example, in the case of 1SV70, referring to Figure 1 a and b, perform n + diffusion using a mask with window hole width a = 180 μm, then align the mask with b = 190 μm and perform p + diffusion. Let's do it. However, if the b-a difference c is increased to eliminate errors in mask alignment, the protruding portion 8 of the p + region from the n + region becomes larger, and the capacitance of that portion is a stray capacitance that reduces the capacitance change ratio of the varicap.
This resulted in the high frequency series resistance R s being disadvantageous in terms of design.
本発明は上記した問題点を解決するためになさ
れたものであり、その目的はホトエツチング工程
を少なくしてしかも耐圧、歩留りを向上できる半
導体接合容量装置の製造方法を提供することにあ
る。 The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a method of manufacturing a semiconductor junction capacitor device that can reduce the number of photo-etching steps and improve breakdown voltage and yield.
その目的達成のための本発明の要旨は、第１導
電型高比抵抗半導体領域（例えば、n-エピタキ
シヤル層）の表面に酸化膜よりなり、窓開部を有
する単一のマスクを通して第１導電型不純物をイ
オン打込みすることにより前記半導体領域と同じ
導電型の低比抵抗の第１領域を形成し、次いで前
記マスク表面のエツチングを行うことにより前記
イオン打込みによつて損傷を受けた前記マスクの
表面層及び前記窓開部の側面層を除去し、その後
前記マスクを通して第２導電型不純物を前記半導
体領域表面に導入することを特徴とする半導体接
合容量装置の製造方法にある。 The gist of the present invention for achieving this purpose is to apply a first conductivity type high resistivity semiconductor region (for example, an n-epitaxial layer) through a single mask made of an oxide film and having a window opening on the surface of the first conductivity type high resistivity semiconductor region (for example, an n - epitaxial layer). A first region of the same conductivity type and low resistivity as the semiconductor region is formed by ion-implanting conductivity-type impurities, and then the mask surface damaged by the ion implantation is removed by etching the mask surface. The method of manufacturing a semiconductor junction capacitor device is characterized in that the surface layer and the side layer of the window opening are removed, and then a second conductivity type impurity is introduced into the surface of the semiconductor region through the mask.
第３図ａ〜ｃは本発明の一実施例を半導体接合
容量装置の製造プロセスにそつて示すものであ
る。 3a to 3c show an embodiment of the present invention along the manufacturing process of a semiconductor junction capacitor device.
(a) n+Si基板（ウエハ）１上にエピタキシヤル
n-層２を成長させたものを用意し、表面の酸
化膜（SiO2）３をホトエツチ処理して一辺の
長さa180μm角の窓開部を有するマスクとし、
Ｐ（リン）又はAs（ヒ素）等のドナ不純物のイ
オン打込みによりn-Si層表面にn+領域４を形
成する。このイオン打込みの際にイオンはSi層
表面のみならず酸化膜の側面にも打込まれ深さ
0.2〜0.4μmのダメージ（損傷）層７がつくられ
る。(a) Epitaxial on n + Si substrate (wafer) 1
Prepare a layer on which the n - layer 2 has been grown, and photo-etch the oxide film (SiO 2 ) 3 on the surface to make a mask having a window opening with a side length a of 180 μm square.
An n + region 4 is formed on the surface of the n - Si layer by ion implantation of a donor impurity such as P (phosphorus) or As (arsenic). During this ion implantation, ions are implanted not only on the surface of the Si layer but also on the sides of the oxide film, resulting in a deep
A damage layer 7 of 0.2 to 0.4 μm is created.
(b) 次にフツ酸系エツチ液により酸化膜の全面を
かるくエツチ（ライトエツチ）する。ところで
前工程のイオン打込みでダメージを受けた酸化
膜表面のダメージ層７はそれを受けない部分の
エツチ速度より数倍速いエツチ速度で侵され
る。そこでウエハを短時間エツチするとダメー
ジ層は急速にエツチされ、ダメージを受けない
部分が現れるとエツチ速度は緩やかになり、従
つてマスク開口部側面ではエツチ完了後180μm
よりもダメージ層部分c′だけサイドエツチが進
行する。(b) Next, lightly etch the entire surface of the oxide film using a hydrofluoric acid etchant (light etch). By the way, the damaged layer 7 on the surface of the oxide film, which has been damaged by the ion implantation in the previous step, is etched at an etch rate several times faster than the etch rate of the portion that is not damaged. Therefore, when the wafer is etched for a short time, the damaged layer is rapidly etched, and when undamaged areas appear, the etching speed slows down.
The side etch progresses by more than the damaged layer portion c'.
(c) ライトエツチ後の酸化膜３′をそのままマス
クとしてＢ（ホウ素）拡散を行ないp+拡散領域
６′を形成する。前の(b)工程で酸化膜のダメー
ジを受けた部分がc′＝0.5〜1.0μmだけサイドエ
ツチされているため、マスクの開口部の幅b′は
c′分だけ広がることになり、p+領域６′のn+領
域４よりのはみ出し部分８は極くわずかですむ
ことになる。(c) Using the light-etched oxide film 3' as a mask, B (boron) is diffused to form a p + diffusion region 6'. Since the damaged part of the oxide film in the previous step (b) is side-etched by c′ = 0.5 to 1.0 μm, the width b′ of the mask opening is
It is expanded by c', and the protruding portion 8 of the p + region 6' from the n + region 4 is extremely small.
以上実施例で述べた本発明によれば、(1)p+領
域のn+領域よりのはみ出し部分がイオン打込み
時のダメージ層の幅に限定されるため、はみ出し
たp+拡散層により浮遊容量を減少させることが
でき、したがつてRsの改良の効果は大きい、(2)
p+拡散のためのホトエツチ工程が不要であり、
セルフアライン化ができる、(3)従来は２回のホト
エツチによるマスク工程のためマスク位置決め誤
差を考慮し、p+拡散のはみ出し量を大きくとる
必要があつたが、本発明でははみ出し量を限定で
きしかも確実にできる、(4)上記(1)〜(3)より耐圧歩
留りを向上し製造原価低減できる等の諸効果が得
られる。さらに本発明によれば、単一の酸化膜マ
スクでセルフアラインができるので製造工程等を
単純化することができる。 According to the present invention described in the above embodiments, (1) the protruding portion of the p + region from the n + region is limited to the width of the damaged layer during ion implantation, so the stray capacitance is caused by the protruding p + diffusion layer. Therefore, the effect of improving R s is large, (2)
No photoetch step is required for p + diffusion,
(3) In the past, the mask process involved two photo-etches, so it was necessary to take mask positioning errors into account and increase the amount of protrusion of the p + diffusion, but with the present invention, the amount of protrusion can be limited. Moreover, various effects such as (4) improvement in pressure yield and reduction in manufacturing cost from the above (1) to (3) can be obtained. Further, according to the present invention, self-alignment can be performed using a single oxide film mask, so that the manufacturing process etc. can be simplified.
本発明は前記実施例に限定されない。例えば半
導体領域の導電型を逆にする場合も同様に実施で
きる。 The invention is not limited to the above embodiments. For example, the conductivity type of the semiconductor region can be reversed in the same manner.
第１図ａ，ｂは在来の半導体接合容量装置の製
造プロセスの一部工程の断面図、第２図は半導体
接合容量装置の不純物濃度分布曲線図、第３図ａ
〜ｃは本発明による半導体接合容量装置の製造プ
ロセスの一部工程の断面図である。
１……n+基板、２……エピタキシヤルn-層、
３……酸化膜マスク、４……n+拡散（イオン打
込み）領域、５……新たな酸化膜マスク、６……
p+拡散領域、７……ダメージ層、８，８′……は
み出し部分。
Figures 1a and b are cross-sectional views of some steps in the manufacturing process of a conventional semiconductor junction capacitor device, Figure 2 is an impurity concentration distribution curve diagram of a semiconductor junction capacitor device, and Figure 3a
-c are cross-sectional views of some steps in the manufacturing process of the semiconductor junction capacitor device according to the present invention. 1...n + substrate, 2...epitaxial n - layer,
3... Oxide film mask, 4... n + diffusion (ion implantation) region, 5... New oxide film mask, 6...
p + diffusion region, 7... Damage layer, 8, 8'... Protruding portion.
Claims (1)
膜よりなり、窓開部を有する単一のマスクを通し
て第１導電型不純物をイオン打込みすることによ
り前記半導体領域と同じ導電型の低比抵抗の第１
領域を形成し、次いで前記マスク表面のエツチン
グを行うことにより前記イオン打込みによつて損
傷を受けた前記マスクの表面層及び前記窓開部の
側面層を除去し、その後前記マスクを通して第２
導電型不純物を前記半導体領域表面に導入するこ
とを特徴とする半導体接合容量装置の製造方法。1 A first conductivity type impurity is ion-implanted into the surface of the first conductivity type high resistivity semiconductor region through a single mask made of an oxide film and having a window opening, thereby forming a low resistivity semiconductor region of the same conductivity type as the semiconductor region. 1st of
forming a region and then etching the mask surface to remove the surface layer of the mask damaged by the ion implantation and the side layer of the window opening;
A method for manufacturing a semiconductor junction capacitor device, comprising introducing a conductive impurity into the surface of the semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16933179A JPS5694673A (en) | 1979-12-27 | 1979-12-27 | Semiconductor junction capacity device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16933179A JPS5694673A (en) | 1979-12-27 | 1979-12-27 | Semiconductor junction capacity device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5694673A JPS5694673A (en) | 1981-07-31 |
| JPS6327867B2 true JPS6327867B2 (en) | 1988-06-06 |
Family
ID=15884560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16933179A Granted JPS5694673A (en) | 1979-12-27 | 1979-12-27 | Semiconductor junction capacity device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5694673A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5896774A (en) * | 1981-12-04 | 1983-06-08 | Mitsubishi Electric Corp | Manufacture of super-stepped type junction diode |
| JPS5976422A (en) * | 1982-10-26 | 1984-05-01 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6459874A (en) * | 1987-08-31 | 1989-03-07 | Toko Inc | Manufacture of variable-capacitance diode |
| US5017950A (en) * | 1989-01-19 | 1991-05-21 | Toko, Inc. | Variable-capacitance diode element having wide capacitance variation range |
| US4987459A (en) * | 1989-01-19 | 1991-01-22 | Toko, Inc. | Variable capacitance diode element having wide capacitance variation range |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826480A (en) * | 1971-08-11 | 1973-04-07 | ||
| JPS5269266A (en) * | 1975-12-08 | 1977-06-08 | Fujitsu Ltd | Production of semiconductor device |
-
1979
- 1979-12-27 JP JP16933179A patent/JPS5694673A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826480A (en) * | 1971-08-11 | 1973-04-07 | ||
| JPS5269266A (en) * | 1975-12-08 | 1977-06-08 | Fujitsu Ltd | Production of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5694673A (en) | 1981-07-31 |
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