JPS5896774A - Manufacture of super-stepped type junction diode - Google Patents

Abstract

PURPOSE:To obtain the super-stepped type junction diode having no deterioration in reverse withstand voltage and a creeping phenomenon by a method wherein after an N<+> type ion implanted layer has been formed using an SiO2 film having an aperture in an N<-> type layer which was grown on a semiconductor substrate, the aperture is widened in width and a P<+> type diffusion layer is formed at the surface layer part of the ion implantation layer in such a manner that it is overhanged into the N<-> type layer. CONSTITUTION:An N<-> type layer 2 is epitaxially grown on an N<++> type Si substrate 1, a thick SiO2 film 3 is generated on the surface layer part of the layer 2 by performing a heat treatment, and an aperture is provided in the center part of the film 3. Then, an N<+> type implanted layer 4 is formed by implanting an ion into the layer 2, which is exposed on the inside of the aperture, using the film 3 as a mask, the SiO2 film 3' which was grown on the layer when the ion implantation is performed is removed and, at the same time, the aperture provided on the film 3 is widened in width. Subsequently, a P<+> type layer 5 is formed by diffusion on the surface layer part of the layer 4 using the widened aperture 5'' in such a manner that the layer 5 will be overhanged into the layer 2, and the super-stepped junction diode is composed of layers 2, 4 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a super-step junction diode.

In general, super-stepped junction diodes are widely used as variable capacitance elements for frequency matching in televisions, radios, and other communication devices by utilizing the capacitance-bias characteristics of pariscapacitor diodes.

In order to manufacture this diode, the following two steps were conventionally required.
Two methods have been adopted. Namely.

The first method is as shown in Figure 1 (8) to (8).
A high-concentration silicon wafer (n+ layer (1)) is prepared, and an n-type image concentration layer (n layer) (2) is grown on the main surface side of the wafer (n layer) (2) by an epitaxial method (same figure).
The surface of the image density layer (2) is heated to a high temperature (1000-1200°
0) Process to form a silicon oxide film (SiQ [) (3) (Figure B). Next, this silicon oxide film (3)
A part of the n+ ion implanted layer (n middle layer) (4) is formed by removing and opening a part of the n+ ion layer (4) by ion-implanting n-type impurities from this part. While forming the opening (5') to make it wider (D in the same figure)
, P-type impurity is diffused (or ion-implanted) through this opening (5') to form a P+ diffusion/[5] (see E in the same figure).
).

Therefore, the reverse breakdown voltage of the hyperstep junction obtained by this first conventional method is determined by the n-type image concentration layer (2) and the P+ diffusion layer (5) formed by the epitaxial method. Although the pressure resistance will be improved,
On the other hand, this method has the disadvantage that the photolithography process is increased by one time, making the work process complicated.

In order to eliminate this drawback, when forming the n+ ion implantation layer (4) by ion implantation, the advantage of ion implantation is that the concentration is lower on the silicon surface side, and this advantage can be utilized. The second method is shown in FIG. 2 (5) to (g).

That is, in FIG. 2 (Al-(Q is the first position to
(Similar to Q, this second method uses a hydrofluoric acid-based The silicon surface is exposed by removing it with a solution of 1, and then P type impurities are diffused from this exposed silicon surface to form a P+ diffusion layer (5) as shown in the same figure.

Therefore, in this second conventional method, the photolithography step for forming the opening (5') in the conventional method g1 can be omitted, but on the other hand, in the case of this method, the fi
+, j The concentration of n in the ion injection layer (4) is low near the silicon surface, but this n+44 degree may be high at the boundary between the silicon oxide film (3) and silicon near the opening. Therefore, there is a problem that the reverse withstand voltage decreases or a creep phenomenon occurs.

This inventive method attempts to improve the drawbacks of each of these conventional methods, and by making the width of the P+ diffusion layer larger than the N+ ion implantation layer without using photolithography, the deterioration of reverse breakdown voltage and This is to avoid the creep phenomenon.

Hereinafter, one embodiment of the method of this invention will be described in detail with respect to FIGS. 3(5) to (5).

In the method of this embodiment as well, the first step is as follows. Similarly to the second conventional method, prepare a high concentration n-type silicon wafer (n+1 layer (1) (see figure A)) and form an n-type image concentration layer (n single layer) (2) on its surface side by epitaxial method. Let it grow (
B) in the same figure, and the surface of this n-type image density layer (2) is heated to a high temperature (
tooo ~ 1200°C) to form a silicon oxide film (s
io, [) (3) is formed, but at this time, this silicon oxide film (3) is formed thicker than in each of the conventional methods described above, and a part of this silicon oxide film (3) is removed and opened. After implanting n-type impurities such as phosphorus and arsenic from here, an n+ ion implantation layer (4) is formed by high temperature treatment (Figure 0). At this high temperature treatment, a silicon oxide film (3') is formed. is formed at the same time (D in the same figure), so next, this silicon oxide film (3') is removed with a hydrofluoric acid solution in the same way as above, but at this time, the silicon oxide film (3') By continuing this removal process even after it has been completely removed, the opening end face of the silicon oxide film (3), which has been thickly formed in advance, will be removed so as to further expand the opening. It is possible to form an opening (5") wider than the n+ ion implantation layer (4), and then by diffusing P-type impurities such as boron through this opening (5"), a layer equivalent to recirculation is formed. P+ diffusion layer (5
) can be formed (E in the same figure).

Therefore, in the case of this embodiment, the P+ diffusion layer (5) formed on the n+ ion-implanted layer (4) is wider than the same layer (4), and the n-type image concentration layer is formed between each end thereof. (2), it is possible to omit one step of the photolithography process in the conventional first method, simplifying the work, and avoiding the problems in the conventional second method. In addition, deterioration in reverse breakdown voltage and creep phenomena can be completely eliminated.

As described in detail above, the present invention has the advantage of simplifying the working method and providing a super-step junction diode with stable electrical characteristics.

[Brief explanation of drawings]

Figures 1 (5) to (1) and Figures 2 (5) to (1) are cross-sectional views sequentially showing the manufacturing process of conventional ultra-step junction diodes by side tilting, and Figures 3 (A) to (1). These are cross-sectional views sequentially illustrating the manufacturing process of a nine-domain super-stepped junction diode by applying an embodiment method of the present invention. (1)...N-type silicon/high concentration wafer, (2)...
...N-type image concentration layer, (3)...Silicon oxide film, (
4)...N+ ion implantation layer, (5)...P medium scattering layer, (5"), (5")...opening. Agent Shin Kuzuno - (1 person) Secondary cause
Figure 2 323- Figure 3

Claims (1)

[Claims] On the main surface of the high concentration silicon wafer of the first conductivity type, a first
After growing a conductive type low concentration layer, its surface is treated at high temperature to form a silicon oxide film, a part of this silicon oxide film is selectively removed to form an opening, and then a An ion-implanted layer of the first conductivity type is formed by ion implantation, and when the silicon oxide film formed in the opening by this ion implantation is removed by etching, the etching time is lengthened so that the oxide film in the opening is removed. , the opening end face of the oxide film forming the opening is widened, and impurity diffusion from the widened opening results in a second conductivity type diffusion having a width wider than the first conductivity type ion implantation layer. A method for manufacturing a super-step junction diode, characterized by forming a layer.