JPS63276233A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63276233A
JPS63276233A JP62111911A JP11191187A JPS63276233A JP S63276233 A JPS63276233 A JP S63276233A JP 62111911 A JP62111911 A JP 62111911A JP 11191187 A JP11191187 A JP 11191187A JP S63276233 A JPS63276233 A JP S63276233A
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrodes
internal electrodes
mounting part
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62111911A
Other languages
Japanese (ja)
Inventor
Kiyoshi Katsuraoka
桂岡 潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62111911A priority Critical patent/JPS63276233A/en
Publication of JPS63276233A publication Critical patent/JPS63276233A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49177Combinations of different arrangements
    • H01L2224/49179Corner adaptations, i.e. disposition of the wire connectors at the corners of the semiconductor or solid-state body

Abstract

PURPOSE:To improve a yield of bonding by a method wherein the respective sides of a semiconductor chip mounting part are made to have a rounding in a circular-arc shape on the side of internal electrodes and the internal electrodes are extended in a vertical direction to the outside on the peripheries of the mounting part to eliminate the phenomenon of the short-circuit between bonding wires. CONSTITUTION:The outer peripheries of a semiconductor mounting part 2 for mounting a semiconductor chip 5, particularly the central outer peripheries of the respective sides of the placing part 2 are swelled roundly toward the side of internal electrodes 1 to be led out to the outside. The electrodes 1 are extended to the outside nearly vertically to the outer peripheries of the mounting part 2. For this, the directions of bonding wires 4 for connecting semiconductor chip connection parts 3 with the electrodes 1 become nearly the same as those of the electrodes 1. Whereupon, the phenomenon of the short-circuit between a wire 4 and an electrode 1 adjacent to the electrode 1 to be connected with the wire 4 is eliminated. Thereby, a yield of bonding is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体チップ載置部周
辺に外部へ導出する内部電極を有する半導体装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having internal electrodes extending outside around a semiconductor chip mounting portion.

〔従来の技術〕[Conventional technology]

従来、こ種の半導体装置においては、半導体チップを搭
載するための半導体装置部の形状が正方形又は長方形で
あり、その周辺に外部へ伸びる内部電極を有し、半導体
チップ側の前記半導体チップ接続部と前記内部電極とを
ボンディングワイヤーにより接続されたものとなってい
た9第5図はかかる従来の一例を示す半導体装置の平面
図、第6図は第5図に示す0部の拡大図である。
Conventionally, in this type of semiconductor device, the shape of the semiconductor device section for mounting the semiconductor chip is square or rectangular, and the semiconductor device section has an internal electrode extending to the outside around the square, and the semiconductor chip connection section on the semiconductor chip side has an internal electrode extending outside. FIG. 5 is a plan view of a semiconductor device showing an example of such a conventional semiconductor device, and FIG. 6 is an enlarged view of part 0 shown in FIG. .

第5図に示すように、この半導体装置は内部電極1を形
成したセラミックパッケージ6の中央に半導体チップ5
を搭載するための領域である半導体チップ載置部2を設
けており、半導体チップ5の半導体チップ接続部3と内
部電極1とをボンディングワイヤー4により接続する構
成である。
As shown in FIG. 5, this semiconductor device has a semiconductor chip 5 placed in the center of a ceramic package 6 in which internal electrodes 1 are formed.
A semiconductor chip mounting section 2 is provided as an area for mounting a semiconductor chip 5, and a semiconductor chip connection section 3 of a semiconductor chip 5 and an internal electrode 1 are connected by a bonding wire 4.

また、第6図に示すC部拡大図からもわかるように、チ
ップの周辺の隅に行くほど、周辺の中央部に比ベボンデ
ィングワイヤー4と内部型i1との角度が小さくなって
いた。
Further, as can be seen from the enlarged view of part C shown in FIG. 6, the angle between the bonding wire 4 and the internal mold i1 became smaller as it went to the peripheral corners of the chip compared to the central part of the periphery.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した半導体装置は、半導体チップ載置部の形状が正
方形又は長方形で、その周辺に外部へ向って内部電極が
伸びている。このため、半導体チップ接続部と内部電極
をボンディングワイヤーで接続すると、特にセラミック
ケースの四隅付近においては、ボンディングワイヤーと
内部電極の方向が異なるためにボンディングワイヤーと
隣りの内部電極とが短絡を起し、ボンディング工程にお
ける歩留りを低下させるという欠点があった。
In the above-described semiconductor device, the semiconductor chip mounting portion has a square or rectangular shape, and internal electrodes extend outward from the periphery thereof. Therefore, when connecting the semiconductor chip connection part and the internal electrodes with bonding wires, the bonding wires and the adjacent internal electrodes may short-circuit because the directions of the bonding wires and the internal electrodes are different, especially near the four corners of the ceramic case. However, there was a drawback that the yield in the bonding process was reduced.

本発明の目的は、かかるボンディングワイヤーとその接
続すべき内部電極以外の内部電極とが短絡現象を起した
すせずに、且つボンディングワイヤー間の短絡現象等を
生じないような半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device that does not cause a short circuit phenomenon between such a bonding wire and an internal electrode other than the internal electrode to be connected to the bonding wire, and also does not cause a short circuit phenomenon between the bonding wires. There is a particular thing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、半導体チップを搭載する半導体
チップ載置部の外周を内部電極側に実質的にふくらみを
持たせて形成し、且つ前記内部電極を前記半導体チップ
載置部の外周に対してほぼ垂直に外部へ延ばすように構
成される。これにより、内部電極の方向とボンディング
ワイヤーの方向をほぼ同じにすることができる。
In the semiconductor device of the present invention, the outer periphery of a semiconductor chip mounting portion on which a semiconductor chip is mounted is formed to have a substantial bulge toward the internal electrode side, and the internal electrode is formed with respect to the outer periphery of the semiconductor chip mounting portion. and is configured to extend outward approximately vertically. Thereby, the direction of the internal electrodes and the direction of the bonding wire can be made substantially the same.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第一の実施例を示す半導体装置の平面
図、第2図は第1図に示すA部の拡大図である。
FIG. 1 is a plan view of a semiconductor device showing a first embodiment of the present invention, and FIG. 2 is an enlarged view of section A shown in FIG. 1.

第1図に示すように、半導体チップ5を搭載する半導体
チップ載置部2の外周が中央外周部はど外部へ導出する
内部電極1側にまるくふくらんでおり、それに沿って且
つ外周に対しほぼ垂直方向に内部電極1が外部へ伸びて
いる。このため、半導体チップ接続部3と内部電極1と
を接続するボンディングワイヤー4と内部電極1の方向
がほぼ同一となる。尚、6は内部電極1を有するセラミ
ックパッケージである。
As shown in FIG. 1, the outer periphery of the semiconductor chip mounting part 2 on which the semiconductor chip 5 is mounted has a central outer periphery that bulges out toward the internal electrode 1 leading out to the outside, and along this bulge and approximately relative to the outer periphery. The internal electrodes 1 extend outward in the vertical direction. Therefore, the directions of the bonding wire 4 that connects the semiconductor chip connection portion 3 and the internal electrode 1 and the internal electrode 1 are substantially the same. Note that 6 is a ceramic package having internal electrodes 1.

また、第2図に示すように、前述のボンディングワイヤ
ー4と内部電極1の方向がほぼ同じとなることにより、
ボンディングワイヤー4と接続すべき内部電極の隣りの
内部電極1との短絡現象を起こすことが無くなる。これ
はセラミックパッケージ6の四隅が従来は空いていたの
に対し、本実施例ではそこをも利用して内部電極1の間
隔および配置を変えたものである。
Furthermore, as shown in FIG. 2, since the directions of the bonding wire 4 and the internal electrode 1 are almost the same,
A short circuit phenomenon between the internal electrode 1 adjacent to the internal electrode to be connected to the bonding wire 4 is eliminated. This is because the four corners of the ceramic package 6 were conventionally open, but in this embodiment, the spaces and arrangement of the internal electrodes 1 are changed by utilizing these corners.

第3図は本発明の第二の実施例を示す半導体装置の平面
図、第4図は第3図に示すB部の拡大図である。
3 is a plan view of a semiconductor device showing a second embodiment of the present invention, and FIG. 4 is an enlarged view of section B shown in FIG. 3.

第3図および第4図に示すように、本実施例の半導体装
置はセラミックパッケージ6上の半導体チップ載置部2
の形状をまるみを持たせた形状から十三角形にしたとこ
ろが前述の第一の実施例と異なっている。前記第一の実
施例でも述べたが、ボンディングワイヤー4と接続すべ
き内部電極の隣りの内部電極1とが短絡しないようにす
るため、半導体チップ載置部2の形状を内部電極1側に
ふくらみを持たせ、且つボンディングワイヤー4と内部
電極1の方向をほぼ同一にしている。しかしながら、こ
の第一の実施例においては、セラミックケース6の四隅
付近においてボンディングワイヤー4と内部電極1の方
向がまだ不十分である。そこで、この第二の実施例では
半導体チップ載置部2を十三角形にすることにより、四
゛隅のボンディングワイヤー4と内部電極1の方向を同
一とし、これによりセラミックケース6の四隅付近の短
絡現象を解消するものである。
As shown in FIGS. 3 and 4, the semiconductor device of this embodiment has a semiconductor chip mounting portion 2 on a ceramic package 6.
This embodiment differs from the first embodiment in that the shape is changed from a rounded shape to a ten-triangular shape. As described in the first embodiment, in order to prevent short circuit between the bonding wire 4 and the internal electrode 1 adjacent to the internal electrode to be connected, the shape of the semiconductor chip mounting portion 2 is bulged toward the internal electrode 1 side. In addition, the bonding wire 4 and the internal electrode 1 are oriented in substantially the same direction. However, in this first embodiment, the directions of the bonding wires 4 and the internal electrodes 1 near the four corners of the ceramic case 6 are still insufficient. Therefore, in this second embodiment, by making the semiconductor chip mounting part 2 into a ten triangular shape, the directions of the bonding wires 4 at the four corners and the internal electrodes 1 are the same, thereby preventing short circuits near the four corners of the ceramic case 6. This is to eliminate the phenomenon.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は半導体チップ載置部の形
状をそれぞれの辺が内部電極側に円弧状(こまるみを持
たせるか又は12角形等の多角形状にふくらませ且つそ
の周辺に外部へ垂直方向に内部電極を延ばして形成する
ことにより、半導体チップ接続部と内部電極間を接続す
るボンディングワイヤーの方向とその内部電極の方向と
をほぼ同一にすることができる。従ってボンディングワ
イヤーと接続すべき内部電極の隣りの内部電極との短絡
現象を無くすことが可能となり、ボンディング歩留りを
改善することができるという効果がある。
As explained above, the present invention provides a structure in which each side of the semiconductor chip mounting portion is curved toward the internal electrode side (either rounded or expanded into a polygonal shape such as a dodecagon), and the periphery thereof is perpendicular to the outside. By forming the internal electrodes by extending them in the direction, the direction of the bonding wire connecting between the semiconductor chip connection part and the internal electrodes can be made almost the same as the direction of the internal electrodes. This has the effect that it is possible to eliminate short-circuit phenomena between internal electrodes and adjacent internal electrodes, and that bonding yield can be improved.

【図面の簡単な説明】 第1図は本発明の第一の実施例を示す半導体装置の平面
図、第2図は第1図におけるA部の拡大図、第3図は本
発明の第二の実施例を示す半導体装置の平面図、第4図
は第3図におけるB部の拡大図、第5図は従来の一例を
示す半導体装置の平面図、第6図は第5図における0部
の拡大図である。 1・・・内部電極、2・・・半導体チップ載置部、3・
・・半導体チップ接続部、4・・・ボンティングワイヤ
ー、5・・・半導体チップ、6・・・セラミックパッケ
ージ。 第1 回 7、−5 千5I21 早6 回
[Brief Description of the Drawings] Fig. 1 is a plan view of a semiconductor device showing a first embodiment of the present invention, Fig. 2 is an enlarged view of section A in Fig. 1, and Fig. 3 is a plan view of a semiconductor device showing a first embodiment of the present invention. 4 is an enlarged view of section B in FIG. 3, FIG. 5 is a plan view of a semiconductor device showing a conventional example, and FIG. 6 is an enlarged view of section 0 in FIG. 5. It is an enlarged view of. DESCRIPTION OF SYMBOLS 1... Internal electrode, 2... Semiconductor chip mounting part, 3...
... Semiconductor chip connection portion, 4... Bonding wire, 5... Semiconductor chip, 6... Ceramic package. 1st 7, -5 thousand 5I21 early 6th

Claims (1)

【特許請求の範囲】[Claims] 半導体チップを搭載する半導体チップ載置部の周辺に外
部へ導出する内部電極を形成してなる半導体装置におい
て、前記半導体チップ載置部の形状を前記内部電極側に
実質的にふくらみを持たせて形成し、且つ前記内部電極
を前記半導体チップ載置部の外周に対してほぼ垂直に配
置したことを特徴とする半導体装置。
In a semiconductor device in which an internal electrode leading to the outside is formed around a semiconductor chip mounting part on which a semiconductor chip is mounted, the shape of the semiconductor chip mounting part is substantially bulged toward the internal electrode side. and the internal electrodes are arranged substantially perpendicularly to the outer periphery of the semiconductor chip mounting section.
JP62111911A 1987-05-08 1987-05-08 Semiconductor device Pending JPS63276233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62111911A JPS63276233A (en) 1987-05-08 1987-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62111911A JPS63276233A (en) 1987-05-08 1987-05-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63276233A true JPS63276233A (en) 1988-11-14

Family

ID=14573210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62111911A Pending JPS63276233A (en) 1987-05-08 1987-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63276233A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7435409B2 (en) 1999-03-12 2008-10-14 Mcneil-Ppc, Inc. Compositions comprising a potassium salt active ingredient, including oral compositions for reducing dental nerve and dentin sensitivity comprising a non-menthol flavoring

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254755A (en) * 1984-05-31 1985-12-16 Fujitsu Ltd Package for mounting semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254755A (en) * 1984-05-31 1985-12-16 Fujitsu Ltd Package for mounting semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7435409B2 (en) 1999-03-12 2008-10-14 Mcneil-Ppc, Inc. Compositions comprising a potassium salt active ingredient, including oral compositions for reducing dental nerve and dentin sensitivity comprising a non-menthol flavoring

Similar Documents

Publication Publication Date Title
JPH06252328A (en) Lead frame for mounting semiconductor element
JPS6035524A (en) Semiconductor device
JPS63276233A (en) Semiconductor device
JPH0648715B2 (en) Integrated circuit chip
US5126828A (en) Wafer scale integration device
JPS59139660A (en) Semiconductor device
JPH04146658A (en) Lead frame
JP2772897B2 (en) Lead frame and method of manufacturing connection terminal using lead frame
JPH02253650A (en) Lead frame
KR100210166B1 (en) Semiconductor package lead frame
JPH05235090A (en) Semiconductor integrated circuit
JPS582059Y2 (en) semiconductor storage container
JPS62266844A (en) Semiconductor device
JPH073637Y2 (en) Bonding pattern
JPH02114544A (en) Semiconductor device
JPH02142151A (en) Integrated circuit device
JPS60101938A (en) Semiconductor device
JPS59105349A (en) Integrated circuit device
JPH01173747A (en) Resin-sealed semiconductor device
JPH01273343A (en) Lead frame
JPH02119228A (en) Semiconductor device
JPS63250165A (en) Semiconductor device
JPH02278742A (en) Semiconductor device
JPH04162763A (en) Resin-sealed semiconductor device
JPH05129501A (en) Package for ic