JPS63272079A - Manufacture of non-volatile memory element - Google Patents

Abstract

PURPOSE:To obtain an element which is improved in its quality of a tunnel oxidizing film and is not contaminated by a gas from a resist or oil from a device during ion implantation, by using an epitaxial growth method to form a tunnel region in an EEPROM of FLOTOX structure on a semiconductor substrate. CONSTITUTION:When an EEPROM of FLOTOX structure is manufactured, a single-crystal epitaxial layer 35, which contains impurities different in their conductivity type from impurities contained in a single-crystal semiconductor substrate 31, is formed as a tunnel region on a desired region on the surface of the substrate 31. A gate oxide film 36 is formed on the surface of the substrate inclusive of the single-crystal epitaxial layer 35, and next one region of the gate oxide film 36 is etched away on the single-crystal epitaxial layer 35. Further the single-crystal epitaxial layer's surface is oxidized to form a tunnel oxide film 37, which is thinner than the gate oxide film 36, on said region. Subsequently, for example, a floating gate electrode 38, an intermediate insulating film 39, a control gate electrode 40 are formed on the substrate 31, and besides a source region 41 and a drain region 42 are formed inside the substrate 31.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to non-volatile memory elements, particularly memory elements of MO8 type structure (EEP) that can be electrically written and erased.
The present invention relates to a method of manufacturing a ROM (referred to as ROM).

(Prior Art) Various structures have been proposed as EEPROMs, but the most commonly used ones are as follows:
It has a 70-ring gate structure (referred to as FLOTOX structure) in which charges are taken in and out through an extremely thin oxide film (referred to as tunnel oxide film) of about 100 A.

A cross-sectional view of the conventional EEFROM having the FLOTOX structure is shown in FIG. In this figure, 1 is a p-type silicon substrate, 2 is an element isolation oxide film, 3 is a source region of an n-type impurity region, 4 is a drain region of an n-type impurity region, and 5 is a p-type silicon substrate.
is an n-type tunnel region formed in contact with the drain region 4 and is generally formed with a lower impurity concentration than the drain region, 6 is a gate oxide film, 7 is formed in a part of the gate oxide film 6, The thickness is extremely thinner than the gate oxide film 6 (approximately 1
00A) A tunnel oxide film, 8 a floating gate electrode made of phosphorous-doped polysilicon, 10 a control gate electrode made of the same material formed above the 70-ting gate electrode 8 with an intermediate insulating film 9 interposed therebetween; 1
Reference numerals 1 and 12 are external extraction electrodes, which are in contact with the source region 3 and drain region 4, respectively. Note that the above description is based on the case where the substrate 1 is p-type.

EEP with conventional FLOTOX structure configured like this
The ROM is conventionally left behind as shown in Figure 3.

First, an element isolation oxide film 2 is uniformly formed on a p-type silicon substrate 1 by a known method, and then an oxide layer 21 is formed on the surface of the active region of the substrate 1 surrounded by the element isolation oxide film 2. , on which Renost 22 is applied except for the tunnel region forming region.
(Fig. 3(a)).

Next, by ion-implanting phosphorus or arsenic in this state, a tunnel region 5 is formed in a part of the substrate 1 not covered with the renost 22 (FIG. 3(b)).

Next, the renost 22 and the oxide film 21 are removed, and a gate oxide film 6 of a predetermined thickness is formed again in the area from which the oxide film has been removed, and then a part of the gate oxide film 6 is removed by etching and oxidized again. In the evening, a tunnel oxide film 7 is formed in the portion where the gate diffusion film has been removed (FIG. 3(C)). Here, the tunnel oxide film 7 is formed on the surface of the tunnel region 5.

After that, tunnel oxide film 7 and gate oxide film 116
70% by phosphorus-doped polysilicon in a predetermined area on the
- forming a gate electrode 8 (FIG. 3(d)).

Next, the surface of the floating gate electrode 8 is oxidized,
After forming the intermediate insulating film 9, a condom electrode IO is formed on its surface using phosphorus-doped polysilicon (FIG. 3(e)).

After that, after depositing PSG (not shown) on the entire surface of the substrate 1, that film and a part of the gate oxide film 6 are etched, and highly concentrated arsenic is injected into the substrate 1 through that part. A source region 3 and a drain region 4 are formed in the substrate 1 (FIG. 3 (fJ)). At this time, the drain region 4 is brought into contact with the tunnel region 5.

Thereafter, external lead electrodes (not shown) for the source/drain regions 3.4 are formed using a general method for making semiconductor integrated circuits, thereby completing the structure shown in FIG. 2.

(Problems to be Solved by the Invention) However, the conventional manufacturing method as described above has the following drawbacks.

(11 The tunnel region 5 is formed by ion implantation of arsenic
Since it is formed by oxidizing the vicinity of the surface of the substrate, it incorporates some of the defects in the substrate l that occur during ion implantation, making it impossible to obtain a good quality product.

(2) When forming the tunnel region 5, ions are implanted with the renost 22 formed on a part of the substrate 1, so
It is subject to contamination by gas emitted from the renost 22 and oil generated by the device during ion implantation.

It is an object of the present invention to provide a method for manufacturing a clean non-volatile memory element that eliminates the poor quality of the tunnel oxide film caused by the conventional method described above and is free from contamination due to gas emitted from renost and oil from the equipment used during ion implantation. With the goal.

(Means for Solving the Problems) The present invention is a method for manufacturing an EEPROM having a FLOTOX structure, in which a tunnel region, which serves as an electron supply source, is formed on a semiconductor substrate by epitaxial growth.

(Function) In the above method, a single crystal epitaxial layer is formed as a tunnel region on a semiconductor substrate by an epitaxial growth method. A tunnel oxide film is formed by oxidizing the surface of the single-crystal epitaxial layer, but since the tunnel oxide film is formed by oxidizing the single-crystal epitaxial layer with extremely few defects, it is extremely difficult to form. The result is a high-quality film with few defects. Further, in this invention, the ion implantation method is omitted because the futunnel region is formed by epitaxial growth instead of the ion implantation method.

(Example) An embodiment of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1(a), after selectively forming an element isolation oxide film 32 on the surface of a p-type nested crystal silicon substrate 31 containing p-type impurities, the element isolation oxide film 32 is An insulating film layer 33 is formed on the surface of the surrounded active region of the substrate 31, and a portion of this insulating film layer 33 is etched to form an opening 3.
form 4. Here, the insulating film layer 33 may be a single layer of oxide film, but a 2m layer of about several thousand amperes, in which a nitride film is layered on an oxide film, is more effective.

Next, on the surface of the desired region of the single crystal silicon substrate 31 exposed through the opening 34 of the insulating film layer 33, a single crystal epitaxial layer 35 of silicon containing n-type impurities is formed as a tunnel region (by selective epitaxial growth). . This single crystal epitaxial layer 35 has a thickness of 0.2 to 1.0 μm.
The concentration of n-type impurities such as phosphorus is lX1.
0 to I x 1019 cm/cm". Such a single crystal epitaxial layer 35 is formed by a normal selective epitaxial growth method such as a thermal decomposition method or a hydrogen reduction method. and 1 using 81.H4 gas
It is formed by a thermal decomposition method at 000-1100°C.

Thereafter, the insulating film layer 33 is removed by etching (FIG. 1(C)). Note that even if very thin polycrystalline silicon may grow on the surface of the insulating film layer 33 during the formation of the single crystal epitaxial layer 35, there is no problem because it is etched away at the same time in the process of etching the insulating film layer 33. .

Next, a gate oxide film 36 is formed several hundred thick on the surface of the substrate 31 including the single crystal epitaxial layer 35 by oxidation (FIG. 1(d)).

Thereafter, a part of the gate oxide film 36 on the single crystal epitaxial layer 35 is removed by etching, and a tunnel oxide film 37 with a thickness of about 100A is formed on that part again by oxidizing the surface of the single crystal epitaxial layer 35 (the first Figure (e))
.

The subsequent steps are exactly the same as the conventional ones. First, a floating gate electrode 38 is formed using phosphorus-doped polysilicon in a predetermined region on the tunnel oxide film 37 and gate oxide film 36 (see FIG. )).

Next, a dielectric intermediate insulating film 39 is formed on the surface of the 70-ring gate electrode 38 by oxidation, and then a control gate electrode 40 is formed on the surface using phosphorus-doped polysilicon (FIG. 1(g)).

Thereafter, a film such as PSG (not shown) is deposited on the entire surface of the substrate 31, and then that film and a part of the gate oxide film 36 are etched, and n-type impurities are injected into the substrate 31 through that part at a high concentration. As a result, a source region 41 and a drain region 42 are formed in the substrate 31 (see the top of FIG. 1). At this time, the drain region 42 is brought into contact with the n-type single crystal epitaxial layer 35.

Finally, extraction electrodes 43 and 44 are formed from metal outside the source and drain regions 41 and 42.

(Effects of the invention) The method of creating this invention as described above has the following effects.

(1) Since the tunnel oxide film, which determines the lifetime, is formed by oxidizing the surface of a single crystal epitaxial layer with extremely few defects, a high quality film with very few defects can be obtained. This, in turn, significantly improves the yield of good chips from wafers and extends device lifetime.

(2) When forming the tunnel region, there is no step of implanting ions with the resist applied, so there is no contamination of the semiconductor substrate by gases from the resist or oil from the equipment, and high-quality devices can be obtained. .

(3) The surface impurity level of the tunnel region is as low as that of EEPROM.
This is a major factor that determines the injection efficiency of cells, but since the tunnel region of the present invention, that is, the single crystal epitaxial layer, can have a uniform concentration regardless of the depth, it is possible to It has much better controllability than K (with a gradient), and it is easier to obtain products without variations.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a process showing an embodiment of the method for manufacturing a non-volatile memory element of the present invention, and FIG. 2 is a cross-sectional view of a conventional FLOTOX.
FIG. 3 is a sectional view showing the structure of an EFJPROM, and FIG. 3 is a process sectional view showing a conventional EEPROM manufacturing method. 31... P-type wheel crystal silicon substrate, 33... Insulating film) fi, 35... Single crystal epitaxial layer, 36...
・Gate oxide film, 37...Tunnel oxide film, 38...
・Floating gate electrode, 39... intermediate insulating film,
40... Control gate electrode, 41... Source region, 42... Drain region. Book arrangement - I example of 1st pattern last neck + IIZ 1st picture; 195th r1 - Funo wo Tomoe Iter 1 1st reworking season! Mffi 1 mouth diagram

Claims (1)

[Claims] Non-volatile memory element, especially EEP with FLOTOX structure
A method for manufacturing a ROM includes the steps of: (a) forming a single crystal epitaxial layer containing an impurity of a conductivity type different from that of the substrate as a tunnel region in a desired region of the surface of a single crystal semiconductor substrate; After forming a gate oxide film on the surface of the substrate including on the single crystal epitaxial layer, a part of the gate oxide film is etched away on the single crystal epitaxial layer, and the single crystal epitaxial layer is further etched in that part. 1. A method of manufacturing a nonvolatile memory element, comprising the step of forming a tunnel oxide film thinner than the gate oxide film by oxidizing a surface portion of the layer.