JPS62142362A - Manufacture of nonvolatile semiconductor memory element - Google Patents

Abstract

PURPOSE:To obtain a tunnel insulating film characterized by excellent film- thickness controllability and excellent tunnel insulating film, by making it possible to provide the tunnel insulating film directly on a semiconductor substrate having less impurities. CONSTITUTION:A tunnel insulating film 2 is provided on a P-type silicon semiconductor substrate 6. Then a floating gate 1 is formed. When an impurity diffused layer 3 is formed, the impurities are simultaneously diffused to a part beneath the tunnel insulating film immediately beneath the floating gate from the side end of the floating gate 1 by the lateral diffusion. Thus the diffused layers beneath the tunnel insulating film is formed. Thus, an EEPROM element structure can be formed without impairing the film quality of the tunnel insulating film. This method contribute to the improvement in yield rate in the manufacture of the EEPROMs and the improvement in reliability in time change an the like owing to the stabilization of the film quality.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory element.

2. Description of the Related Art Conventionally, among non-volatile semiconductor memory devices, electrically programmable and erasable floating gate memory devices (hereinafter referred to as EEFROMs)
) usually has a two-layer gate structure. The second layer (upper layer) is used as a control gate, and the first layer (lower layer) gate is used as a floating gate. Furthermore, a region with a very thin insulating film is provided between the floating gate and the semiconductor substrate, and the memory element operation is realized by injecting and extracting electrons from the substrate side to the floating gate through the insulating film. FIG. 2 schematically shows a plan view of a commonly used EEFROM element. FIG. 3 schematically shows a cross-sectional structure when cut along AA' in FIG. 2, and is the structure of an E E FROM element produced by a conventional method.

In FIGS. 2 and 3, 1 is the first layer gate, that is, the floating gate region, a part of which is the tunnel insulating film region 2.
3 on top is an n-type or p-type high concentration diffusion layer, 6
6 is a thick insulating film forming a field portion, 6 is a p-type semiconductor substrate, and 7 is a second layer gate, that is, a control gate region, which is provided through the floating gate 1 and the insulating film. 8
is an insulating film between the floating gate and the control gate. In an EEFROM having such a structure, in order to facilitate injection and extraction of electrons, it is usually necessary to form a dense n-type or p-type diffusion layer 3 on the surface of the semiconductor device under the bulge insulating film. . On the other hand, when forming a very thin insulating film such as a tunnel insulating film on the surface of a diffusion layer using a heat treatment method such as a thermal oxidation method or a thermal nitridation method, the higher the impurity concentration of the diffusion layer, the more difficult it is to control the film thickness. It is well known that this is difficult and the film quality deteriorates due to impurities being incorporated into the insulating film during the thin film formation process. - To form the diffusion layer 3, there is a method in which a tunnel thin film is formed in advance on the semiconductor substrate 2, and then impurities are implanted through the thin film by a method such as ion implantation to form the diffusion layer. In this case, damage occurs to the tunnel insulating film during ion implantation, and complete recovery is difficult even with subsequent heat treatment.

Problems to be Solved by the Invention The ideal method for forming a tunnel insulating film is to form it on a semiconductor substrate that has not been diffused with many impurities, and then do not cause any damage to the film. A method has not yet been realized.

Further, in order to facilitate the operation of the EEPROM element, it is practically necessary to provide some kind of diffusion layer under the tunnel insulating film.

The purpose of the present invention is to propose a new manufacturing method for forming an impurity diffusion layer under the tunnel insulating film without affecting the film quality of the tunnel insulating film. In this method, a tunnel insulating film is first formed on a semiconductor substrate without a diffusion layer, and then a floating gate layer is immediately formed. After processing the floating gate to a predetermined size, impurities are diffused using the same floating gate as a diffusion mask, and the impurities are laterally diffused from the side edges of the floating gate under the tunnel insulating film to the region corresponding to the bottom of the floating gate. By using this zero-effect method, which is the manufacturing method for non-volatile semiconductor memory elements introduced in A tunnel insulating film is obtained. Even when the impurity diffusion layer is subsequently formed, the diffusion layer can be directly formed without damaging the tunnel insulating film, so that the good film quality at the time of initial formation is maintained. Therefore, according to the present invention, it is possible to form an EEPROM having a tunnel insulating film region on a diffusion layer formed by lateral diffusion of impurity ions under a floating gate.

Example Next, the method of the present invention will be explained in detail using the drawings.

FIG. 1 shows a cross-sectional structure of an EzpROM element manufactured by the manufacturing method of the present invention. When forming the tunnel insulating film 2 on the semiconductor substrate 6, then forming the floating gate 1, and then forming the impurity diffusion layer 3, impurities are simultaneously diffused in the lateral direction from the side edges of the floating gate 1 directly below the floating gate. To do this, diffuse the layer under the insulating film (to form a diffusion layer under the tunnel insulating film).

By this method, it is possible to form the EEPROM terminal structure without damaging the film quality of the tunnel insulating film. The subsequent manufacturing steps are similar to the conventional method shown in FIG. Next, details of the present invention will be described.

A field oxide film 5 is formed on a P-type silicon substrate 6 by the usual selective oxidation method, and s is formed on the inside of the field oxide film 6.
A gate oxide film of onm or sonm is formed. Next, in order to form the tunnel insulating film 2, a part of the gate oxide film on the silicon substrate θ is removed using photolithography technology, and then a tunnel insulating film 2 with a thickness of about 10 nm is formed using a thermal oxidation method. do. Then, immediately about 40
After growing polycrystalline silicon to a thickness of onm and introducing impurities, a floating gate 1 made of a polycrystalline silicon layer is formed using normal processing techniques. After that, phosphorus (P) or arsenic (AS) accelerated at 100 to 160 KeV using ion implantation technology is implanted into the silicon substrate 6 using the floating gate 1 as a mask. Impurities have not yet been introduced directly below the floating gate 1 and the control gate 7. Next, to form an oxide film between the floating gate 1 and the control gate 7, it is heated in an oxidizing atmosphere at a temperature of 1000'C to 1100'C. When thermal oxidation is performed for 10 minutes, an oxide film 8 is formed, and at the same time, the impurity phosphorus or arsenic implanted near the side edges of the floating gate 1 in the silicon substrate is diffused in the lateral force direction, as shown in FIG. A diffusion layer 4 directly under the floating gate is formed as shown in .At this time, the amount of diffusion in the lateral direction can be controlled by the type of impurity and the heat treatment temperature for 0 hours, so that the diffusion layer 4 is not necessarily spread over the entire surface directly under the floating gate 1. It is not necessary, and it is sufficient that a certain amount of the diffusion layer 4 always overlaps with the floating gate 1. In this case, the amount of overlap can be controlled not by processing technology but by diffusion technology, so it can be determined very accurately. The subsequent manufacturing method is the same as the usual method, and the control gate 7 made of a polycrystalline silicon layer is formed, and then wiring made of aluminum metal or the like is formed to complete the device.

Effects of the Invention Ell! manufactured by the method of the present invention! In PROM devices, the tunnel insulating film is formed directly on the silicon substrate before forming the diffusion layer, but even after the tunnel oxide film is formed, the tunnel insulating film is formed directly on the silicon substrate.
This insulating film allows a diffusion layer to be formed under the floating gate without being damaged, so it has a high-quality outer tunnel insulating film that does not cause variations in film thickness or deterioration in film quality.

Therefore, the present invention contributes to improving the yield in manufacturing EIEPROMs and improving reliability against changes over time by stabilizing film quality.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structure diagram of a non-volatile semiconductor memory element showing a method of manufacturing a non-volatile semiconductor memory element according to the present invention, FIG. 2 is a plan view of essential parts of a conventional non-volatile semiconductor memory element, and FIG. FIG. 1... Floating gate, 2... Tony insulating film, 3... Impurity diffusion layer, 4...
Lateral diffusion layer, 5...Field insulating film thickness, 6
... Semiconductor substrate, 7 ... Control gate, 8
・・・・・・Interlayer insulating film between floating gate and control gate.

Claims (1)

[Claims] In the manufacturing process of an electrically programmable and erasable nonvolatile memory element having a floating gate, a step of forming an impurity diffusion layer under the tunnel insulating thin film directly under the floating gate by lateral diffusion from the side edge of the floating gate. A method for manufacturing a nonvolatile semiconductor memory element, characterized by comprising: