A6 B6 五、發明説明（） 發明背景 最早期EPROM及快閃EPROM之位元線係在叠曆複晶矽閘極形 成後覆一硼酸鹽玻瑀（B P S G)，再Μ接觭窗光罩於源極 汲極上形成接觸窗孔，及沉横一可填充該接觸窗孔之金觴 層經蝕刻成條狀圖案，該連接位於同一線上之各記憶單元 之汲極金靥圓案即稱「位元線j 。之後，鑑於因在各記憶 單元皆形成有接觭窗孔將造成元件無法高密度化，遂進步 發展為具有埋層位元線结構，主要係在線路佈局上將各位 於同一線之源極汲極予Μ埋層擴散區構成，僅在預連接電 源處形成接觸窗孔，因此可使元件密度大為提高，該類習 知技術可參考美國專利公報公告號第五〇七〇〇三二號， 等。又由於埋層位元媒结構之EPH0M及快閃EPROM其兩位元 線間係K場氧化層（FIELD OXIDE)作電性隔離，因此當成 長場氧化層（FIELD OXIDE)時伴生之鳥啄（BIO’S BEAK)問 題，使得預先設計之活躍區（置放電子元件之處）面積包括 位元線和通道區將因而受減損且形成烏啄之場氧化層因其 厚度不夠不足做電性隔雔，故便形同晶片面稹之浪費，亦 即造成元件無法高密度之主要原因。 為克眼此一問題，遂有提出另一改良式埋層位元線 结構EPROM及快閃EPROM,即如美國專利公報公告號第五0 八七五八四號（下稱前案），其主要係在該場氧化層成長後 並非為習知之方塊狀而係條狀，然後於形成位元線之前藉 蝕刻使其恢復方塊狀，因此自晶片平面観之，該條狀場氧 化曆形成鳥啄面積顯然較方塊狀減少一半，並藉此可大大 一 3 一 本紙張尺度遘用中國國家標準（CNS)〒4规格（210 X 297公货> 82. 9. 6,000 --------^ I--*Til{ (請先《讀背面之注意事項再堝寫本頁) 丨裝- 訂- 線‘A6 B6 5. Description of the invention () Background of the invention The bit lines of the earliest EPROM and flash EPROM are covered with a borate glass (BPSG) after the formation of the polycrystalline silicon gate, and then connected to the window mask A contact window hole is formed on the source and drain electrodes, and a gold layer that can fill the contact window hole is etched into a stripe pattern. The case of the drain electrode gold junction connecting the memory cells on the same line is called "bit Element line j. Later, in view of the fact that due to the formation of openings in each memory cell, which will prevent the device from being high-density, it has progressed to a structure with buried bit lines, mainly in the circuit layout will be located on the same line The source-drain electrode is composed of an M buried layer diffusion region, and a contact window hole is formed only at the pre-connected power source, so the density of the device can be greatly improved. 〇No. 3, etc. And because the EPH0M and flash EPROM of the buried bit medium structure are electrically isolated between the two field lines of the K field oxide layer (FIELD OXIDE), they should be grown as the field oxide layer (FIELD OXIDE) ) When the accompanying bird pecking (BIO'S BEAK) asked , So that the area of the pre-designed active area (where electronic components are placed) including the bit line and the channel area will be reduced and form a black pecking field oxide layer because its thickness is not enough to make electrical barriers, so it is the same The waste of the chip surface is the main reason for the high density of the device. To overcome this problem, another improved buried layer bit line structure EPROM and flash EPROM have been proposed, such as the US Patent Gazette Announcement No. Fifth 0, eight, seven, five and four four (hereinafter referred to as the previous case), which is mainly after the growth of the field oxide layer is not a conventional block shape but a strip shape, and then it is restored by etching before forming the bit line It is square, so from the plane of the wafer, the area of the bird's pecking area formed by the strip field oxidation calendar is obviously reduced by half compared to the square, and this can greatly use the Chinese National Standard (CNS) 〒4 Specifications (210 X 297 public goods> 82. 9. 6,000 -------- ^ I-* Til {(please read the precautions on the back and then write this page) 丨 Installation- Order- Line '
號專利申請案中文說明書正頁 修正日期85 / 08 / 1 6 B7 五、發明説明（） 地提高元件之密度。以下將簡單介絕前案，請配合圖1A-1G 可使前案之技術手段，功效更爲明瞭。首先於P型矽半導體 基材10上先後依序形成墊氧化層11及氮化矽層12，如圖1A 所示。後然進行一氮化矽光罩及蝕刻將活躍區111及場隔離 區112定義出，再以p型雜質離子植入形成在後續成長之場 氧化層底部具通道截止區16，即如圖1B所示。 之後，光阻去除及將整個晶片於含水蒸氣及氧氣中進行 高溫氧化，使其在場隔離區112成長一厚約5000-6000埃場 氧化層17，即如圖1C所示。然後去除墊氧化層11再經熱氧 化層19 ，厚度約爲100埃。再依序沈積第一複晶矽21 ，中 間介電層22及第二複晶矽23，如圖1D所示。接著請參閱圖 1E，進行一光罩，將欲形成懸浮閘及控制閘處予以光阻PR 25 覆蓋，再藉異方向性蝕刻，使其在閘氧化層19上形成有由第 二複晶矽23，中間介電層22及第一複晶矽21構成之條狀叠 構造24。圖1E之遠觀圖示於圖1F，明顯示出該場氧化層乃 係呈條狀，其鳥啄171形成僅在晶片平面之X軸或Y軸，而 習知之方塊狀卻同時在X軸及Y軸形成有鳥啄171 ，因此前 案可大量減少由於鳥啄171造成晶片面積之浪費。接著再進 行一光罩及蝕刻以去除未光阻覆蓋之叠層構造 24及場氧化 層17，使條狀叠層構造24形成具有槽溝26及塊狀叠層構造 27 。之後，以N型高濃度雜質離子植入形成源極汲極區（即 位元線區〉30，如圖1G所示。同時可明顯由圖1G中示出場氧 化層17於此步驟被蝕刻而恢復習知之方塊狀，位元線區面積 由於場氧化層17未形成鳥啄171故未受損， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉 -_ -- - - 1 - - —^ϋ - - -I - - - - ^f i- - - n^i n ml u V -1 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A6 B6 五、發明説明（） 然而位於閘氧化層19下（即通道區面稹）將因有鳥啄171產 生使其面槙受損，意即晶片面稹因鳥啄171產生而造成浪 費。因此逐有必要再提出一徹底解決因成長場氧化層伴生 鳥啄問題之解決方法，並進而藉此大大提高元件之高密度 化。 又傳統之EPROM及快閃EPROM於擦拭期間，若擦拭時間 過長則導致漏電流，使記憶單元之起始電懕值漯移而影響 其原有之電性參數，並進而造成產品可靠度變差。為克服 上述問題可由間斷閘極EPROM及快閃EPROM記憶單元佈局圖 如圖2所示，其中懸浮閘（即斜線區所示）之兩端並非如習 知跨接兩位元線區30而係偏移一位置，即一端跨接於位元 線區30另一端則位於通道區内形同閘極間斷之结構。又由 懸浮閘構造之電晶S8稱懸浮閘電晶體（通道長度MLf代表 ),其係和加強型（Enhanced Type)霣晶體（通道長度KLe 代表）串聯係做為防止當過度擦拭時產生之漏電流。且兩 位元線間之電性隔離乃係藉場氧化層達成的，如前面所述 ,藉場氧化層達成電性隔離之構造將造成間斷閘極 EPROM 及快閃EPROM元件無法高密度化，因此逐有必要提出一解 決方法Μ使間斷閘極EPROM及快閃EPROM元件得以高密度積 體化。 發明概述 本發明主要目的乃提供一種不具埸氧化層之間斷閘極 EPROM及快閃EPROM製法及其裝置。 -5 - (請先«讀背面之注t事項再埸裒本頁) --1 — —· -Γ-. -*'--------裝------訂 -線 經濟邾中夹標準局<*工消费合作社印製 82. 9. 6,000 本紙张尺度通用中國國家標準（CNS)甲4现格（210 X 297公货） A6 B6 五、發明説明（） 本發明進一目的乃係提供一種可提高元件高密度化之 間斷閘極EPROM及快閃EPROM製法及其裝置。 本發明主要係於叠曆複晶矽閘極形成後植入與矽半導 體同一導電型雜質離子Μ代替習知之場氧化層做為活躍區 與活躍區之間電性隔離，因此由於場氧化層成長伴生鳥啄 (bird’s beak)造成元件密度無法提高等問題將可獲得解 決，同時本發明再併藉埋鼷位元線结構，以達到高度積體 化之功效。 附圖說明 圖1A-1G為美國專利公報公告號第五〇八七五八四號 主要製程剖面画。 圖2為間斷閘極EPROM及快閃EPROM之電路佈局圖。 圖3A-3E為依据本發明之沿圖2之A-A’線各主要製程剖 面圔。 圖4A-4E為依据本發明之沿圖2之B-B'線各主要製程剖 面圖。 檷號部份： 矽半導艘基材或井區--------------------------10 墊氧化層-------- 1 1 氮化砂層------------------------------------12 活躍區---------- 111 埸隔離區------- 112 通道截止區----- 1 6 場氧化層------------------------------------1 7 —6 一 {請先《讀背面之注意事項再項寫本頁) .裝. 訂· .線· tt濟邾中夹標準曷貝工消费合作社印製 oc. y. 本紙張尺度通用中國B家標準（CNS)甲4規格（210 X 297公» ) A6 B6 五、發明説明（） 閘氧化層--------- 19 第一複晶砂（懸浮關）--------- 21 中間介電層........... 22 第二複晶矽（控制閣）--------------------------23 絕緣氧化）g ----- 211 隔離絕緣層---------------------------------2 3 1 光阻(P R )....... ...........................25 條狀叠層携造--------------------------------24 tl m--------------------------- 26 塊狀β層構造--------------------------------27 埋層位元線光軍之源極汲極區------------------29 源極汲極區（位元線區）------------------------30 圖3Α-3Ε和«4Α-4Ε分別係依据本發明之沿圖2Α-Α’線 及Β-Β'各主要製程剖面圖。首先請參閱圖3Α, 4Α在Ρ型矽 半導體基材或井區 10進行一埋層位元線光罩將欲形成記 憶單元之源極汲極區29(即位元線區）予以曝露其他區域則 Κ光阻P.R.覆蓋，接著施Κ高濃度Ν型雜霣離子如砷離子 於能悬約35Kev,劑量約為1015cm·2條件下植入，即如圖 3 A , 4 A所示。光姐去除之後，將整個晶片進行高溫氧化 ， 由於氧化層成長速率與所含雜質濃度有M,意即高雜質濃 度具有增強氧化層成長速率之特性，因此於原先覆有光阻 區域成長一厚約100埃之閘氧化層19而於欲形成記憶單元 之源極汲極區29上成長一厚氧化層（厚度約300或600埃）， 於進行高溫氧化之同時，N型雜質離子將受高溫驅使而擴 ---------——^ --------裝------訂-----"、線 <請先《讀背面之注意事項再塡寫本頁) 7The main page of the Chinese description of the patent application No. 85/08/1 6 B7 V. Description of the invention () Increase the density of components. The following will briefly exclude the previous case. Please cooperate with Figures 1A-1G to make the technical means of the previous case clearer. First, a pad oxide layer 11 and a silicon nitride layer 12 are sequentially formed on the P-type silicon semiconductor substrate 10, as shown in FIG. 1A. Then, a silicon nitride photomask and etching are performed to define the active region 111 and the field isolation region 112, and then implanted with p-type impurity ions to form a channel cut-off region 16 at the bottom of the subsequently grown field oxide layer, as shown in FIG. 1B As shown. After that, the photoresist is removed and the entire wafer is oxidized at high temperature in water vapor and oxygen to grow a thick field oxide layer 17 in the field isolation region 112, as shown in FIG. 1C. Then, the pad oxide layer 11 is removed and then the thermal oxide layer 19 is formed to a thickness of about 100 angstroms. Then, the first polycrystalline silicon 21, the intermediate dielectric layer 22 and the second polycrystalline silicon 23 are deposited in sequence, as shown in FIG. 1D. Next, referring to FIG. 1E, a photomask is formed to cover the place where the floating gate and the control gate are to be formed with a photoresist PR 25, and then the second polycrystalline silicon is formed on the gate oxide layer 19 by etching in different directions 23. A strip-shaped stacked structure 24 composed of an intermediate dielectric layer 22 and a first polycrystalline silicon 21. The perspective view of FIG. 1E is shown in FIG. 1F, which clearly shows that the field oxide layer is strip-shaped, and its bird peck 171 is formed only on the X-axis or Y-axis of the wafer plane, while the conventional square shape is on the X The bird peck 171 is formed on the axis and the Y axis, so the previous case can greatly reduce the waste of wafer area due to the bird peck 171. Then, a photomask and etching are performed to remove the stacked structure 24 and the field oxide layer 17 that are not covered by the photoresist, so that the strip-shaped stacked structure 24 is formed with grooves 26 and a bulk stacked structure 27. After that, N-type high-concentration impurity ions are implanted to form the source drain region (ie, the bit line region> 30, as shown in FIG. 1G. At the same time, it can be obviously recovered from the field oxide layer 17 shown in FIG. 1G by being etched at this step. The square shape of the conventional, the area of the bit line area is not damaged because the field oxide layer 17 has not formed the bird peck 171, so the paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -_---1 --— ^ Ϋ---I----^ f i---n ^ in ml u V -1 (Please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A6 B6 V. Description of the invention () However, under the gate oxide layer 19 (namely, the channel area surface rim) will be damaged due to the occurrence of bird peck 171, which means that the wafer surface ridge is wasteful due to the bird peck 171. Therefore, it is necessary to put forward a solution to thoroughly solve the problem of bird pecking due to the oxide layer of the growth field, and thereby greatly increase the density of the components. Also, the traditional EPROM and flash EPROM during the wiping period, if the wiping time passes Long time leads to leakage current, which causes the initial electrical value of the memory cell to shift The original electrical parameters are affected, and the reliability of the product is deteriorated. To overcome the above problems, the layout of the intermittent gate EPROM and flash EPROM memory cells can be shown in Figure 2, in which the floating gate (that is, the diagonal line area is shown) ) The two ends are not offset by a position across the two-bit line area 30 as is conventionally known, that is, one end is connected to the bit line area 30 and the other end is located in the channel area with the same gate intermittent structure. The transistor S8 of the floating gate structure is called a floating gate transistor (channel length MLf represents), which is connected in series with an enhanced type (channel length KLe representative) as a prevention of leakage current generated when excessively wiped. And the electrical isolation between the two-bit lines is achieved by the field oxide layer. As mentioned above, the structure of the electrical isolation by the field oxide layer will cause the discontinuous gate EPROM and flash EPROM devices to be unable to be high-density. Therefore, it is necessary to propose a solution M to enable the intermittent gate EPROM and flash EPROM devices to be integrated at a high density. SUMMARY OF THE INVENTION The main objective of the present invention is to provide a method for manufacturing a break gate EPROM and flash EPROM without an oxide layer Its device. -5-(please first «read the notes on the back and then this page) --1 — — · -Γ-.-* '-------- install ------ Order-Line Economy Yongzhong folder Standard Bureau < * Industrial and Consumer Cooperative Printed 82. 9. 6,000 This paper standard is universal Chinese National Standard (CNS) A 4 present grid (210 X 297 public goods) A6 B6 V. Description of invention ( ) A further object of the present invention is to provide a method and device for making the EPROM and flash EPROM of the discontinuous gate that can increase the density of the device. The present invention is mainly to implant the same conductivity type impurity ion M as the silicon semiconductor after the formation of the stacked calendar polycrystalline silicon gate instead of the conventional field oxide layer as the electrical isolation between the active region and the active region, so the field oxide layer grows The problem that the density of components cannot be increased due to the accompanying bird's beak will be solved. At the same time, the present invention also uses the structure of the bit line to achieve a highly integrated effect. Brief Description of the Drawings Figures 1A-1G are the main process cross-section drawings of US Patent Gazette Announcement No. 5087857. Figure 2 is a circuit layout diagram of intermittent gate EPROM and flash EPROM. 3A-3E are cross-sectional views of main processes along the line A-A 'of FIG. 2 according to the present invention. 4A-4E are cross-sectional views of main processes along line BB 'of FIG. 2 according to the present invention. Part number: Silicon semi-conductor base material or well area -------------------------- 10 pad oxide layer ------ -1 1 Nitride sand layer ------------------------------------ 12 Active area ---- ------ 111 field isolation zone ------- 112 channel cut-off zone ----- 1 6 field oxide layer ------------------- ----------------- 1 7 —6 1 (please read "Precautions on the back and then write this page"). Pack. Order .. Line. TtJi Zhongzhong The standard is printed by oc. Y. Co., Ltd. This paper scale is in accordance with the Chinese B family standard (CNS) A 4 specifications (210 X 297 public ») A6 B6 V. Description of invention () Gate oxide layer ------ --- 19 First polycrystalline sand (levitation off) --------- 21 Intermediate dielectric layer ... 22 Second polycrystalline silicon (control cabinet)- ------------------------ 23 Insulation oxidation) g ----- 211 Isolation insulation layer ------------ --------------------- 2 3 1 Photoresist (PR) .............................. ............. 25 Strip layer stacking manufacturing ------------------------------ --24 tl m --------------- 26 Block β-layer structure ------------ -------------------- 27 The source and drain regions of the light army of the buried layer bit line -------------------------------- - 29 Source-drain region (bit line region) ------------------------ 30 Figure 3Α-3Ε and «4Α-4Ε are based on this The invention is a cross-sectional view of each main process along the lines AA 'and BB' of FIG. 2. First, please refer to FIG. 3Α, 4Α a buried layer bit line mask is formed on the p-type silicon semiconductor substrate or well region 10 to expose the source drain region 29 (ie, the bit line region) of the memory cell to be exposed to other regions. The K photoresist PR is covered, and then a high concentration of N-type heterodyne ions such as arsenic ions are implanted under the condition that the suspension can be about 35Kev at a dose of about 1015cm · 2, as shown in FIGS. 3A and 4A. After the removal of the photo sister, the entire wafer is oxidized at high temperature. Since the growth rate of the oxide layer and the concentration of the impurities contained are M, which means that the high impurity concentration has the characteristics of enhancing the growth rate of the oxide layer, it grows thicker in the original photoresist area A gate oxide layer 19 of about 100 angstroms grows a thick oxide layer (thickness of about 300 or 600 angstroms) on the source drain region 29 of the memory cell to be formed. While performing high-temperature oxidation, N-type impurity ions will be exposed to high temperature Drive and expand ------------- ^ -------- installed ------ order ----- ", line < Please read "Notes on the back" first Rewrite this page) 7
經濟部中央標準局Λ工消费合作社印K 82. 9. 6,000 本紙張尺度適用中國國家標翠（CNS)甲4规格（210 X 297公货〉 A6 B6 五、發明説明（） 散形成一若干條狀之源極汲極區30(即位元線區），然後再 進行一懋浮閘電晶體起始電壓調整之雜質雛子植入如圖3B 所示。而在圖 2之B-B’線因皆無雜質離子植入因此無厚氧 化層20產生，如圖4B所示。 接著，依序沉積一含高濃度雜質摻雜之第一複晶矽21 及中間介電層22,其中複晶矽内之雑質可藉由離子植入， 雜質擴敗或現場植入程序Un-situ process)等方法達成， 又中間介電層 22亦可為一種由氧化矽一氮化矽一氧化矽 (oxide-ni*tride-〇xide 0N0)三種材質ft層所構成的。然 後經一光罩照相，蝕刻後形成間斷懸浮閛21,其一端則位 於通道區内。接著進行一加強型（enhanced type)電晶膀 起始電壓調整之雜質離子植入，即如圚3C,4C所示。 再經熱氧化則於第一複晶矽21邊緣成長一絕緣氧化層 211而在其餘氧化物速率則非常慢。然後沉積第二複晶矽 並高濃度雜質摻雜及經一光罩照相，叠層蝕刻後形成控制 閘23(即字線）如圈3D, 4D所示。又由圖3D明顗示出懸浮閘 電晶體（通道畏度以Lf代表）係與加強型電晶體（通道長度 Le代表）係呈串聯因該加強型電晶體於擦拭狀態係圼斷路 故可防止因過度擦拭造成之漏電流。惟若Le值太小則易使 電晶趙導通便無法達到上述之功效，一般而言Le值需至少 為0.3微米。同時由匾4D可看出由於第二複晶矽23蝕刻與 第一複晶矽21係連鑲蝕刻完成的，因此第二複晶矽23與第 一複晶矽21具有自我對準之作用。在圖2之代號”F”中部份 區域之矽半導雔基體表面因為在叠層蝕刻時並未被第一複 晶矽21所覆蓋，因此當蝕刻完第一複晶矽21後形成一凹槽 --------!II^J («·先閱讀背面之注意事項再塡寫本頁) 裝‘ 訂· 線. tt濟部中-Λ標準渴Λ工消费含作 -8 - 82. 9, 6,000 本坻張尺度通用中ΗΒ家標準（CNS〉甲4規格（210 X 297公> A6 B6 五、發明説明（） 之後，藉沉積一絕緣靥及蝕刻回去（etch-back)技術 使其在由第一複晶矽21,中間介電層22及第二複晶矽23構 成之叠層構造邊緣形成有隔離絕緣層231 ,其主要作用係 確保當第二複晶矽頂部與耐高溫金靨形成矽化物之同時於 ft層構造邊緣不會產生，否則會造成第一與第二複晶矽間 之短路，同時又因隔離絕緣層231之蝕刻速率造較B.P.S.G 者為慢，因此可適度地保護叠層構造。之後，再進行一全 面性與矽半専體基材同一導電型即 P型雜質雔子植入該步 驟又稱場離子植入。該雜質之劑量需滿足下列二條件下取 得最佳值；即一是有效地防止兩位元媒間之擊穿現象，另 一則是位元線區内有部份未被複晶矽覆蓋其N型雜質濃度 將被部份補償掉，導致P-N接面崩漬電壓降低，因P型濃度 不可太澹否則易使位元線之PN接面易於崩潰，如画4E所示。 反観在通道區内因受複晶矽之保護，故矽半導®基體 10之表面雜質濃度並未受到場離子植入之影響，如圖3E所 示。又場離子植入在符合前述二要件之最佳條件係在能量 約30Kev,劑量約5X 1012-2X 1013之範圍所達成的。 在圖3E, 4E之後續製程即包含典型之互補式金氧半導 賭製程，其中包括周邊線路之源極汲極形成，硼矽酸鹽玻 璃之沉積，整形（Reflow),及接觸窗，金颺層之光罩照相 ，蝕刻等。 本發明與習知技術（即圖1A-1G)相比較具下列數優點即 是：本發明兩位元線30間之電性隔離係藉植入與矽半導體 基材或井區同一導電型之雜質離子Μ提高場起始電壓而達 —9 — (請先閱讀背面之注意事項再塡寫本頁) 丨裝. 訂· 線· 經濟部中喪標举扃Λ工消费合作社印製 本紙张尺度通用中國國家標準（CNS)甲4规格（210 X 297公釐〉 82. 9. 6,000 A6 B6 五、發明説明（） 成的，且其位置在圖2中代號”F”所示之區域。因此可免除 如習知般箱氮化矽沉積，蝕刻及場區氧化等繁雑步驟方能 達成活蹯區間電性隔離之目的。且由於場氧化層形作之同 時伴生之鳥啄（bird’s beak)造成晶片面積浪費之問題於本 發明中可獲得徹底性地解決，故本發明較習知技術更具有 使元件高密度化之功效。 然，本發明之最佳實施例雖已揭兹，凡本行業者根据 前面最佳實施例所做之等功效替換，單純姐合皆屬本案之 實質精神範睡I。 (請先《讀背面之注意事項再塡寫本頁) 裝· 訂‘ 線· 經濟部中夬標準局R工消費合作社印製 -10- 本紙张尺次通用中SB家標準（CNS)甲4规格（210 X 297公货） 82. 9. 6,000Printed by the Central Standards Bureau of the Ministry of Economic Affairs, K 82. 9. 6,000 This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 public goods) A6 B6 V. Description of invention () Formed into a number of articles The source-drain region 30 (that is, the bit line region) of the shape, and then implantation of an impurity child with an initial voltage adjustment of the floating gate transistor is shown in FIG. 3B. The BB ′ line in FIG. 2 is due to There is no impurity ion implantation and therefore no thick oxide layer 20 is produced, as shown in FIG. 4B. Next, a first polycrystalline silicon 21 and an intermediate dielectric layer 22 doped with high concentrations of impurities are deposited in sequence, in which the polycrystalline silicon The quality can be achieved by ion implantation, impurity diffusion or un-situ process, and the intermediate dielectric layer 22 can also be a silicon oxide-silicon nitride-oxide (oxide- ni * tride-〇xide 0N0) ft layer composed of three materials. After taking a photo with a photomask, an intermittent suspended dung 21 is formed after etching, and one end is located in the passage area. Then, an enhanced type of implanted impurity ion implantation of the initial voltage of the transistor is carried out, as shown in 3C and 4C. After thermal oxidation, an insulating oxide layer 211 is grown on the edge of the first polycrystalline silicon 21 and the rate of the remaining oxides is very slow. Then, a second polycrystalline silicon is deposited and doped with high-concentration impurities and photographed through a photomask. After the stack etching, a control gate 23 (ie, word line) is formed as shown in circles 3D and 4D. 3D shows that the floating gate transistor (channel fear is represented by Lf) and the reinforced transistor (channel length Le represents) are in series. The reinforced transistor can be prevented from breaking in the wipe state. Leakage current caused by excessive wiping. However, if the Le value is too small, it is easy for the transistor to turn on and the above-mentioned effect cannot be achieved. Generally speaking, the Le value needs to be at least 0.3 microns. At the same time, it can be seen from the plaque 4D that since the etching of the second polycrystalline silicon 23 and the first polycrystalline silicon 21 are consecutively etched, the second polycrystalline silicon 23 and the first polycrystalline silicon 21 have a self-aligning effect. The surface of the silicon semiconductor substrate in a part of the codename "F" in FIG. 2 is not covered by the first polycrystalline silicon 21 during the stacked etching, so when the first polycrystalline silicon 21 is etched, a surface is formed Groove --------! II ^ J («· Read the precautions on the back before writing this page) Binding 'Order · Line. TtJizhong-Λstandard thirsty Λ 工 consumption included as -8 -82. 9, 6,000 The standard of the general standard of the HB standard (CNS> A4 specifications (210 X 297 g > A6 B6) 5. Description of invention (), by depositing an insulating tungsten and etching back (etch-back ) Technology to form an isolation insulating layer 231 on the edge of the stacked structure composed of the first polycrystalline silicon 21, the intermediate dielectric layer 22 and the second polycrystalline silicon 23, the main function of which is to ensure that the top of the second polycrystalline silicon At the same time as the formation of silicide with high temperature resistant gold, it will not occur at the edge of the ft layer structure, otherwise it will cause a short circuit between the first and second polycrystalline silicon, and the etching rate of the isolation insulating layer 231 is slower than that of the BPSG Therefore, the laminated structure can be properly protected. Afterwards, a comprehensive conductivity type that is the same conductivity type as the silicon semi-substrate substrate, that is, the P-type impurity can be carried out. This step of implantation is also called field ion implantation. The dose of the impurity must meet the following two conditions to obtain the best value; one is to effectively prevent the breakdown between the two-bit medium, and the other is in the bit line area Some of them are not covered by polycrystalline silicon, and their N-type impurity concentration will be partially compensated, resulting in a decrease in the PN junction breakdown voltage. Because the P-type concentration should not be too large, otherwise the PN junction of the bit line is prone to collapse. As shown in picture 4E. Since the channel area is protected by polycrystalline silicon in the channel area, the surface impurity concentration of the silicon semiconductor substrate 10 is not affected by field ion implantation, as shown in FIG. 3E. The best conditions to meet the above two requirements are achieved in the range of energy of about 30Kev and dose of about 5X 1012-2X 1013. The subsequent processes in Figures 3E and 4E include typical complementary gold-oxygen semi-conducting gambling processes, These include the formation of the source drain of the peripheral circuit, the deposition of borosilicate glass, reflow, and contact windows, the photomask of the gold layer, etching, etc. The present invention and the conventional technology (ie, FIG. 1A- 1G) Compared with the following advantages: The electrical isolation is achieved by implanting impurity ions M of the same conductivity type as the silicon semiconductor substrate or the well area to increase the field starting voltage to -9 — (please read the precautions on the back before writing this page). Order · Line · Printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs. The paper standard of the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 82. 9. 6,000 A6 B6 V. Description of invention () And its location is in the area indicated by the code "F" in Figure 2. Therefore, the conventional silicon nitride deposition, etching, and field oxidation and other cumbersome steps can be eliminated to achieve electrical isolation between active areas. purpose. Moreover, the problem of wasted wafer area due to the accompanying bird's beak while the field oxide layer is formed can be completely solved in the present invention, so the present invention is more effective than the conventional technology in increasing the density of the device . Of course, although the best embodiment of the present invention has been disclosed, where the equivalent replacements made by those in the industry according to the previous best embodiment, the simple sisterhood is the essence of this case. (Please read "Notes on the back side and then write this page"). Binding · Order 'Line · Printed by the Rongong Consumer Cooperative Society of the Central Bureau of Standards of the Ministry of Economics -10- This paper size is commonly used in the SB Family Standard (CNS) A 4 Specifications (210 X 297 public goods) 82. 9. 6,000