JPS63268264A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63268264A JPS63268264A JP10242487A JP10242487A JPS63268264A JP S63268264 A JPS63268264 A JP S63268264A JP 10242487 A JP10242487 A JP 10242487A JP 10242487 A JP10242487 A JP 10242487A JP S63268264 A JPS63268264 A JP S63268264A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- opening part
- photoresist
- opening
- resistance region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明に半導体装置の製造方法に関し、特に高精度イオ
ン注入抵抗素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a high-precision ion implantation resistive element.
従来イオン注入抵抗の製造方法に、Ｎ型半導体基板上に
形成さｔ′したイオン注入時に充分マスキング効果のあ
る厚い酸化膜に周知のＰＲ技術で選択的に抵抗領域であ
る開孔部を形成し、前記開孔部上にイオン注入のチャネ
リング防止用の薄い酸化膜（数百Ａ程度）を形成した後
、前記厚い酸化膜をマスクに、イオン注入し、抵抗を形
成していた。A conventional method for manufacturing an ion-implanted resistor involves selectively forming an opening, which is a resistive region, using a well-known PR technique in a thick oxide film that has a sufficient masking effect during ion implantation and is formed on an N-type semiconductor substrate. After forming a thin oxide film (approximately several hundred amperes) on the opening to prevent channeling of ion implantation, ions were implanted using the thick oxide film as a mask to form a resistor.
上述した従来のイオン注入抵抗の製造方法は。 The above-mentioned conventional ion implantation resistor manufacturing method is as follows.
イオン注入抵抗の精度を決める抵抗幅がフォトレジスト
の抜は及び酸化膜厚のバラツキ及びエツチング液のエッ
チレートのバラツキ等の影響を受ける為、抵抗の精度が
低下するという欠点があった。The resistance width, which determines the accuracy of the ion implantation resistor, is affected by the photoresist removal, variations in the oxide film thickness, and variations in the etching rate of the etching solution, resulting in a reduction in the precision of the resistance.
本発明によｎば、Ｎ型半導体基板上にイオン注入時充分
マスキング効果のある厚い酸化膜を形成し、周知のＰＲ
技術にエフ、目的とする抵抗領域、［：９も大きく酸化
膜をエツチングして開孔部を形成し、前記開孔部表面に
薄い酸化膜全形成させた後、全面にフォトレジストを塗
布し、目的とする抵抗領域の開孔部を前記開孔部より小
さくあけ、薄い酸化膜を介してＰ型不純物イオンをドー
プする。このような構成によれば、仮に前記厚い酸化膜
をエツチングする際、開孔部の大きさにバラツキがあっ
ても目的とする抵抗領域の抵抗幅は、フォトレジストの
抜は幅で決まる為、抵抗の精度の向上が期待できる。According to the present invention, a thick oxide film having a sufficient masking effect during ion implantation is formed on an N-type semiconductor substrate, and
For the desired resistance region, the oxide film is etched to a large size to form an opening, and after a thin oxide film is completely formed on the surface of the opening, a photoresist is applied to the entire surface. , an opening in the target resistance region is made smaller than the opening, and P-type impurity ions are doped through the thin oxide film. According to such a configuration, even if there is variation in the size of the opening when etching the thick oxide film, the resistance width of the target resistance region is determined by the width of the photoresist. It is expected that the accuracy of the resistance will improve.
本発明に、Ｎ型半導体基板上にイオン注入時充分マスキ
ング効果のある厚い酸化膜を形成し１周知のＰＲ技術に
よジ、目的とする抵抗領域よりも大きく酸化膜をエツチ
ングして開孔部を形成し、前記開孔部表面に薄い酸化膜
を形成させ、さらに全面に７オトレジストを塗布し、フ
ォトレジストに目的とする抵抗領域の開孔部を前記開孔
部よジ小さくあけ、前記薄い酸化膜を介してＰ型不純物
イオンをドープする。以上の方法Ｖｃよジ、従来の方法
による抵抗領域のサイドエッチのバラツキ全はとんどな
くすることが出来、かつ精度の良いイオン注入抵抗が出
来る効果がある。In the present invention, a thick oxide film with a sufficient masking effect is formed on an N-type semiconductor substrate during ion implantation, and the oxide film is etched to a size larger than the desired resistance region using well-known PR technology to form an opening. , form a thin oxide film on the surface of the opening, apply 7 photoresist to the entire surface, make an opening in the desired resistance region smaller than the opening in the photoresist, and form a thin oxide film on the surface of the opening. P-type impurity ions are doped through the oxide film. The above method Vc has the effect that all the variations in side etching of the resistance region caused by the conventional method can be almost completely eliminated, and a highly accurate ion implantation resistor can be obtained.
し実施例〕 次に不発明について図面を参考にして説明する。Example] Next, non-invention will be explained with reference to the drawings.
まず、Ｐ型半導体基板１の表面にＮ型エピタキシャル領
域２を形成し、酸化膜３をＮ型エピタキシャル領域２上
へ形成する。（同図（ａ））次に周ものＰＲ技術にエフ
１選択的に開孔部４全形成する。（同図（ｂ））
次に開孔部４上に薄い酸化膜（４００Ａ程度）５を形成
する。その後、フォトレジスト６を全面に塗布し、周知
のＰＲ技術に、ｌ：り開孔部７を形成する（同図（Ｃ）
）次にフォトレジスト６をマスクに。First, an N-type epitaxial region 2 is formed on the surface of a P-type semiconductor substrate 1, and an oxide film 3 is formed on the N-type epitaxial region 2. (FIG. 1(a)) Next, the entire opening 4 is formed selectively in F1 using the PR technique on the periphery. ((b) in the same figure) Next, a thin oxide film (approximately 400 Å) 5 is formed on the opening 4. After that, a photoresist 6 is applied to the entire surface, and a hole 7 is formed using a well-known PR technique (see (C) in the same figure).
) Next, use photoresist 6 as a mask.
かつ、酸化膜５を介して、Ｐ型不純物イオンをイオン注
入でドープすることにより、抵抗領域８を形成する。（
同図（ｄ））
次に抵抗領域８のコンタクトホール９を形成し、最後に
厚キ１．３〜１．７μｍ８度のアルミニウム１０を用い
て電極を形成する。（同図（ｅ））Furthermore, a resistance region 8 is formed by doping P-type impurity ions through the oxide film 5 by ion implantation. (
((d) in the figure) Next, a contact hole 9 for the resistance region 8 is formed, and finally an electrode is formed using aluminum 10 with a thickness of 1.3 to 1.7 μm and 8 degrees. (Figure (e))
第１図（ａ）〜（ｅ）は本発明の一実施例についての製
造工程順の半導体基板の断面図である。
１−・−・−・Ｐ型半導体基板、２・・・・・・Ｎ型エ
ピタキシャル層、３・・・・・・酸化膜、４・・・・・
・開孔部、５・−・・・・酸化膜、６・・・・・・フォ
トレジスト、７・・・・・・Ｋ孔部、 ｓ・・・・−・
抵抗領域、９・・−・・・コンタクトホール、１ｏ・・
・・・・アルミ電極。
一゛邑
−５〜
第１回
（（Ｌ） 「＝＝＝＝：＝＝：＝：＝＝＝ｚ＝＝
Ｆ〜／？３
ＣＩ）ノ 「＝＝＝：＝：；；＝ムニ
７＝耳＝＝＝＝；＝＝ニニ１／ ？
（Ｃ，）トｉ〒〒＝；＝＝〒＝モβ＝ニブ＝〒＝〒〒〒
［；二７５ ″
ｔｅｌ） ■〒＝ｉヒ＝〒］３
／ ？
δ ２FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor substrate in the order of manufacturing steps according to an embodiment of the present invention. 1-...P-type semiconductor substrate, 2...N-type epitaxial layer, 3...Oxide film, 4...
・Opening area, 5---Oxide film, 6---Photoresist, 7---K hole area, s------
Resistance region, 9...Contact hole, 1o...
...Aluminum electrode. Ichimura-5~ 1st ((L) ``====:==:=:===z==
F~/? 3 CI)ノ ``===:=:;;=Muni7=ear====;==Nini1/? (C,)Toi〒〒=;==〒=Moβ=Nib=〒= 〒〒〒
[;275″ tel) ■〒=ihi=〒]3 / ? δ 2
Claims (1)
膜に、選択的に第１開孔部を設け、該開孔部表面に、第
２酸化膜を形成させた後、前記第１酸化膜及び第２酸化
膜上にフォトレジストを塗布し、前記第１開孔部分に、
該開孔部より、小さい第２開孔部を前記フォトレジスト
に設け、然る後、前記第２開孔部に、前記第２酸化膜を
介して、第２導電型不純物イオンをドーピングすること
を特徴とする半導体装置の製造方法。A first oxide film is formed on a first conductivity type semiconductor substrate, a first opening is selectively provided in the oxide film, and a second oxide film is formed on the surface of the opening. A photoresist is applied on the first oxide film and the second oxide film, and in the first opening part,
A second opening smaller than the opening is provided in the photoresist, and then the second opening is doped with impurity ions of a second conductivity type through the second oxide film. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10242487A JPS63268264A (en) | 1987-04-24 | 1987-04-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10242487A JPS63268264A (en) | 1987-04-24 | 1987-04-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63268264A true JPS63268264A (en) | 1988-11-04 |
Family
ID=14327071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10242487A Pending JPS63268264A (en) | 1987-04-24 | 1987-04-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63268264A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57103345A (en) * | 1980-12-18 | 1982-06-26 | Clarion Co Ltd | Manufacture of semiconductor device |
| JPS6142914A (en) * | 1984-08-06 | 1986-03-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61129824A (en) * | 1984-11-27 | 1986-06-17 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1987
- 1987-04-24 JP JP10242487A patent/JPS63268264A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57103345A (en) * | 1980-12-18 | 1982-06-26 | Clarion Co Ltd | Manufacture of semiconductor device |
| JPS6142914A (en) * | 1984-08-06 | 1986-03-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61129824A (en) * | 1984-11-27 | 1986-06-17 | Fujitsu Ltd | Manufacture of semiconductor device |
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