JPS6134966A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6134966A JPS6134966A JP15610984A JP15610984A JPS6134966A JP S6134966 A JPS6134966 A JP S6134966A JP 15610984 A JP15610984 A JP 15610984A JP 15610984 A JP15610984 A JP 15610984A JP S6134966 A JPS6134966 A JP S6134966A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- etching
- type semiconductor
- semiconductor substrate
- formation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 238000000206 photolithography Methods 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims 1
- 238000005121 nitriding Methods 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 5
- 238000001259 photo etching Methods 0.000 abstract 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 240000000220 Panda oleosa Species 0.000 description 1
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体装置の製造方法特にイオン注入法により
ネ細物を半導体基板中に導入して形成された半導体領域
を抵抗体として使用する半導体装置の製造方法に関する
。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor device manufacturing method, particularly a semiconductor device in which a semiconductor region formed by introducing a thin material into a semiconductor substrate by an ion implantation method is used as a resistor. The present invention relates to a method for manufacturing a device.
(従来の技術)
従来、イオン注入法により不純物を半導体基板中に導入
し抵抗体として使用するいわゆるイオン注入抵抗は高抵
抗が容易にできるので半導体集積回路等に広く用いられ
ている。(Prior Art) Conventionally, so-called ion implantation resistors, in which impurities are introduced into a semiconductor substrate by ion implantation and used as a resistor, have been widely used in semiconductor integrated circuits and the like because high resistance can be easily achieved.
しかし、従来のイオン注入抵抗はイオン注入法によりネ
細物を半導体基板中に導入した後次工程の拡散工程のマ
スクとするため或いはメタライズ工程の準備のために酸
化工程を行ない、イオン注入法によp不純物を導入した
半導体領域上に酸化膜を形成しているが、この酸化工程
において半導体基板狭面の不純物が酸化膜中へ入シ、こ
のため不純物磯度にバラツキが生じイオン注入抵抗のシ
ート抵抗にバラツキを生じるという致命的欠点があった
。特に不純物が酸化膜中に入る割合いは歳化の条件の変
動に大きく影響されるものであった。However, in the conventional ion implantation resistor, after the thin material is introduced into the semiconductor substrate by the ion implantation method, an oxidation process is performed to use it as a mask for the next diffusion process or to prepare for the metallization process. An oxide film is formed on a semiconductor region into which p-type impurities have been introduced, but during this oxidation process, impurities on the narrow surface of the semiconductor substrate enter the oxide film, resulting in variations in the degree of impurity and a decrease in ion implantation resistance. This had the fatal drawback of causing variations in sheet resistance. In particular, the rate at which impurities enter the oxide film is greatly affected by changes in aging conditions.
(発明が解決しようとする問題点)
本発明の目的はかかる従来のイオン注入抵抗の製造方法
の持つ欠点を解消し、シート抵抗のバラツキの少い抵抗
を得ることにある。(Problems to be Solved by the Invention) An object of the present invention is to eliminate the drawbacks of the conventional method for manufacturing an ion-implanted resistor, and to obtain a resistor with less variation in sheet resistance.
(問題点を解決するための手段)
本発明によれば、−導電型半導体基板に酸化膜を成長さ
せる工程と、この酸化膜を写真蝕刻法により選択的にエ
ツチングする工程と、選択エツチングされた酸化膜をマ
スクとしてイオン注入法により他の導電型の不純物を半
導体基板中に導入して他の導電型半導体領域を形成する
工程と、その後写真蝕刻法により前記酸化膜を更に選択
的にエツチングして半導体基板の他の領域を露出する工
程と、その後全面に窒化膜を成長し、酸化膜の除去され
た他の領域上の窒化膜の1部を選択的に除去しコンタク
ト部を形成する工程とを有し、前記他の導電型半導体領
域を抵抗体として使用することを特徴とする半導体装1
dの製造方法を得る。(Means for Solving the Problems) According to the present invention, - a step of growing an oxide film on a conductive type semiconductor substrate, a step of selectively etching the oxide film by photolithography, and a step of selectively etching the oxide film by photolithography; A step of introducing impurities of other conductivity type into the semiconductor substrate by ion implantation using the oxide film as a mask to form a semiconductor region of another conductivity type, and then further selectively etching the oxide film by photolithography. a step of exposing other regions of the semiconductor substrate, and then a step of growing a nitride film over the entire surface, and selectively removing a part of the nitride film on the other region where the oxide film has been removed to form a contact portion. A semiconductor device 1 characterized in that the other conductive type semiconductor region is used as a resistor.
Obtain the manufacturing method of d.
(実施例) 以下、本発明を図面を用いてより詳細に説明する。(Example) Hereinafter, the present invention will be explained in more detail using the drawings.
第2図は従来のイオン注入抵抗の製法の1例を示す各工
程での断面図である。まずN型半導体基板1を準備しく
第2図(a) ) 、このN型半導体基板1を酸化雰囲
気中で酸化して酸化膜2を形成しく第2図(b) )
s次に写真蝕刻法により酸化膜2を選択的にエツチング
して、開孔領域3を形成しく第2図(c) ) 、次に
イオン注入法によfiP型不純物領域4を形成した(第
2図(d))後酸化工程を経て酸化膜5を形成した(第
2図(e))のち、写真蝕刻法により選択的に酸化膜2
をエツチングし次工程の不純物拡散領域の形成のための
凹部或いはコンタクト孔6aを形成する(第2図(f)
)。FIG. 2 is a cross-sectional view at each step showing an example of a conventional method for manufacturing an ion-implanted resistor. First, an N-type semiconductor substrate 1 is prepared (FIG. 2(a)), and this N-type semiconductor substrate 1 is oxidized in an oxidizing atmosphere to form an oxide film 2 (FIG. 2(b)).
Next, the oxide film 2 was selectively etched by photolithography to form an opening region 3 (FIG. 2(c)), and then the fiP type impurity region 4 was formed by ion implantation (FIG. 2(c)). After forming the oxide film 5 through a post-oxidation process (Fig. 2(d)), the oxide film 2 is selectively removed by photolithography.
A recess or contact hole 6a for forming an impurity diffusion region in the next step is formed by etching (FIG. 2(f)).
).
このような従来のイオン注入抵抗の製法においては、イ
オン注入法によりネ細物を導入した後酸化工程を行なう
ため、酸化のバラツキがそのままイオン注入抵抗のシー
ト抵抗のバラツキとなシ、本来高精度であるイオン注入
法の長所が全く生かされないという欠点があった。In this conventional manufacturing method for ion-implanted resistors, the oxidation process is performed after introducing fine particles by ion implantation, so variations in oxidation do not directly result in variations in the sheet resistance of the ion-implanted resistors, making them inherently highly accurate. The drawback was that the advantages of the ion implantation method were not fully utilized.
本発明は前記イオン注入抵抗の製法の持つ致命的欠点を
解消するものである。The present invention eliminates the fatal drawbacks of the above-mentioned method of manufacturing ion implanted resistors.
本発明の一実施例の谷製造工程での断面図を第1図に示
す。まずN型半導体基板1を準備しく第1図Ta) )
、このN型半導体基板1を酸化雰囲気中で酸化して酸化
膜2を形成した(第1図(b))後、写真蝕刻法により
選択的に酸化膜2をエツチングしく第1図(c))、イ
オン注入法によ、9P型不純物を半導体基板1中に導入
してP型半導体領域4を形成して抵抗体としく第1図(
d) ) S次に、写真蝕刻工程により選択的に酸化膜
2をエツチングして他の拡散層のコンタクト孔6bを形
成した後(第1図(e) ) 、減圧CVD法により全
面に窒化膜7を形成しく第1図(f) ) s次に写真
−剣法により窒化膜7をコンタクト孔6b内部を含み選
択的にエツチングしてコンタクト孔を完成させ(第1図
(g))、その後にメタライズ工程を行なうものである
。FIG. 1 shows a cross-sectional view of a valley manufacturing process according to an embodiment of the present invention. First, prepare the N-type semiconductor substrate 1 (see Figure 1 (Ta)).
After this N-type semiconductor substrate 1 was oxidized in an oxidizing atmosphere to form an oxide film 2 (FIG. 1(b)), the oxide film 2 was selectively etched by photolithography as shown in FIG. 1(c). ), a 9P type impurity is introduced into the semiconductor substrate 1 by ion implantation to form a P type semiconductor region 4 to form a resistor as shown in FIG.
d) ) S Next, after selectively etching the oxide film 2 using a photolithography process to form a contact hole 6b for another diffusion layer (FIG. 1(e)), a nitride film is formed on the entire surface using a low pressure CVD method. 7 (Fig. 1(f)) s Next, the nitride film 7 is selectively etched including the inside of the contact hole 6b using a photographic technique to complete the contact hole (Fig. 1(g)), and then This is a metallization process.
本発明によると、イオン注入法によ#)P型不純物を導
入した後に酸化工程がないため、酸化によるP型半導体
層4の表面濃度のバラツキがないため高精度のイオン注
入抵抗を容易に実現できるという大きな利点がある。According to the present invention, since there is no oxidation step after introducing the P-type impurity using the ion implantation method, there is no variation in the surface concentration of the P-type semiconductor layer 4 due to oxidation, so a highly accurate ion implantation resistor can be easily realized. There is a big advantage that it can be done.
なお以上の説明において導電型を互いに入れ換えてもそ
のまま成立することは言うまでもない。It goes without saying that the above description holds true even if the conductivity types are interchanged.
(発明の効果)
本発明によれば、イオン注入後の熱処理条件に影響され
ないシート抵抗をもつ抵抗を得ることができる。(Effects of the Invention) According to the present invention, a resistor having a sheet resistance that is not affected by heat treatment conditions after ion implantation can be obtained.
第1図(a)〜(g)は本発明の一実施例による各製造
工程での断面図であシ、第2図(a)〜(f)は従来の
製造工程における断面図である。
1・・・−・・N型半導体基叡、2・・・・・・酸化膜
、3・旧・・酸化膜開孔部、4・・・・・・P型半導体
領域、5・・・・・酸化膜、6a・・・・・・開孔部、
6b・・・・・・開孔部、7・・・・・・窒化膜、8・
・・・・・開孔部。
槃 l @
第 2 図FIGS. 1(a) to (g) are cross-sectional views of each manufacturing process according to an embodiment of the present invention, and FIGS. 2(a) to (f) are cross-sectional views of conventional manufacturing processes. 1... N-type semiconductor substrate, 2... Oxide film, 3... Old oxide film opening, 4... P-type semiconductor region, 5... ...Oxide film, 6a...Opening part,
6b...Opening portion, 7...Nitride film, 8.
...opening area. Kana l @ Figure 2
Claims (1)
記酸化膜を写真蝕刻法により選択的にエッチングする工
程と、前記酸化膜をマスクとしてイオン注入法により他
の導電型の不純物を前記半導体基板中に導入して他の導
電型半導体領域を形成する工程と、その後写真蝕刻法に
より前記酸化膜を選択的にエッチングして前記半導体基
板の他の領域を露出する工程と、その後全面に窒化膜を
成長し、前記他の領域上の窒化膜を選択的に除去しコン
タクト部を形成する工程とを有し、前記他の導電型の半
導体領域を抵抗体として使用することを特徴とする半導
体装置の製造方法。A step of growing an oxide film on a semiconductor substrate of one conductivity type, a step of selectively etching the oxide film by photolithography, and an ion implantation method using the oxide film as a mask to implant impurities of another conductivity type into the semiconductor substrate. A step of introducing the oxide film into the substrate to form another conductive type semiconductor region, a step of selectively etching the oxide film by photolithography to expose another region of the semiconductor substrate, and then nitriding the entire surface. a step of growing a film and selectively removing a nitride film on the other region to form a contact portion, and using the semiconductor region of the other conductivity type as a resistor. Method of manufacturing the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15610984A JPS6134966A (en) | 1984-07-26 | 1984-07-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15610984A JPS6134966A (en) | 1984-07-26 | 1984-07-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6134966A true JPS6134966A (en) | 1986-02-19 |
Family
ID=15620505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15610984A Pending JPS6134966A (en) | 1984-07-26 | 1984-07-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6134966A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04109770U (en) * | 1991-03-01 | 1992-09-22 | 株式会社リコー | Image forming device |
-
1984
- 1984-07-26 JP JP15610984A patent/JPS6134966A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04109770U (en) * | 1991-03-01 | 1992-09-22 | 株式会社リコー | Image forming device |
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