JPS63261729A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63261729A JPS63261729A JP9535987A JP9535987A JPS63261729A JP S63261729 A JPS63261729 A JP S63261729A JP 9535987 A JP9535987 A JP 9535987A JP 9535987 A JP9535987 A JP 9535987A JP S63261729 A JPS63261729 A JP S63261729A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- oxide film
- silicon oxide
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 23
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 14
- 150000002500 ions Chemical class 0.000 abstract description 5
- -1 nitrogen ions Chemical class 0.000 abstract description 5
- 241000293849 Cordylanthus Species 0.000 abstract description 4
- 238000001039 wet etching Methods 0.000 abstract description 2
- 238000010894 electron beam technology Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 24
- 238000005566 electron beam evaporation Methods 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 101150098533 SOST gene Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の製造方法に係り、より詳しくは半
導体素子分離領域の形成方法に関するものでおる。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a semiconductor device isolation region.
従来、この糧の半導体集積回路の素子分離領域の形成方
法としては、例えば「特公昭４５−４１４５５号公報、
特公昭４７−６１３１号公報」に開示されている様に、
耐酸化性のシリコン窒化膜（Ｓｉ３Ｎ４）を用いた選択
酸化法が一般に知られている。然るに、この選択酸化法
では、周知の様に特にバーズビークの発生から素子分離
領域の拡がりが大きくなり、Δターンデザイン上大きな
制約を与える。Conventionally, methods for forming element isolation regions in semiconductor integrated circuits have been disclosed in Japanese Patent Publication No. 45-41455,
As disclosed in Japanese Patent Publication No. 47-6131,
A selective oxidation method using an oxidation-resistant silicon nitride film (Si3N4) is generally known. However, as is well known, in this selective oxidation method, the expansion of the element isolation region becomes large due to the occurrence of bird's beaks, which imposes a large restriction on the Δ-turn design.
近年、ＶＬＳＩ化が進み半導体素子並びに素子分離領域
の微細化が強く要求されている。そのため、前記選択酸
化法に代わる素子分離領域の形成方法として、ＩＶＤ法
という窒素イオンとシリコン電子ビーム蒸着を同時に行
なう方法を用いて、化学量論的組成の制御されたシリコ
ン窒化膜形成方法が開発されている。In recent years, with the advancement of VLSI, there is a strong demand for miniaturization of semiconductor elements and element isolation regions. Therefore, as an alternative method for forming element isolation regions to the selective oxidation method, a method for forming a silicon nitride film with a controlled stoichiometric composition was developed using the IVD method, a method in which nitrogen ions and silicon electron beam evaporation are performed simultaneously. has been done.
以下、第２図（ａ）乃至（ｄ）に従来方法の工程図を示
して、ＩＶＤ法により形成したシリコン窒化膜の素子分
離法を説明する。Hereinafter, a device isolation method for a silicon nitride film formed by the IVD method will be described with reference to FIGS. 2(a) to 2(d) showing process diagrams of the conventional method.
先ず、第２図（ａ）に示す如く、Ｐ型シリコン基板（以
下基板という）ｌを真空度が２ Ｘ １Ｏ−６Ｔｏｒｒ
程度のチャンバー内にセットし、窒素イオンを加速電圧
５〜２０ ＫｅＶ 、電流密度０．０５〜５ｍＡ／ｃ！
ｉで１〜３５分程度前記基板１０表面部位に打ち込むと
同時にシリコンの電子ビーム蒸着を蒸着速度４０９ｍ１
ｎで行なう。斯くして、前記基板ｌ上に窒素イオンとシ
リコン原子との直接反応によって、窒素イオン注入層２
及びシリコン窒化膜３が順次形成される。尚、ＩＶＤ法
により形成された該シリコン窒化膜３は６００＾程度の
深さ迄均質に形成される。First, as shown in FIG. 2(a), a P-type silicon substrate (hereinafter referred to as a substrate) is placed at a vacuum level of 2 x 1O-6 Torr.
Nitrogen ions are accelerated at a voltage of 5 to 20 KeV and a current density of 0.05 to 5 mA/c.
i for about 1 to 35 minutes on the surface of the substrate 10, and at the same time, electron beam evaporation of silicon was performed at a deposition rate of 409 m1.
Do it with n. In this way, a nitrogen ion implantation layer 2 is formed on the substrate l by direct reaction between nitrogen ions and silicon atoms.
and silicon nitride film 3 are sequentially formed. The silicon nitride film 3 formed by the IVD method is uniformly formed to a depth of about 600°.
次に、第２図（ｂ）に示す如く、前記シリコン窒化膜３
上にレジスト膜４を７０００〜５ｏｏｏλ程度塗布した
後、ノ蓼ターニングを施し、開口部５を形成する。Next, as shown in FIG. 2(b), the silicon nitride film 3
After applying a resist film 4 of about 7000 to 500λ on the resist film 4, turning is performed to form an opening 5.
その後、レジスト膜４をマスクとして、前記窒素イオン
注入層２及びシリコン窒化膜３をＲＩＥ法を用いてエツ
チングする。続いて、同しソスト膜４をマスクとして、
素子分離領域の反転防止用不純物（ボロンＢ＋ ）をイ
オン注入（４０ＫｅＶ、 ２Ｘ１０Ｌ３ｔｏｎｓ／ｃｊ
） ｌ、、不純物イオン注入層６を形成する。Thereafter, using the resist film 4 as a mask, the nitrogen ion implantation layer 2 and silicon nitride film 3 are etched using the RIE method. Next, using the same Sost film 4 as a mask,
Ion implantation of impurity (boron B+) for preventing inversion in the element isolation region (40KeV, 2X10L3tons/cj
) l., an impurity ion implantation layer 6 is formed.
しかる後、第２図（Ｃ）に示す如く、前記レジスト膜４
を除去した後、１０００℃、Ｈ，＋ ０．の酸化雰囲気
中で熱的酸化を行なうことにより前記開口部５の不純物
イオン注入層６上に素子分離領域の酸化シリコン膜７を
６０００λ程度成長形成する。そして、第２図（ｄ）に
示す如く、前記シリコン窒化膜３及び窒素イオン注入層
２を熱リン酸によりエツチング除去して、素子分離領域
Ａと素子領域Ｂとを夫々形成していた。After that, as shown in FIG. 2(C), the resist film 4 is
After removing, 1000°C, H, +0. By performing thermal oxidation in an oxidizing atmosphere, a silicon oxide film 7 of about 6000 λ is grown as an element isolation region on the impurity ion implanted layer 6 in the opening 5. Then, as shown in FIG. 2(d), the silicon nitride film 3 and the nitrogen ion-implanted layer 2 were removed by etching with hot phosphoric acid to form an element isolation region A and an element region B, respectively.
然し乍ら、従来の素子分離領域Ａの形成方法においては
、基板１の全面に窒素イオン注入とシリコン電子ビーム
蒸着とを行なうため、素子分離領域Ａのノ臂ターニング
エツチングの際、終点判定が困難となる。そのため、シ
リコン窒化膜３が完全に除去されず、次工程の選択酸化
の際、酸化シリコン膜７の表面７ａ及び境界面７ｂに凹
凸による歪みが生じるという問題点があった。However, in the conventional method for forming the element isolation region A, since nitrogen ion implantation and silicon electron beam evaporation are performed on the entire surface of the substrate 1, it is difficult to determine the end point during the turning etching of the element isolation region A. . Therefore, there is a problem that the silicon nitride film 3 is not completely removed, and distortion occurs due to the unevenness on the surface 7a and the boundary surface 7b of the silicon oxide film 7 during the next step of selective oxidation.
本発明の目的は上述の問題点に鑑み、素子分離領域の酸
化シリコン膜の歪みが防止できる半導体素子の製造方法
を提供するものである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent distortion of a silicon oxide film in an isolation region.
本発明は上述した目的を達成するため、シリコン基板８
上に表面保護膜としての酸化シリコン膜９を形成する工
程と、該酸化シリコン［９を／＃ターニングして開口部
１０を形成する工程と、前記シリコン基板８及び前記酸
化シリコン膜９上にＩＶＤ法を以て、窒化シリコン膜１
１を堆積する工程と、該窒化シリコン膜１１を、エッチ
パック法を以て、前記開口部１０にのみ残留させる工程
と、前記酸化シリコン膜９をエツチング除去する工程と
、前記シリコン基板８上部に不純物イオン注入層１３を
形成した後、高温酸化によって、該不純物イオン注入層
１３上に酸化シリコン膜１４を成長形成する工程とを含
むものである。In order to achieve the above-mentioned object, the present invention provides a silicon substrate 8
A step of forming a silicon oxide film 9 as a surface protection film on the silicon oxide film 9, a step of turning the silicon oxide film 9 to form an opening 10, and forming an IVD film on the silicon substrate 8 and the silicon oxide film 9. The silicon nitride film 1 is
1, a step of leaving the silicon nitride film 11 only in the opening 10 using an etch-pack method, a step of etching away the silicon oxide film 9, and a step of depositing impurity ions on the upper part of the silicon substrate 8. After forming the implanted layer 13, the method includes a step of growing a silicon oxide film 14 on the impurity ion implanted layer 13 by high-temperature oxidation.
本発明においては、予めシリコン基板の素子分離領域に
表面保護膜用の酸化シリコン膜を・臂ターニング形成し
た後、窒化シリコン膜を堆積するので、素子分離領域形
成のための高温酸化後において、素子分離領域における
酸化シリコン膜の表面及び境界面の歪みが防止され、該
酸化シリコン膜は所定形状に形成される。In the present invention, a silicon nitride film is deposited after a silicon oxide film for a surface protection film is formed in advance in the element isolation region of a silicon substrate by turning. Distortion of the surface and interface of the silicon oxide film in the isolation region is prevented, and the silicon oxide film is formed into a predetermined shape.
本発明の半導体素子の製造方法に係る一実施例を第１図
に本発明方法の工程図を示して説明する。An embodiment of the method of manufacturing a semiconductor device of the present invention will be described with reference to FIG. 1, which shows a process diagram of the method of the present invention.
先ず、第１図（ａ）に示す如＜、ｉｏｏ結晶軸を有する
２塁シリコン基板（以下基板という）８に熱的酸化を施
すことによりその主面８ａに保護膜としての酸化シリコ
ン膜９を１０００λ程度形成する。First, as shown in FIG. 1(a), a silicon oxide film 9 as a protective film is formed on a main surface 8a by thermally oxidizing a second base silicon substrate (hereinafter referred to as a substrate) 8 having an ioo crystal axis. Form about 1000λ.
次いで、第１図（ｂ）に示す如く、ホトリソ工程を以て
、前記酸化シリコン膜９をＲＩＥ法によりエツチングし
て、素子分離領域を形成する領域となる開口部１０を形
成する。続いて、前記基＠８を、イオン銃と電子ビーム
蒸着源とを配備すると共に、真空度が概ねＩ Ｘ １０
−１’ Ｔｏｒｒの真空容器内に配置し、室温において
、ＩＶＤ法による低加速エネルギー（約１０ ＫｅＶ
）の窒素イオン注入を行なうと同時に、シリコンの電子
ビーム蒸着を行ない、窒化シリコン膜１１を５０００λ
程度堆積する。その際、基板８の開口部１０側と窒化シ
リコン膜１１の基板８側とには、窒素イオンのみ注入さ
れ、窒素の深さ方向のグロファイルがガウシアン分布に
なっている傾城（窒化シリコン膜）１２が形成される。Next, as shown in FIG. 1(b), the silicon oxide film 9 is etched by RIE using a photolithography process to form an opening 10 which will become a region for forming an element isolation region. Subsequently, the base @8 is equipped with an ion gun and an electron beam evaporation source, and the vacuum level is approximately I x 10.
-1' Torr in a vacuum chamber, and at room temperature, low acceleration energy (approximately 10 KeV
) At the same time as nitrogen ion implantation, electron beam evaporation of silicon is performed to form a silicon nitride film 11 with a thickness of 5000λ.
It accumulates to some extent. At this time, only nitrogen ions are implanted into the opening 10 side of the substrate 8 and the substrate 8 side of the silicon nitride film 11, and the sloped wall (silicon nitride film) in which the nitrogen profile in the depth direction has a Gaussian distribution is formed. 12 is formed.
尚、前記の窒化シリコン膜１１は減圧ＣＶＤ法により形
成した窒化シリコン膜に比較して、基板１に結晶欠陥を
生じさせない低ストレス膜でアリ、前記窒化シリコン膜
１１のシリコンと窒素との組成比は、耐酸化性を有する
ものであれば、必ずしもＳｉ：Ｎが３：４の化学量論的
に安定し次もので無くても良い。而して、第１図（Ｃ）
に示す如く、前記窒化シリコン膜１１をＲＩＢ法を以て
、エッチバックし、前記開口部１０のみに残す。その際
、開口部１０以外の窒化シリコン膜１１が完全にエツチ
ングされているか否かは分光分析法によるＣｏのピーク
の検出により再現性良く制御されるので、エツチング残
りが生じないと共に、エツチング面積が小さくなり、エ
ツチング速度が急に速くなるローディング効果の影響を
受は無い。又、開口部１０に残った窒化シリコン膜１１
の膜厚制御は酸化シリコン膜９の膜厚を変更することで
制御される。The silicon nitride film 11 is a low-stress film that does not cause crystal defects in the substrate 1 compared to a silicon nitride film formed by low-pressure CVD, and the composition ratio of silicon to nitrogen of the silicon nitride film 11 is As long as it has oxidation resistance, it does not necessarily have to have a stable Si:N stoichiometry of 3:4. Therefore, Figure 1 (C)
As shown in FIG. 2, the silicon nitride film 11 is etched back using the RIB method, leaving only the opening 10. At this time, whether or not the silicon nitride film 11 other than the opening 10 is completely etched is controlled with good reproducibility by detecting the Co peak using spectroscopic analysis, so that no etching residue is left and the etching area is reduced. It is not affected by the loading effect, which causes the etching speed to suddenly increase. Moreover, the silicon nitride film 11 remaining in the opening 10
The film thickness is controlled by changing the film thickness of the silicon oxide film 9.
次に、第１図（ｄ）に示す如く、フッ酸等のエツチング
液により前記酸化シリコン膜９をウェットエツチング除
去する。更に、前記基板８の上面に素子分離領域の反転
防止用不純物（ボロンＢ＋）をイオン注入（４０ＫｅＶ
、 ２Ｘ１０Ｌ３ｉｏｎｓ／ｃｄ ） ｌ、、不純物イ
オン注入層１３を形成する。その後、第１図（ｅ）に示
す如＜、１０００℃ウェット酸化雰囲気中で高温酸化を
行ない、該不純物イオン注入層１３上に酸化シリコン膜
１４を６０００＾程度成長形成させる。そして、前記窒
化シリコン膜１１及び１２を熱リン酸によるエツチング
と次工程のホワイトリボン酸化を以て、完全に除去し、
バーズビークの発生が殆ど無い平担な素子分離領域Ｃ及
び素子形成領域りが夫々形成される。Next, as shown in FIG. 1(d), the silicon oxide film 9 is removed by wet etching using an etching solution such as hydrofluoric acid. Further, an impurity (boron B+) for preventing inversion of the element isolation region is ion-implanted (40 KeV) into the upper surface of the substrate 8.
, 2X10L3ions/cd) 1, an impurity ion implantation layer 13 is formed. Thereafter, as shown in FIG. 1(e), high-temperature oxidation is performed in a wet oxidation atmosphere at 1000° C., and a silicon oxide film 14 is grown to a thickness of about 6000° on the impurity ion-implanted layer 13. Then, the silicon nitride films 11 and 12 are completely removed by etching with hot phosphoric acid and white ribbon oxidation in the next step,
A flat element isolation region C and a flat element formation region with almost no bird's beaks are formed.
以上詳細に説明し友様に本発明によれば、低加速エネル
ギーの窒素イオン注入とシリコンの電子ビーム蒸着とを
同時罠行なうＩＶＤ法を用いて、予め素子分離領域に表
面保護膜用の酸化シリコン膜を・ンターニング形成した
シリコン基板上に、窒化シリコン膜を堆積するので、素
子分離領域形成の際の高温酸化後において、素子分離領
域の酸化シリコン膜の表面及び境界面は、マスク寸法通
りに歪みが無く平担に形成できる。従って、素子分離領
域における横方向へのバーズビークの発生及び素子分離
領域パターンの歪みが防止できる。そのため、前記素子
分離領域を微細にできるので、素子の微細化が達成でき
、半導体集積回路の高集積化ができる等の特有の効果よ
り前述の問題を解決し得る。As explained in detail above, according to the present invention, silicon oxide for a surface protective film is pre-coated in an element isolation region using an IVD method that simultaneously performs low acceleration energy nitrogen ion implantation and silicon electron beam evaporation. Since the silicon nitride film is deposited on the silicon substrate on which the film has been patterned, the surface and boundary surfaces of the silicon oxide film in the element isolation region are aligned with the mask dimensions after high-temperature oxidation when forming the element isolation region. It can be formed flat without distortion. Therefore, generation of bird's beak in the lateral direction in the element isolation region and distortion of the element isolation region pattern can be prevented. Therefore, since the element isolation region can be made finer, the above-mentioned problems can be solved by the unique effects such as miniaturization of elements and higher integration of semiconductor integrated circuits.
第１図（ａ）乃至（６）は本発明方法に係る一実施例を
示す工程図、第２図（ａ）乃至（ｄ）は従来方法の工程
図を示すものである。
８・・・シリコン基板（基板）、９・・・酸化シリコン
膜、１０・・・開口部、１１・・・窒化シリコン膜、１
２・・・領域（窒化シリコン膜）、１３・・・不純物イ
オン注入層、１４・・・酸化シリコン膜、Ｃ・・・素子
分離領域、Ｄ・・・素子形成領域。
”ｖ ＥＢ（５７）
１１置置１１
未発１１７ｓｔ／）工ずｉｆＪ
第１図FIGS. 1(a) to (6) are process diagrams showing one embodiment of the method of the present invention, and FIGS. 2(a) to (d) are process diagrams of a conventional method. 8... Silicon substrate (substrate), 9... Silicon oxide film, 10... Opening, 11... Silicon nitride film, 1
2... Region (silicon nitride film), 13... Impurity ion implantation layer, 14... Silicon oxide film, C... Element isolation region, D... Element formation region. ”v EB (57) 11 Placement 11 Unexploded 117st/) Works ifJ Figure 1
Claims (1)
形成する工程と、 該酸化シリコン膜をパターニングして開口部を形成する
工程と、 前記シリコン基板及び前記酸化シリコン膜上にＩＶＤ法
を以て、窒化シリコン膜を堆積する工程と、 該窒化シリコン膜を、エッチバック法を以て、前記開口
部にのみ残留させる工程と、 前記酸化シリコン膜をエッチング除去する工程と、 前記シリコン基板上部に不純物イオン注入層を形成した
後、高温酸化によつて、該不純物イオン注入層上に酸化
シリコン膜を成長形成する工程とを含むことを特徴とす
る半導体素子の製造方法。[Claims] A step of forming a silicon oxide film as a surface protection film on a silicon substrate, a step of patterning the silicon oxide film to form an opening, and a step of forming an opening on the silicon substrate and the silicon oxide film. a step of depositing a silicon nitride film using an IVD method; a step of leaving the silicon nitride film only in the opening using an etch-back method; a step of etching away the silicon oxide film; 1. A method of manufacturing a semiconductor device, comprising the step of forming an impurity ion implantation layer and then growing a silicon oxide film on the impurity ion implantation layer by high-temperature oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9535987A JPS63261729A (en) | 1987-04-20 | 1987-04-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9535987A JPS63261729A (en) | 1987-04-20 | 1987-04-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63261729A true JPS63261729A (en) | 1988-10-28 |
Family
ID=14135445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9535987A Pending JPS63261729A (en) | 1987-04-20 | 1987-04-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63261729A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686348A (en) * | 1996-08-19 | 1997-11-11 | United Microelectronics Corp. | Process for forming field isolation structure with minimized encroachment effect |
-
1987
- 1987-04-20 JP JP9535987A patent/JPS63261729A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686348A (en) * | 1996-08-19 | 1997-11-11 | United Microelectronics Corp. | Process for forming field isolation structure with minimized encroachment effect |
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