JPS6326144A - Digital delay detection circuit - Google Patents

Abstract

PURPOSE:To inexpensively obtain a digital delay detection circuit with high accuracy with a simple constitution by using a counter as a delay element. CONSTITUTION:A counter 3 started at one edge of an FSK (Frequency Shift Keying) signal having a mark frequency fH and a space frequency fL and counting a clock having a prescribed frequency fs, a decoder 4 generating a sampling pulse SPL when the counter counts n-clock and a D flip-flop 2 sampling the FSK by using the pulse SPL are provided to the titled circuit. Then the count (n) is selected to satisfy the relation of 1/2fH<n.1/fs<1/2fL.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital delay detection circuit using a counter as a delay element.

[Conventional technology]

F S K (Frequency 5hift Ke
ying) detection methods include synchronous detection and delayed detection, but delayed detection does not require synchronous regeneration of the carrier wave, so the circuit configuration is simple, and it also has the advantage of being able to respond quickly to burst signals. . There are analog and digital types of delay detection circuits, and the former is constructed using an analog delay element such as a delay line, a mixer, and a low-pass filter.

A conventional digital delay detection circuit is constructed using a shift register 1 as a delay element and a D-type flip-flop (FF) 2 as a phase comparator, as shown in FIG. Figure 6 is a time chart, where e (t) is the waveform-shaped received signal, V (11 is the detected signal, and received signal e (tl is the mark frequency fH by FSK modulation).
If this is delayed by the time τ in the shift register 1 and the rising edge of the output e (at t-) is used as the clock CK of FF2, then the non-delayed received signal e ( The sample-and-hold output Q of tl becomes the detected signal v (t).

The delay time τ due to the shift register 1 is set to τ. fS is a shift clock of this shift register 1, and is set to satisfy fL fH.

[Problem that the invention seeks to solve]

In the shift register type digital delay detection circuit described above, when fH and fL are close to each other, the delay time τ cannot be set appropriately unless the frequency of the shift clock rs is made sufficiently high. Therefore, there is a drawback that the number of stages of the shift register 1 increases significantly.

The present invention attempts to solve the above drawbacks by replacing the delay element with a counter.

[Means for Solving the Problems] FIG. 1 is a basic configuration diagram of the present invention, in which 2 is a D-FF, 3 is a counter, and 4 is a decoder. Counter 3 receives the received signal e
(SET) at the falling edge of tl, clock f
Start counting to 3. When the counter 3 counts n clocks fS, the decoder 4 outputs a sampling pulse SPL.
Output. FF2 samples the received signal e (t) at the rising edge of the pulse SPL and holds the level until the next sampling. This hold output Q becomes the detection signal v (tl).

[Effect]

FIG. 2 is a time chart showing the operation of FIG. 1. The timing at which the sampling pulse SPL is ordered is a certain time Tc after the fall of the received signal e (t), and is set so that this satisfies the following. Since this time Tc is, if the lock frequency fS is increased, the count number n
Therefore, it is possible to reduce the error rate by using a high fS. Moreover, the count number n
The increase in the number of stages of the counter 3 due to the increase in the number of stages of the counter 3 is significantly smaller than that of a shift register.

〔Example〕

FIG. 3 is a configuration diagram showing an embodiment of the present invention, and 31.32
are binary counters of 4 bits each.

The counter 31 counts the clock fS, and the counter 31 counts the clock fS.
Since counter 2 counts the overflow output QD, an 8-bit binary counter 3 is constructed as a whole. Reference numeral 5 denotes a delay differentiator circuit that detects the falling edge of the received signal e (t), and loads initial values into the counters 31 and 32 using the output EDG. The initial value is input A of the counter 31
, B, C, D and the inputs A, B, C, D of the counter 32, a total of 8 bits. 6 is DI for that purpose
P switch (Dual in 1ine packag)
It is an e-type switch) and is composed of eight two-contact type switch circuits, and is 0 when ON and 1 when OFF. In this example, rH=200KHz, fL=210KHzSfS=4
As 0MHz, 10011101 (binary) = 157
(decimal) is set as the initial value.

In this way, after 98 counts of clock fS (n=
98), the outputs QA to QD of counters 31 and 32 are 111.
11111 (binary) = 255 (decimal). Since the decoder 4 uses an 8-person Nantes gate,
At this time, the output SPL switches from 1 to 0. Then, when SPL rises from 0 to 1 at the next count, FF2 is driven and samples the received signal e (t) at that time. FIG. 4 is a time chart showing this.

The count value of n=98 can be obtained from +31 +41 as follows. First, from equation (3), 2.38 p s < T c < 2.5 p s can be found. Substituting equation (4) into the above equation results in 2.38 μs<0.025·n<2.5 us.

The delay time by the counter 3 described above corresponds to the delay time of a 2m stage shift register, where m is the number of counter stages. Therefore, an equivalent digital delay detection circuit can be realized with a simple configuration.

〔Effect of the invention〕

As described above, according to the present invention, since a counter is used as a delay element, a highly accurate digital delay detection circuit can be realized with a simple configuration and at low cost.

[Brief explanation of drawings]

Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is a time chart thereof, Fig. 3 is a block diagram showing an embodiment of the present invention, Fig. 4 is a time chart thereof, and Fig. 5 is a conventional digital delay. FIG. 6 is a configuration diagram showing an example of a detection circuit, and a time chart thereof. In the figure, 2 is a D-type flip-flop, 3 is a counter, and 4 is a D-type flip-flop.
is a decoder. Applicant Fujitsu Ten Ltd. Agent Patent Attorney Aoyagi Hoki 1TlI! IO Basic 1 O book wide map Figure 1 (Enlarged view (1)) Gold body diagram') r+o Retime + Yard Figure 2

Claims (1)

[Claims] F having a mark frequency f_H and a space frequency f_L
The predetermined frequency f_S is activated by one edge of the SK signal.
a decoder (4) that generates a sampling pulse (SPL) when the counter counts n clocks, and a D-type flip-flop that samples the FSK signal with the sampling pulse. (2), and the above count number n
is 1/(2f_H)<n・(1/f_S)<1/(2f_
A digital delay detection circuit characterized in that it is set to satisfy the following relationship: L).