JPH01229518A - Semiconductor integrated circuit by master slice system - Google Patents

Abstract

PURPOSE:To generate an arbitrary timing pulse by only the change of a ROM value and to obtain a stable and highly accurate timing signal by using a decoder as a ROM for a gate array. CONSTITUTION:A timing pulse f2 is generated by a counter 4 with an input signal f1 as an input, a decoder 5 to generate an arbitrary timing with output signal fa of the counter 4 as an input signal, and a JK flip flop 6 with output signals fb and fc of the decoder 5 and the f1 as input signals. In a circuit constructed in such a way, all the output signals change synchronously with the signal f1 therefore, the stable output signal f2 can be obtained. By using the decoder 5 as the ROM for gate array, the ROM of real use capacity can be constructed and the timing signal can be easily changed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to, for example, a timing generation unit that can easily generate arbitrary timing pulses.

[Conventional technology]

FIG. 4 is a circuit diagram of a conventional timing pulse generation circuit, for example, shown in the document "Practical IC Circuit Design Guide" written by Kazuhiro Hara and published by Ohmsha on December 30, 1987. In the figure, (1) is a capacitor, (2) is a resistor, and (3) is a mono-multivibrator.

Next, the operation will be explained. This circuit consists of a capacitor (
1) and the time constant of the resistor (2), the output of the mono multivibrator (3) is used to invert the output signal for a certain period of time according to the above time constant, and the start timing signal for inverting the output pulse is set. An arbitrary timing pulse is generated as an input signal to the mono-multivibrator (3).

[Problem to be solved by the invention]

Conventional timing pulse generation circuits are configured as described above, but cannot output stable timing pulse signals because the time constant changes due to temperature, etc., and depending on the next stage circuit, this instability may occur. There were problems such as malfunctions due to various reasons.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a timing pulse generation circuit that outputs a stable timing pulse signal and can easily change the timing of the output signal. .

[Means to solve the problem]

The timing pulse generation circuit according to the present invention uses a decoder to generate change start and end timing signals of the output pulse signal from the output signal of the counter, and inputs this timing signal to the J and terminals of the JK flip-flop in the next stage. , generate a timing pulse signal. In addition, by configuring the decoder with a ROM for gate arrays,
This allows a ROM configuration with an actual capacity to be used, and allows the timing signal to be easily changed.

[For production]

In this invention, the timing pulse signal is obtained by inputting the output signal of the decoder to the JK flip-flop, and is processed entirely digitally, using analog elements such as capacitors and resistors, and is highly accurate and stable. A timing pulse signal is obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 1 is a circuit diagram of a timing pulse generation circuit for a semiconductor integrated circuit using an asterslice method according to an embodiment of the present invention. In the figure, (4) is a counter that outputs a binary signal according to the frequency of the input signal, (5) is a decoder that outputs a timing signal, and (6) receives the above timing signal as input and outputs a timing pulse signal. J.K.
It's a flip flop.

Next, the operation will be explained.

FIG. 2 is a timing chart of the timing generation circuit configured as described above. The output signal f of the counter (4) which takes the input signal f1' as an input; The output signal fb, fc of the decoder (5) which takes the above fa as an input signal and generates an arbitrary timing; the above fb, fc and fl are taken as input signals. , JK flip-flop (6) generates a timing pulse signal f2.

In all of the circuits configured in this way, the output signals change in synchronization with the 11 signals, so that a stable output signal f2 can be obtained.

Note that in the above-mentioned embodiment, when the power is turned on, the state of the internal circuit is unstable, so normal operation may not be performed. Therefore, by making arrangements as shown in FIG. 3, stable operation can be guaranteed at all times. FIG. 3 is a circuit diagram of another embodiment of the timing generation circuit of the present invention, in which the clock input is a signal inverted by an inverter (7), and the data input is a D flip-flop (8) with the power level. The output signal of the counter (4) and the JK flip-flop are reset input, and the D flip-flop (8
) is supplied with a reset signal to its reset input. That is, by adding the circuit as described above, a stable initial state is realized.

In the embodiment shown in FIG. 3, the counter (4) and the JK flip-flop (6) are configured as a circuit with a reset function, and the D flip-flop (8) to which the sixth order is input as data input is used as the counter (4) and the JK flip-flop. (6) 1ζ
Although I tried to give a reset signal, the counter (4)
The JK flip-flop (6) may be used as a setting circuit, and the counter (4) and the JK flip-flop (6) may be set by the D flip-flop (8) to which the GND potential is input as data input. The same effects as in the above embodiment are achieved.

〔Effect of the invention〕

As described above, according to the present invention, by using a gate array ROM circuit as a decoder, it is possible to generate an arbitrary timing pulse simply by changing the ROM value, and
This has the effect of providing a stable and highly accurate timing signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a timing pulse generation circuit for a semiconductor integrated circuit using a master slice method according to an embodiment of the present invention, and FIG. 2 is a timing chart of the circuit of FIG. 1.
FIG. 3 is a circuit diagram of another embodiment of the timing generation circuit of the present invention, and FIG. 4 is a circuit diagram of a conventional timing pulse generation circuit. In the figure, (4) is a counter, (5) is a decoder, (
6) is a JK flip-flop, (7) is an inverter, (
8) is a D flip-flop. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A counter that outputs a binary signal according to the frequency of an input signal, a decoder that outputs a decoded signal of the output signal of the counter, and a flip-flop that receives the input signal of the counter and the output signal of the decoder and outputs a pulse signal. A semiconductor integrated circuit using a master slice method, characterized by comprising: