JPS63260099A - Multilayer printed interconnection board - Google Patents
Multilayer printed interconnection boardInfo
- Publication number
- JPS63260099A JPS63260099A JP9300987A JP9300987A JPS63260099A JP S63260099 A JPS63260099 A JP S63260099A JP 9300987 A JP9300987 A JP 9300987A JP 9300987 A JP9300987 A JP 9300987A JP S63260099 A JPS63260099 A JP S63260099A
- Authority
- JP
- Japan
- Prior art keywords
- holes
- multilayer printed
- wiring
- signal layer
- layer pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、多層印刷配線板の信号層パターンにより部品
間の配線を行う装置に係り、特に電子計X機の高密度印
刷配線板に好適な多層印刷配線板〔従来の技術〕
従来の多層印刷配線板では配線パターンにおける信号の
遅れを最少限におさえる為に%XおよびY軸方向の信号
層パターンに加えて、それ以外の角度の信号層パターン
を組み合せて配線を行っていた。例えば特開昭58−1
34493号公報忙示される4のがある。しかし、従来
の多層印刷配線板では、スル−ホール径を大きくした場
合に、スルーホールと信号層パターンの間隔に対する配
慮から、必ずしも最短で配線することができなかったO
〔発明が解決しようとする問題点〕
第2図は従来の多層印刷配線板和おいて、X軸に対して
45°方向忙配線を行う場合の信号層パターンの走行状
態を示したものである。同図に示すよ5&c、従来の多
層印刷配線板においてはスルーホール径はfべて同一径
である為にスルーホール径が大きくなった場合、配線用
スルーホールC−り間の配線を行う際、スルーホールと
信号層パターン間の間隔を確保できなくなりパターン4
に示すように信号層パターンを折れ線状にしなければな
らない、これにより、配線を最短で行うことができない
為、信号遅延時間の増加を招(。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a device for wiring between components using a signal layer pattern of a multilayer printed wiring board, and is particularly suitable for high-density printed wiring boards of electronic measuring machines. [Conventional technology] In conventional multilayer printed wiring boards, in order to minimize signal delays in wiring patterns, in addition to signal layer patterns in the X and Y axis directions, signals at other angles are Wiring was done by combining layer patterns. For example, JP-A-58-1
No. 34493 has 4 listed in the publication. However, in conventional multilayer printed wiring boards, when the diameter of the through holes is increased, it is not always possible to wire in the shortest possible length due to considerations for the spacing between the through holes and the signal layer pattern. Problems] FIG. 2 shows the running state of the signal layer pattern in a conventional multilayer printed wiring board in which busy wiring is performed in a direction of 45° with respect to the X axis. As shown in the same figure, in conventional multilayer printed wiring boards, all the through holes have the same diameter, so when the through hole diameter becomes large, when wiring between the wiring through holes C and 2. , it becomes impossible to secure the space between the through hole and the signal layer pattern, pattern 4
As shown in Figure 2, the signal layer pattern must be in the form of a polygonal line.This results in an increase in signal delay time because wiring cannot be done in the shortest possible time.
本発明の目的は、配線を最短で行うようにすることにあ
る。An object of the present invention is to make the wiring as short as possible.
上記目的は、たがいに径の異なる部品接続用スルーホー
ルと配線用スルーホールなXおよびY方向の双方につい
て交互に設け、基本格子上で同一径のスルーホールが隣
り合わないようにすること九より、達成される、
〔作用〕
たがいに径の異なる部品接続用スルーホールと配線用ス
ルーホールをXおよびY方向の双方について交互に設け
ることによって基本格子上で同一径のスルーホールが隣
り合わなくなる。そわによって、XおよびY@忙対して
+45°および−45゜方向の信号層パターンとスルー
ホール間の導体間隔を確保できることから、配線を最短
で行える為に信号の遅延時間を短縮できる。The above purpose is to alternately provide component connection through-holes and wiring through-holes with different diameters in both the X and Y directions, and to prevent through-holes with the same diameter from adjoining each other on the basic grid. [Function] By alternately providing through holes for component connection and through holes for wiring that have different diameters in both the X and Y directions, through holes with the same diameter are no longer adjacent to each other on the basic lattice. By warping, the conductor spacing between the signal layer pattern and the through hole in the +45° and -45° directions with respect to the X and Y directions can be secured, so that the wiring can be done in the shortest possible time, thereby shortening the signal delay time.
以下、本発明の一実施例を第1図により説明する。この
図においては配線用スルーホール1と部品接続用スルー
ホール2を基本格子上で同一径のスルーホールが隣り合
わないように設けている。An embodiment of the present invention will be described below with reference to FIG. In this figure, through-holes 1 for wiring and through-holes 2 for connecting components are provided so that through-holes with the same diameter are not adjacent to each other on a basic grid.
まずスルーホールAから出発し、Y方向に、αだけ配線
する。αの位置は、相隣り合うスルーホール12の中間
位置に設けられる。αからbまでは直線状に配線する。First, starting from through hole A, wire by α in the Y direction. The position α is provided at an intermediate position between adjacent through holes 12. Wire from α to b in a straight line.
bの位置も相隣り合うスルーホールt2の中間位置であ
る。bからはX方向に直線的にBまで配線する。このよ
うに構成された本発明の多層印刷配線板では配線用スル
ーホールA−B間を直線の信号層パターン5で配線して
もスルーホールと信号層パターン間の導体間隔を確保で
きる為に配線長を短(できる。The position b is also an intermediate position between the adjacent through holes t2. Wire from b to B in a straight line in the X direction. In the multilayer printed wiring board of the present invention configured as described above, even if the wiring through holes A and B are wired with a straight signal layer pattern 5, the conductor spacing between the through hole and the signal layer pattern can be secured. Shorten the length (can be done)
本発明によれば、配線長を短縮することによって信号の
遅延時間を短縮できる為、装討を高速化することができ
る。According to the present invention, since the signal delay time can be shortened by shortening the wiring length, the installation speed can be increased.
第1図は本発明による多層印刷配線板のスルーホールの
配置および信号層パターンを示した部分的平面図、第2
図は従来の多層印刷配線板のスルーホールの配置および
信号層パターンを示した部分的平面図である。
1・・・配線用スルーホール、2・・・部品接続用スル
ーホール、3・・・配線用スルーホールA−B間を接続
する信号層パターン、4・・・配線用スルーホールC−
り間を接続する信号層パターン。
名 l 図
名2図FIG. 1 is a partial plan view showing the through-hole arrangement and signal layer pattern of a multilayer printed wiring board according to the present invention;
The figure is a partial plan view showing the arrangement of through holes and the signal layer pattern of a conventional multilayer printed wiring board. 1...Through hole for wiring, 2...Through hole for component connection, 3...Signal layer pattern connecting between through holes A and B for wiring, 4...Through hole for wiring C-
A signal layer pattern that connects between Name l Figure name 2 Figure
Claims (1)
る為の電源層を有する多層印刷配線板において、部品接
続用のスルーホール径と配線用スルーホール径を異なる
径とし、かつXおよびY方向の双方について異なる径の
スルーホールを交互に設け、基本格子上で同一径のスル
ーホールが隣り合わないようにしたことを特徴とする多
層印刷配線板。In a multilayer printed wiring board that has multiple or one signal layer and a power supply layer for supplying power to components, the through-hole diameter for component connection and the through-hole diameter for wiring are different diameters, and A multilayer printed wiring board characterized in that through holes of different diameters are provided alternately on both sides so that through holes of the same diameter are not adjacent to each other on a basic grid.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9300987A JPS63260099A (en) | 1987-04-17 | 1987-04-17 | Multilayer printed interconnection board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9300987A JPS63260099A (en) | 1987-04-17 | 1987-04-17 | Multilayer printed interconnection board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63260099A true JPS63260099A (en) | 1988-10-27 |
JPH0587159B2 JPH0587159B2 (en) | 1993-12-15 |
Family
ID=14070406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9300987A Granted JPS63260099A (en) | 1987-04-17 | 1987-04-17 | Multilayer printed interconnection board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63260099A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012054296A (en) * | 2010-08-31 | 2012-03-15 | Kyocer Slc Technologies Corp | Wiring board and method of manufacturing the same |
-
1987
- 1987-04-17 JP JP9300987A patent/JPS63260099A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012054296A (en) * | 2010-08-31 | 2012-03-15 | Kyocer Slc Technologies Corp | Wiring board and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0587159B2 (en) | 1993-12-15 |
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