JPS63255939A - Linear array - Google Patents

Linear array

Info

Publication number
JPS63255939A
JPS63255939A JP62090324A JP9032487A JPS63255939A JP S63255939 A JPS63255939 A JP S63255939A JP 62090324 A JP62090324 A JP 62090324A JP 9032487 A JP9032487 A JP 9032487A JP S63255939 A JPS63255939 A JP S63255939A
Authority
JP
Japan
Prior art keywords
voltage power
power supply
power source
transistors
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62090324A
Other languages
Japanese (ja)
Inventor
Tadashi Shibata
正 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP62090324A priority Critical patent/JPS63255939A/en
Publication of JPS63255939A publication Critical patent/JPS63255939A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11801Masterslice integrated circuits using bipolar technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To constitute a large scale analog circuit which can be operated by a high voltage power source, by arranging an element for the high voltage power source in, at least, a part of the periphery of a chip. CONSTITUTION:In the outer periphery of a chip 1, a plurality of NPN transistors 4 for a high voltage power source are arranged in the form of a nearly rectangular ring, so as to surround a transistor array 2. An adequate number of the transistors 4 for the high voltage power source are combined to constitute an input-output circuit and the like having a high operating voltage. These transistors 4 for the high voltage power source are formed by a fine working in the similar manner to transistors 3 for a low voltage power source. Thereby, the integration degree of elements for a low voltage power source is increased, and a large scale analog circuit can be constituted, which can be operated by the high voltage power source.

Description

【発明の詳細な説明】 発明の目的 (産業上の利用分野) この発明は半導体集積回路に係り、詳しくはマスクスラ
イス方式のリニアアレイに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit, and more particularly to a mask slicing linear array.

(従来の技術) 従来の基本的なバイポーラプロセスにより作製されるリ
ニアアレイに設けられた低圧電源用トランジスタ30は
、素子耐圧の点を考慮して第10図(a)、(ロ)に示
すように大きく形成されており、例えば3IIX11角
のチップ上に形成できる同トランジスタ30は歩留り等
から考えて200個程度が限界であり、この従来のリニ
アアレイで構成できる回路規模には限界がある。
(Prior Art) A low-voltage power transistor 30 provided in a linear array manufactured by a conventional basic bipolar process is constructed as shown in FIGS. 10(a) and 10(b) in consideration of device breakdown voltage. For example, the number of transistors 30 that can be formed on a 3IIX11 square chip is limited to about 200 in terms of yield, and there is a limit to the circuit scale that can be constructed using this conventional linear array.

(発明が解決しようとする問題点) しかし、システムの小型化、多機能化に伴ってリニアア
レイに要求される機能も増大化する傾向にあり、大規模
アナログ回路を構成できる集積度の高いリニアプレイが
必要となる。このために従来プロセスに代えて微細化プ
ロセスにより内部トランジスタ数を数倍増加させること
が必要になるが、各素子の微細化に伴って素子耐圧が低
下し、微細化プロセスにより作製したリニアアレイを例
えば自動車バッテリーの12V電圧で使用することがで
きないという問題点がある。
(Problem to be solved by the invention) However, as systems become smaller and more multifunctional, the functions required of linear arrays tend to increase. Play is required. For this purpose, it is necessary to increase the number of internal transistors several times by using a miniaturization process instead of the conventional process, but as each element becomes miniaturized, the element withstand voltage decreases, and the linear array fabricated using the miniaturization process For example, there is a problem in that it cannot be used with the 12V voltage of an automobile battery.

この発明は上記問題点を解決するためになされたもので
あって、その目的は低圧電源用素子の集積度を向上して
大規模アナログ回路を構成することができるとともに、
高圧電源で使用可能なリニアアレイを提供することにあ
る。
This invention was made to solve the above problems, and its purpose is to improve the degree of integration of low-voltage power supply elements and to configure large-scale analog circuits.
The objective is to provide a linear array that can be used with a high voltage power supply.

発明の構成 (問題点を解決するための手段) この発明は上記目的を達成するため、チップ上に低圧電
源用素子と高圧電源用素子とを設けたリニアアレイにお
いて、前記高圧電源用素子をチップの周縁部の少なくと
も一部に配置するという構成を採用している。
Structure of the Invention (Means for Solving Problems) In order to achieve the above object, the present invention provides a linear array in which a low voltage power supply element and a high voltage power supply element are provided on a chip. A configuration is adopted in which the device is arranged at least in part on the peripheral edge of the device.

(作用) 従って、高圧電源系の入出力回路部を高圧電源用素子で
構成するとともに、低圧電源系の制御回路等を低圧電源
用素子で構成し、入力出力回路と制御回路等を接続する
ことにより、このリニアアレイを例えば自動車用バッテ
リー等の12V電圧で使用することができる。
(Function) Therefore, the input/output circuit section of the high-voltage power supply system is configured with high-voltage power supply elements, and the control circuit, etc. of the low-voltage power supply system is configured with low-voltage power supply elements, and the input/output circuit and the control circuit, etc. are connected. This allows this linear array to be used with a 12V voltage, for example in a car battery.

(実施例) 以下、この発明を具体化したリニアアレイの一実施例を
図面に基づいて説明する。
(Example) Hereinafter, an example of a linear array embodying the present invention will be described based on the drawings.

第1図に示すように千ツブ1のコア部1aには、第2図
(a)、 (b)に示す低圧電源用NPN)ランジスタ
3を多数配設したトランジスタアレイ2が複数列設され
ている。トランジスタアレイ2の各トランジスタ3は微
細化プロセスにより形成されており、高集積度となって
いる。そして、適数の低圧電源用トランジスタ3を組合
わせることにより例えば制御回路等を構成することがで
きる。
As shown in FIG. 1, a plurality of rows of transistor arrays 2 each having a large number of NPN transistors 3 for low-voltage power supply shown in FIGS. There is. Each transistor 3 of the transistor array 2 is formed by a miniaturization process and has a high degree of integration. For example, a control circuit or the like can be constructed by combining an appropriate number of low-voltage power supply transistors 3.

千ツブ1の外周縁部には第3図(a)、 (b)に示す
ような複数の高圧電源用NPNI−ランジスタ4が、前
記トランジスタアレイ2を囲繞するようにほぼ四角環状
に配設されており、適数の高圧電源用トランジスタ4を
組合わせることにより、使用電圧の高い入出力回路等を
構成することができる。又、これらの高圧電源用トラン
ジスタ4も前記低圧電源用トランジスタ3と同様に微細
加工により形成されている。
A plurality of high-voltage power supply NPNI transistors 4 as shown in FIGS. 3(a) and 3(b) are arranged on the outer periphery of the tube 1 in a substantially rectangular ring shape so as to surround the transistor array 2. By combining an appropriate number of high-voltage power supply transistors 4, it is possible to configure an input/output circuit that uses a high voltage. Further, these high-voltage power supply transistors 4 are also formed by microfabrication similarly to the low-voltage power supply transistor 3.

なお、この実施例においては低圧電源用トランジスタ3
の個数と高圧電源用トランジスタ4の個数との割合を約
4=1に設定しており、これにより集積度の低下を防止
している。
Note that in this embodiment, the low voltage power supply transistor 3
The ratio between the number of high-voltage power supply transistors 4 and the number of high-voltage power supply transistors 4 is set to approximately 4=1, thereby preventing a decrease in the degree of integration.

前記コア部1aと環状に配設された高圧電源用トランジ
スタ4との間の配線トラック領域5は低圧電源用トラン
ジスタ3により構成される各回路間、あるいは前記トラ
ンジスタ3により構成される回路と高圧電源用トランジ
スタ4で構成される入出力回路等との間の配線のための
領域である。
The wiring track area 5 between the core portion 1a and the high-voltage power supply transistors 4 arranged in an annular manner is between each circuit constituted by the low-voltage power supply transistor 3, or between the circuit constituted by the transistor 3 and the high-voltage power supply. This is an area for wiring between the input/output circuit and the like made up of the transistor 4.

外部電橋6はワイヤポンディング用パッドあるいはフリ
ンブチップ用のバンプとして使用される。
The external bridge 6 is used as a wire bonding pad or a bump for a flimb chip.

上記のように構成したリニアアレイにポリシリコン工程
、電極工程、配線工程等を施すことにより第4図に示す
ように例えば自動車バッテリー等の高圧電源8で使用可
能な回路が構成される。
By subjecting the linear array constructed as described above to a polysilicon process, an electrode process, a wiring process, etc., a circuit that can be used in a high-voltage power source 8 such as an automobile battery is constructed as shown in FIG. 4.

降圧回路7及び入力回路9はそれぞれ前記高圧電源用ト
ランジスタ4を適数使用して構成され、降圧回路7は電
源8の12V電圧を5v付近まで降圧させるようになっ
ており、入力回路9はセンサ、スイフチ等の外部入力機
器10から出力される12V電圧の信号SG1を5V電
圧以下の信号SG2に変換して次段の制御回路12に出
力するようになっている。
The step-down circuit 7 and the input circuit 9 are each constructed by using an appropriate number of the high-voltage power supply transistors 4, and the step-down circuit 7 is configured to step down the 12V voltage of the power supply 8 to around 5V. , a signal SG1 of 12V voltage outputted from an external input device 10 such as a switch, etc., is converted into a signal SG2 of 5V voltage or less and output to the control circuit 12 at the next stage.

定電圧回路11及び制御回路12は前記低圧電源用トラ
ンジスタ3を適数使用して構成され、定電圧回路11は
前記降圧回路7により5■付近まで降圧された電圧を精
密な5■電圧に変換して制御回路12の駆動電圧として
出力するようになっており、制御回路12は前記入力回
路9から出力されるSG2に基づいて制御信号SG3を
次段の出力回路13に出力するようになっている。
The constant voltage circuit 11 and the control circuit 12 are constructed by using an appropriate number of the low-voltage power supply transistors 3, and the constant voltage circuit 11 converts the voltage reduced to around 5■ by the step-down circuit 7 into a precise 5■ voltage. The control circuit 12 outputs a control signal SG3 to the next stage output circuit 13 based on the SG2 outputted from the input circuit 9. There is.

又、出力回路13は前記入力回路9と同様に高圧電源用
トランジスタ4を適数使用して構成され、前記制御信号
SG3を12V電圧の駆動信号SG4に変換して電源8
に接続されたコイル等の機器を駆動するための駆動回路
14に出力するようになっている。
Further, the output circuit 13 is constructed by using an appropriate number of high-voltage power supply transistors 4 similarly to the input circuit 9, and converts the control signal SG3 into a drive signal SG4 of 12V voltage to supply the power supply 8.
The output signal is output to a drive circuit 14 for driving equipment such as a coil connected to the drive circuit 14.

さて、この実施例ではチップ1上に微細化プロセスによ
り低圧電源用トランジスタ3及び高圧電源用トランジス
タ4を形成したので、低圧電源用トランジスタ3の集積
度を大幅に向上して大規模アナログ回路を構成すること
ができるとともに、低圧電源用トランジスタ3の微細化
に伴う素子耐圧の低下を高圧電源用トランジスタ4を組
合わせて構成した回路により補償できるので、このリニ
アアレイを例えば12V電圧である自動車バッテリー等
の高圧電源8で使用することができる。
Now, in this embodiment, the low-voltage power supply transistor 3 and the high-voltage power supply transistor 4 are formed on the chip 1 by a miniaturization process, so the degree of integration of the low-voltage power supply transistor 3 is greatly improved to configure a large-scale analog circuit. At the same time, the reduction in element withstand voltage due to the miniaturization of the low-voltage power transistor 3 can be compensated for by the circuit configured by combining the high-voltage power transistor 4, so this linear array can be used for example in a car battery with a voltage of 12V, etc. It can be used with the high voltage power supply 8.

又、この実施例ではチップl中央のコア部1aに多数の
低圧電源用トランジスタ3を設けるとともに、チップ1
の外周縁部に多数の高圧電源用トランジスタ4をほぼ環
状に配設したので、各低圧電源用トランジスタ3間の配
線接続に際して高圧電源用トランジスタ4が邪魔になら
ず、又、高圧電源用トランジスタ4が外部電極6の近傍
に位置しているため、高圧電源用トランジスタ4と外部
入力機器lOあるいはコイル等の駆動回路14との配線
が容易になり、パターン設計を容易に行うことができる
Further, in this embodiment, a large number of low-voltage power supply transistors 3 are provided in the core portion 1a at the center of the chip 1, and
Since a large number of high-voltage power supply transistors 4 are arranged approximately in a ring shape around the outer periphery of the high-voltage power supply transistor 4, the high-voltage power supply transistor 4 does not get in the way when wiring is connected between the low-voltage power supply transistors 3, and the high-voltage power supply transistor 4 Since it is located near the external electrode 6, wiring between the high-voltage power supply transistor 4 and the external input device 1O or the drive circuit 14 such as a coil becomes easy, and pattern design can be easily performed.

なお、前記実施例では高圧電源用トランジスタ4を通数
組合わせて出力回路13を構成したが、第5図に示すよ
うにリニアアレイと外部機器との間で伝達される信号レ
ベルの調整用素子として、高圧電源用トランジスタ4を
1個のみ使用してもよい。
In the above embodiment, the output circuit 13 was constructed by combining a number of high-voltage power supply transistors 4, but as shown in FIG. 5, an element for adjusting the signal level transmitted between the linear array and external equipment Therefore, only one high-voltage power supply transistor 4 may be used.

又、第6図に示すように、それぞれ高圧電源で動作する
オペアンプ15、バイアス回路16等からなるリニア回
路ブロック17を構成する場合、複数個の高圧電源用ト
ランジスタ4を近接して配設しであるので、パターン設
計を容易に行うことができる。
Further, as shown in FIG. 6, when configuring a linear circuit block 17 consisting of an operational amplifier 15, a bias circuit 16, etc. each operating on a high-voltage power supply, a plurality of high-voltage power supply transistors 4 may be disposed close to each other. Therefore, pattern design can be easily performed.

さらに、第7図に示すように静電破壊保護回路18を構
成する一対のダイオード19として、前記高圧電源用ト
ランジスタ4を使用することもできる。この場合にはベ
ースB・エミッタ8間あるいはベースB・コレクタC間
のPN接合を利用している。この例における抵抗20は
ポリシリコン抵抗である。
Furthermore, as shown in FIG. 7, the high-voltage power supply transistor 4 can also be used as a pair of diodes 19 constituting the electrostatic discharge protection circuit 18. In this case, a PN junction between base B and emitter 8 or between base B and collector C is used. Resistor 20 in this example is a polysilicon resistor.

又、前記実施例では高圧電源用トランジスタ4をチップ
lの外周縁部にほぼ環状に配設したが、例えば第8図に
示すようにチップ1の一側縁にのみ設けたり、第9図に
示すように外周縁部の二側縁に設けたりしてもよい。
Further, in the above embodiment, the high-voltage power supply transistor 4 is arranged approximately in an annular shape around the outer peripheral edge of the chip l, but for example, as shown in FIG. As shown, it may be provided on two side edges of the outer peripheral edge.

発明の効果 以上詳述したように、この発明は低圧電源用素子の集積
度を向上して大規模アナログ回路を構成することができ
るとともに、高圧電源でイ専用することができる優れた
効果がある。
Effects of the Invention As detailed above, the present invention has the excellent effect that it is possible to configure large-scale analog circuits by improving the degree of integration of low-voltage power supply elements, and it can also be used exclusively for high-voltage power supplies. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明を具体化したリニアアレイの一実施例
を示す平面図、第2図(a)は低圧電源用トランジスタ
を示す平面図、第2図(ト))はその断面図、第3図(
a)は高圧電源用トランジスタを示す平面図、第3図(
b)はその断面図、第4図はリニアプレイで構成される
一般的な回路のブロック図、第5図は高圧電源用トラン
ジスタを信号調整用素子として使用した状態を示す電気
回路図、第6図は高圧電源用トランジスタにより構成し
たリニア回路ブロックを示す電気回路図、第7図は高圧
電源用トランジスタにより構成した静電破壊保護回路図
、第8.9図はそれぞれリニアアレイの別個を示す平面
図、第10図(a)は従来の低圧電源用トランジスタを
示す平面図、第10図(b)はその断面図である。 図において、1はチップ、3は低圧電源用トランジスタ
、4は高圧電源用トランジスタである。 特許出願人     日本電装 株式会社代 理 人 
    弁理士 恩1)博宣第1[ 第2図(a)  第8図(a)
FIG. 1 is a plan view showing an embodiment of a linear array embodying the present invention, FIG. 2(a) is a plan view showing a low-voltage power supply transistor, FIG. Figure 3 (
a) is a plan view showing a transistor for high-voltage power supply;
b) is its cross-sectional view, Fig. 4 is a block diagram of a general circuit configured with a linear play, Fig. 5 is an electric circuit diagram showing a state in which a high-voltage power supply transistor is used as a signal adjustment element, and Fig. 6 The figure is an electric circuit diagram showing a linear circuit block composed of high-voltage power supply transistors, Figure 7 is a diagram of an electrostatic discharge protection circuit composed of high-voltage power supply transistors, and Figures 8 and 9 are plan views showing separate linear arrays. 10(a) is a plan view showing a conventional low-voltage power supply transistor, and FIG. 10(b) is a sectional view thereof. In the figure, 1 is a chip, 3 is a low-voltage power supply transistor, and 4 is a high-voltage power supply transistor. Patent applicant Nippondenso Co., Ltd. Agent
Patent Attorney On 1) Hironobu 1 [Figure 2 (a) Figure 8 (a)

Claims (1)

【特許請求の範囲】 1 チップ上に低圧電源用素子と高圧電源用素子とを設
けたリニアアレイにおいて、 前記高圧電源用素子をチップの周縁部の少なくとも一部
に配置したことを特徴とするリニアアレイ。 2 前記高圧電源用素子は低圧電源用素子を囲繞するよ
うにチップの周縁部にほぼ環状に配置されている特許請
求の範囲第1項に記載のリニアアレイ。
[Claims] 1. A linear array in which a low-voltage power supply element and a high-voltage power supply element are provided on a chip, characterized in that the high-voltage power supply element is disposed on at least a part of the periphery of the chip. array. 2. The linear array according to claim 1, wherein the high-voltage power supply elements are arranged substantially annularly around the periphery of the chip so as to surround the low-voltage power supply elements.
JP62090324A 1987-04-13 1987-04-13 Linear array Pending JPS63255939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62090324A JPS63255939A (en) 1987-04-13 1987-04-13 Linear array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62090324A JPS63255939A (en) 1987-04-13 1987-04-13 Linear array

Publications (1)

Publication Number Publication Date
JPS63255939A true JPS63255939A (en) 1988-10-24

Family

ID=13995341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62090324A Pending JPS63255939A (en) 1987-04-13 1987-04-13 Linear array

Country Status (1)

Country Link
JP (1) JPS63255939A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283610A (en) * 2008-05-21 2009-12-03 Elpida Memory Inc Esd protective circuit
US8025744B2 (en) 2007-03-16 2011-09-27 Shin-Etsu Chemical Co., Ltd. Rare earth permanent magnet and its preparation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122262A (en) * 1985-11-22 1987-06-03 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122262A (en) * 1985-11-22 1987-06-03 Hitachi Ltd Semiconductor integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8025744B2 (en) 2007-03-16 2011-09-27 Shin-Etsu Chemical Co., Ltd. Rare earth permanent magnet and its preparation
JP2009283610A (en) * 2008-05-21 2009-12-03 Elpida Memory Inc Esd protective circuit

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