JPS62122262A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS62122262A JPS62122262A JP60261165A JP26116585A JPS62122262A JP S62122262 A JPS62122262 A JP S62122262A JP 60261165 A JP60261165 A JP 60261165A JP 26116585 A JP26116585 A JP 26116585A JP S62122262 A JPS62122262 A JP S62122262A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit
- circuit device
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 230000015556 catabolic process Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
この発明は、半導体集積回路装置技術さらには多数の論
理回路が高密度に集積形成されるＬＳＩ（大規模半導体
集積回路装置）に適用して特に有効な技術に関するもの
で、例えば多数のＣＭＯＳ論理回路が高密度に集積形成
される半導体集積回路装置に利用して有効な技術に関す
るものである。[Detailed Description of the Invention] [Technical Field] The present invention is particularly effective when applied to semiconductor integrated circuit device technology and to LSI (Large-Scale Semiconductor Integrated Circuit Device) in which a large number of logic circuits are integrated at high density. The present invention relates to technology, and is effective for use in semiconductor integrated circuit devices in which a large number of CMOS logic circuits are integrated at high density, for example.
例えば、日経マグロウヒル社刊行「日経エレクトロニク
ス １９８２年６月２１日号１１１１〜２３０頁に記載
のように、半導体集積回路装置では、その動作速度、集
積度、および消費電力の３項目の特性が非常に重要であ
る。このために、半導体集積回路装置内に集積形成され
る回路素子のサイズを微細加工によって小型化すること
が行われてきた。For example, as described in "Nikkei Electronics, June 21, 1982 issue, pages 1111-230," published by Nikkei McGraw-Hill, semiconductor integrated circuit devices have three characteristics that are extremely important: operating speed, degree of integration, and power consumption. This is important. For this reason, efforts have been made to reduce the size of circuit elements integrated within a semiconductor integrated circuit device by microfabrication.
例えば、多数のＣＭＯＳ論理回路が高密度に集積形成さ
れた半導体集積回路装置では、そこに形成される能動素
子すなわちＣＭＯＳトランジスタのゲート長などの素子
サイズを小さくすることが上記３項目の特性を改善する
上で非常に有効であるとされている。For example, in a semiconductor integrated circuit device in which a large number of CMOS logic circuits are densely integrated, the characteristics of the above three items can be improved by reducing the element size such as the gate length of the active element formed there, that is, the CMOS transistor. It is said to be very effective in doing so.
しかしながら、素子サイズを小さくして行くと、その素
子の耐圧が低くなって、他の半導体集積回路装置との互
換性を有する電源電圧では安全に動作させることが困難
になってくる、という問題点を生じるようになることが
本発明者らによって明らかとされた。However, as the element size decreases, the withstand voltage of the element decreases, making it difficult to operate safely at a power supply voltage that is compatible with other semiconductor integrated circuit devices. The present inventors have clarified that this occurs.
この発明の目的は、半導体集積回路装置の動作速度、集
積度、および消費電力の３項目の特性の改善を、他の半
導体集積回路装置との互換性を有する電源電圧でも安全
に動作させられる条件を保ちつつ、達成できるようにし
た半導体集積回路装置技術を提供することにある。The purpose of this invention is to improve the three characteristics of a semiconductor integrated circuit device: operating speed, degree of integration, and power consumption, under conditions that allow it to operate safely even at a power supply voltage that is compatible with other semiconductor integrated circuit devices. It is an object of the present invention to provide a semiconductor integrated circuit device technology that can achieve this while maintaining the following.
この発明の前記ならびにそのほかの目的と新規な特徴に
ついては、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものを簡単
に説明すれば、下記のとおりである。A brief description of typical inventions disclosed in this application is as follows.
すなわち、半導体集積回路装置の半導体基板に２つの集
積回路部を互いに電気的に分離した状態で形成するとと
もに、各回路部の動作電源電圧を互いに異ならせて、高
い方の電源電圧で動作させられる回路部には、サイズは
大きいが耐圧の高い回路素子を形成する一方、低い方の
電源電圧で動作させられる回路部には、耐圧は低いが小
サイズに微細加工された回路素子を形成する構成によシ
、その半導体集積回路装置の動作速度、集積度、および
消費電力の３項目の特性の改善を、他の半導体集積回路
装置との互換性を有する電源電圧でも安全に動作させら
れる条件を保ちつつ、達成できるようにする、という目
的を達成するものである。That is, two integrated circuit sections are formed on a semiconductor substrate of a semiconductor integrated circuit device in a state where they are electrically separated from each other, and the operating power supply voltages of each circuit section are made different from each other so that the circuit sections are operated at the higher power supply voltage. In the circuit section, a circuit element that is large in size but has a high withstand voltage is formed, while in a circuit section that can be operated at a lower power supply voltage, a circuit element that is microfabricated into a small size and has a low withstand voltage is formed. In order to improve the three characteristics of the semiconductor integrated circuit device: operating speed, degree of integration, and power consumption, we will also develop conditions that allow it to operate safely at a power supply voltage that is compatible with other semiconductor integrated circuit devices. The goal is to maintain and achieve the goals.
以下、この発明の代表的な実施例を図面を参照しながら
説明する。Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.
なお、図面において同一符号は同一あるいは相当部分を
示す。In the drawings, the same reference numerals indicate the same or corresponding parts.
第１図および第２図はこの発明による半導体集積回路装
置の一実施例を示す。FIGS. 1 and 2 show an embodiment of a semiconductor integrated circuit device according to the present invention.
同図に示す半導体集積回路装置１００は、多数のＣＭＯ
Ｓ論理回路が高密度に集積形成されたＬＳＩであって、
その半導体集積回路装置の半導体基板には、第１図およ
び第２図に示すように、２つの集積回路部１，２が互い
に電気的に分離された状態で形成されている。これとと
もに、各回路部１，２の動作電源電圧ＶＣＣとＶｄｄが
互いに異ならせられている。A semiconductor integrated circuit device 100 shown in the figure includes a large number of CMOs.
An LSI in which S logic circuits are densely integrated,
As shown in FIGS. 1 and 2, two integrated circuit sections 1 and 2 are formed on a semiconductor substrate of the semiconductor integrated circuit device in a state where they are electrically isolated from each other. Along with this, the operating power supply voltages VCC and Vdd of each circuit section 1 and 2 are made different from each other.
各回路部１，２の電気的分離は、第２図に示すように、
ｐ−型シリコン半導体基板１０とｐ型分離拡散層１２と
によってｎ−型エピタキシャル層１１を取り囲む構成に
よって行われている。この場合、高い方の電源電圧Ｖｃ
ｃ（約５Ｖ）で動作させられる回路部２には、サイズは
比較的大きいが耐圧の高いＣＭＯＳトランジスタＭｌ
、Ｍ２が形成されている。一方、低い方の電源電圧■ｄ
ｄ（ｖｄｄ（Ｖｃｃ）で動作させられる回路部１には、
耐圧は低いが小サイズに微細加工されたＣＭＯＳトラン
ジスタＭ３．Ｍ４が高密度に形成されている。The electrical separation of each circuit section 1 and 2 is as shown in FIG.
This is achieved by a structure in which an n-type epitaxial layer 11 is surrounded by a p-type silicon semiconductor substrate 10 and a p-type isolation diffusion layer 12. In this case, the higher power supply voltage Vc
The circuit section 2, which is operated at voltage c (approximately 5 V), includes a CMOS transistor Ml that is relatively large in size but has a high breakdown voltage.
, M2 are formed. On the other hand, the lower power supply voltage ■d
The circuit section 1 operated at d(vdd(Vcc)) includes:
CMOS transistor M3. has a low breakdown voltage but is microfabricated into a small size. M4 is formed with high density.
なお、第２図において、ｐチャンネルＭＯＳトランジス
タＭｌ、Ｍ３はそれぞれ、ｎ−型エピタキシャル層１１
中に部分拡散されたｐ十研ソース・ドレイン拡散層１３
、基板接続用のｎ十型拡散層１４、およびゲート電極１
５などによって形成されている。また、ｎチャンネルＭ
Ｏ８）ランジスタＭ２．Ｍ４はそれぞれ、ｐ型ウェル拡
散層１６中に部分拡散されたｎ十型ソース・ドレイン拡
散層１７、基板接続用のｐ十型拡散層１８、およびゲー
ト電極１５などによって形成されている。そのほか、１
９はアルミニウムなどによる電極、２０は表面酸化膜を
それぞれ示す。In addition, in FIG. 2, p-channel MOS transistors M1 and M3 each have an n-type epitaxial layer 11
p-juken source/drain diffusion layer 13 partially diffused inside
, an n-type diffusion layer 14 for substrate connection, and a gate electrode 1
5, etc. Also, n channel M
O8) Transistor M2. Each M4 is formed by an n+ type source/drain diffusion layer 17 partially diffused into the p type well diffusion layer 16, a p+ type diffusion layer 18 for substrate connection, a gate electrode 15, and the like. In addition, 1
Reference numeral 9 indicates an electrode made of aluminum or the like, and reference numeral 20 indicates a surface oxide film.
また、この実施例では、第１図に示すよｐに、高い方の
電源電圧ＶＣＣで動作させられる回路部２によって半導
体集積回路装置１００の周辺回路部が形成される一方、
低い方の電源電圧Ｖｄｄで動作させられる回路部１によ
って半導体集積回路装置１００の内部回路部が形成され
ている。Further, in this embodiment, as shown in FIG. 1, the peripheral circuit section of the semiconductor integrated circuit device 100 is formed by the circuit section 2 operated at the higher power supply voltage VCC, while
The internal circuit section of the semiconductor integrated circuit device 100 is formed by the circuit section 1 operated at the lower power supply voltage Vdd.
さらに、第１図に示すように、上記２つの回路部１，２
の間には、信号のレベル変換を行うインターフェイス部
３が形成されている。このインターフェイス部３は周辺
回路部２側のＭＯＳ）ランジスタＭｌ、Ｍ２（第２図）
を用いて構成され、高電源電圧ＶＣＣ近くまで振幅する
論理信号と低電圧Ｖｄｄ以下で振幅する論理信号との間
のレベル変換動作を行う。Furthermore, as shown in FIG.
An interface section 3 for converting signal levels is formed between them. This interface section 3 is a MOS transistor on the peripheral circuit section 2 side (Fig. 2).
It performs a level conversion operation between a logic signal that swings close to the high power supply voltage VCC and a logic signal that swings below the low voltage Vdd.
以上のようにして、内部回路部１の素子を高度に微細化
することにより、その半導体集積回路装ｆｉｌｌｌｏＯ
の全体的な集積密度が向上させられるとともに、その微
細化によって動作速度も向上させられるようになる。さ
らに、内部回路部１の動作電源電圧■ｄｄだけを分離し
て低く設定できるので、他の半導体集積回路装置との互
換性を保ちつつ、その消費電力の大幅な低減化が可能に
なる。As described above, by highly miniaturizing the elements of the internal circuit section 1, the semiconductor integrated circuit device filloO
As well as increasing the overall integration density of the device, its miniaturization also increases the operating speed. Furthermore, since only the operating power supply voltage dd of the internal circuit section 1 can be isolated and set low, it is possible to significantly reduce the power consumption while maintaining compatibility with other semiconductor integrated circuit devices.
（１）半導体集積回路装置の半導体基板に２つの集積回
路部を互いに電気的に分離した状態で形成するとともに
、各回路部の動作電源電圧を互いに異ならせて、高い方
の電源電圧で動作させられる回路部には、サイズは大き
いが耐圧の高い回路素子を形成する一方、低い方の電源
電圧で動作させられる回路部には、耐圧は低いが小サイ
ズに微細加工された回路素子を形成する構成により、そ
の半導体集積回路装置の動作速度、集積度、および消費
電力の３項目の特性の改善を、他の半導体集積回路装置
との互換性を有する電源電圧でも安全に動作させられる
条件を保ちつつ、達成できるようになる、という効果が
得られる。(1) Two integrated circuit parts are formed on a semiconductor substrate of a semiconductor integrated circuit device in a state where they are electrically separated from each other, and the operating power supply voltages of each circuit part are made to be different from each other, so that the circuit parts are operated at the higher power supply voltage. In the circuit section that is operated by a lower power supply voltage, we form a circuit element that is large in size but has a high withstand voltage, while in the circuit section that is operated at a lower power supply voltage, we form a circuit element that has a low withstand voltage but is microfabricated into a small size. The configuration improves the three characteristics of the semiconductor integrated circuit device: operating speed, degree of integration, and power consumption, while maintaining conditions that allow it to operate safely even at a power supply voltage that is compatible with other semiconductor integrated circuit devices. The effect is that you will be able to achieve your goals while also achieving your goal.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、この発明は上記実施 例に限定さ
れるものではなく、その要旨を逸脱しない範囲で種々変
更可能であることはいうまでもない。例えば、上記ＣＭ
ＯＳ論理回路は、ＣＭＯＳトランジスタとバイポーラ・
トランジスタとが論理回路内にて複合化されたＢｉ−０
ＭＯ８型の論理回路あってもよい。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the above CM
The OS logic circuit uses CMOS transistors and bipolar
Bi-0 that is combined with a transistor in a logic circuit
An MO8 type logic circuit may also be provided.
以上、本発明者によってなされた発明をその背景となっ
た利用分野である論理用半導体集積回路装置の技術に適
用した場合について説明したが、それに限定されるもの
ではなく、例えばバイポーラ・トランジスタによるリニ
ア回路とＣＭＯＳによる論理回路とが共存して形成され
るアナログ／デジタル型半導体集積回路装置の技術など
にも適用できる。The above description has been made of the case where the invention made by the present inventor is applied to the technology of logic semiconductor integrated circuit devices, which is the background field of application, but the invention is not limited thereto. The present invention can also be applied to technology for analog/digital semiconductor integrated circuit devices formed by coexisting circuits and CMOS logic circuits.
第１図はこの発明による半導体集積回路装置の全体的な
構成の一実施例を示す図、
第２図は第１図に示した半導体集積回路装置の要部にお
ける素子構造を示す断面図である。
１・・・高度に微細化されて低電源電圧で動作させられ
る低耐圧の回路部、２・・・比較的大サイズに形成され
て高電源電圧で動作させられる高耐圧の回路部、３・・
・半導体集積回路装置内のインターフェイス部、１００
・・・半導体集積回路装置、Ｍｌ、Ｍ３・・・回路素子
（ｐチャンネルＭＯＳトランジスタ）、Ｍ２．Ｍ４・・
・回路素子（ｎチャンネルＭＯＳトランジスタ）。FIG. 1 is a diagram showing an embodiment of the overall configuration of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a cross-sectional view showing the element structure of the main part of the semiconductor integrated circuit device shown in FIG. 1. . 1... A low breakdown voltage circuit section that is highly miniaturized and can be operated at a low power supply voltage, 2... A high breakdown voltage circuit section that is formed in a relatively large size and operated at a high supply voltage, 3.・
・Interface part in semiconductor integrated circuit device, 100
. . . Semiconductor integrated circuit device, Ml, M3 . . . Circuit element (p channel MOS transistor), M2. M4...
-Circuit element (n-channel MOS transistor).
Claims (1)
体集積回路装置であって、この半導体集積回路装置の半
導体基板に２つの集積回路部が互いに電気的に分離され
た状態で形成されるとともに、各回路部の動作電源電圧
が互いに異ならせられ、高い方の電源電圧で動作させら
れる回路部には、サイズは大きいが耐圧の高い回路素子
が形成される一方、低い方の電源電圧で動作させられる
回路部には、耐圧は低いが小サイズに微細加工された回
路素子が高密度に形成されていることを特徴とする半導
体集積回路装置。 ２、高い方の電源電圧で動作させられる回路部によって
半導体集積回路装置の周辺回路部が形成される一方、低
い方の電源電圧で動作させられる回路部によって半導体
集積回路装置の内部回路部が形成されていることを特徴
とする特許請求の範囲第１項記載の半導体集積回路装置
。 ３、上記２つの回路部の間に信号のレベル変換を行うイ
ンターフェイス部が形成されていることを特徴とする特
許請求の範囲第１項または第２項記載の半導体集積回路
装置。 ４、上記低い方の電源電圧で動作させられる回路部にＣ
ＭＯＳ論理回路が形成されていることを特徴とする特許
請求の範囲第１項から第３項までのいずれかに記載の半
導体集積回路装置。[Scope of Claims] 1. A semiconductor integrated circuit device in which a large number of logic circuits are densely integrated, and two integrated circuit parts are electrically separated from each other on a semiconductor substrate of the semiconductor integrated circuit device. At the same time, the operating power supply voltages of each circuit section are made to be different from each other, and a circuit element that is large in size but has a high breakdown voltage is formed in the circuit section that is operated at a higher power supply voltage. A semiconductor integrated circuit device characterized in that, in a circuit section operated at a lower power supply voltage, circuit elements having a low breakdown voltage but microfabricated into small sizes are formed at high density. 2. The peripheral circuit section of the semiconductor integrated circuit device is formed by the circuit section operated at the higher power supply voltage, while the internal circuit section of the semiconductor integrated circuit device is formed by the circuit section operated at the lower power supply voltage. A semiconductor integrated circuit device according to claim 1, characterized in that: 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein an interface section for performing signal level conversion is formed between the two circuit sections. 4.C in the circuit section that is operated with the lower power supply voltage mentioned above.
A semiconductor integrated circuit device according to any one of claims 1 to 3, characterized in that a MOS logic circuit is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60261165A JPS62122262A (en) | 1985-11-22 | 1985-11-22 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60261165A JPS62122262A (en) | 1985-11-22 | 1985-11-22 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62122262A true JPS62122262A (en) | 1987-06-03 |
Family
ID=17358018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60261165A Pending JPS62122262A (en) | 1985-11-22 | 1985-11-22 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62122262A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255939A (en) * | 1987-04-13 | 1988-10-24 | Nippon Denso Co Ltd | Linear array |
| JPS6432647A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Ltd | Semiconductor integrated circuit device |
| EP0545604A2 (en) * | 1991-11-29 | 1993-06-09 | Fuji Electric Co. Ltd. | High-withstand voltage integrated circuit |
| US5517049A (en) * | 1994-09-30 | 1996-05-14 | Vlsi Technology, Inc. | CMOS output buffer with enhanced ESD resistance |
-
1985
- 1985-11-22 JP JP60261165A patent/JPS62122262A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255939A (en) * | 1987-04-13 | 1988-10-24 | Nippon Denso Co Ltd | Linear array |
| JPS6432647A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Ltd | Semiconductor integrated circuit device |
| EP0545604A2 (en) * | 1991-11-29 | 1993-06-09 | Fuji Electric Co. Ltd. | High-withstand voltage integrated circuit |
| EP0545604A3 (en) * | 1991-11-29 | 1995-11-22 | Fuji Electric Co. Ltd. | High-withstand voltage integrated circuit |
| US5517049A (en) * | 1994-09-30 | 1996-05-14 | Vlsi Technology, Inc. | CMOS output buffer with enhanced ESD resistance |
| US5618740A (en) * | 1994-09-30 | 1997-04-08 | Vlsi Technology, Inc. | Method of making CMOS output buffer with enhanced ESD resistance |
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