JPH0691193B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a structure of a semiconductor device, and more particularly to a parasitic transistor generation prevention measure in a semiconductor device for driving a motor using a load such as a coil.

[Prior art]

An example of a semiconductor device for driving a motor using an inductance (L load) such as a coil is OA issued by Hitachi, Ltd.
(Office Automation), FA (Factory Automation) Equipment Control Transistor Catalog (1985
(Published in February, 2002), and the contents are as shown in the circuit diagram in FIG.

The semiconductor device IC for driving a motor shown in FIG. 3 has three Hall elements for detecting the rotational positions of the motor coils L ₁ , L ₂ and L _3.
H _1, H _2, H ₃ and, this three Hall elements H _1, H _2, three Hall receiving an output from the H ₃ amplifier A _1, A _2, A _3, the Hall amplifier A _1, A matrix circuit (MATRIX CIRCUIT) B having six outputs A ₂ and A ₃ as inputs, and three driver circuits C ₁ , C ₂ and C ₃ operated by the outputs of the matrix circuit B,
It includes motor coils L ₁ , L ₂ and L ₃ driven by respective outputs of driver circuits C ₁ , C ₂ and C ₃ . Matrix circuit B
The output of the matrix circuit B is predetermined by the combination of the signals input from the Hall amplifiers A ₁ , A ₂ , and A ₃ , and the output of the matrix circuit B energizes the motor coils L ₁ , L ₂ , and L ₃ . The direction of current flow is controlled. The output of the matrix circuit B is input to the base electrodes of the control transistors Q ₁ and Q ₂ of the driver circuit C ₁ as shown in the figure, and the output signals of the control transistors Q ₁ and Q ₂ are motor coils L ₁ Are input to the respective base electrodes of the power transistors Q ₃ and Q ₄ as an output stage circuit for driving. In addition, D ₁ and D ₂ are diodes for preventing destruction of the transistors Q ₃ and Q ₄ , and R ₁ is a resistance. Further, the driver circuits C ₁ and C ₂ and C ₃ have the same circuit configuration and therefore are omitted.

The driver circuit is a PNP transistor Q as shown in the figure.
₁ and NPN transistors Q _{2 to} Q _4, and the transistors Q ₃ and Q ₄ are power transistors.

Matrix circuit outputs U, V, W during motor drive
_Two of the power transistors in the respective driver circuits C ₁ , C ₂ , and C ₃ are turned on or off depending on the level. For example, if W>V> U at a certain point of time, Q ₃ in the driver circuit C ₁ and the transistor in the driver circuit C ₃ are connected to each other in the driver circuit C ₁ .
The transistor corresponding to Q ₄ turns on, and motor coils L ₁ and L ₃
A current I ₁ will flow as shown in FIG.

[Problems to be solved by the invention]

In the motor drive circuit, the rotation of the motor is controlled by changing the directions of the currents supplied to the motor coils L ₁ , L ₂ and L ₃ in six ways. Therefore, a back electromotive force is generated in the motor coils (L ₁ , L ₂ , L ₃ ) acting as the L load due to the change in the direction of the energized current.

For example, reverse power is generated due to the inductance component of the motor coil L ₁ , and the output pin p ₁ momentarily becomes below the ground potential. On the other hand, since the collector electrode of the control transistor Q ₂ has a potential near the power supply potential, when the control transistor Q ₂ and the output transistor Q ₄ are placed close to each other, as shown by the dotted line in the figure. The parasitic transistor Qx becomes conductive and malfunction occurs.

FIG. 4 is a device sectional view showing the cause of generation of the parasitic transistor Qx. Parasitic transistor Qx in the figure consists of two n-type collector region 2a of the NPN transistor Q _2, Q _4, and 2b, a p-type semiconductor substrate 1 by. Generation of the parasitic transistor Qx occurs as follows.
If the current I ₁ shown in FIG. 3 is phase-switched like the current I ₂ at the next time point, a counter electromotive force is generated in the load L ₁ and the output pin
When the potential of p ₁ momentarily drops to the ground potential (GND or OV), O
Similarly, the collector region 2b of the transistor Q _{4 in} the FF state is at the ground potential or lower. On the other hand, the p-type semiconductor substrate 1 has the GND potential, and the collector region 2a of the transistor Q _{2 in} the OFF state has a potential near the power supply potential (V _CC ). Therefore, a parasitic transistor Qx having the collector region 2a as the collector, the p-type substrate 1 as the base, and the collector region 2b as the emitter is generated. The parasitic transistor Qx turns on when the difference between the potential of the p-type substrate 1 and the potential of the collector region 2b becomes about 0.7 V or more.
As means for preventing the generation of such a parasitic npn transistor Qx, the inventors of the present application 1) an island of V _CC (island of resistance),
2) L-pnp transistor whose emitter is connected to V _CC , 3)
Elements such as an Lpnpn transistor whose emitter is connected to V _CC and whose collector is connected to its base have been arranged as far as possible from the epitaxial layer (collector region 2b) having a negative potential. Therefore, the wiring distance of the aluminum (Al) wiring becomes long, and the layout design becomes difficult.

The present invention has been made in order to solve the above problems, and an object of the present invention is to prevent a parasitic transistor from operating due to a momentary potential drop in a semiconductor device that drives an L load. Another object is to provide a structure that can prevent the wiring distance of the Al wiring and shorten the wiring distance.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Of the inventions disclosed in the present application, the outline of a typical one will be briefly described as follows.

That is, in a semiconductor device that drives an L load, a floating semiconductor island region is interposed between a semiconductor island region having a high potential and a semiconductor island region that may have a negative potential on the output side. It is a thing.

[Action]

According to the above-described means, the base width WB of the lateral parasitic npn transistor Qx is widened by the floating island region between the high potential island region and the potential negative island region. The current amplification factor h _FE can be reduced to achieve the above object.

〔Example〕

FIG. 1 shows an embodiment of the present invention and is a partial vertical cross-sectional view of a motor driving power IC for driving an inductance L load.

Reference numeral 1 is a p-Si substrate (substrate) 2a, 2b and 2c, which are epitaxial n-Si layers, which are separated by an isolation p ⁺ layer 3 into island regions of an epitaxial semiconductor. this house,
The high-potential epitaxial layer (for example, the island region 2a having the V _CC potential) in which the npn transistor Q ₂ is formed and the output npn
A transistor Q ₄ is formed, and a potential-independent floating epitaxial layer (island region) 2c is interposed as a buffer between the transistor Q ₄ and the epitaxial layer 2b which may be at a negative potential due to the back electromotive force of the L load.

FIG. 2 is a plan view schematically showing an entire IC chip having the motor drive power transistor shown in FIG.
In the figure, the hatched area is the floating epitaxial region, and
It is provided between Q ₃ and Q ₄ (including other power transistors) and control transistors Q ₁ and Q ₂ (including other control transistors) from one side Y of the chip to a side Z parallel to the side Y. . With such a structure, the parasitic current can be suppressed even when the output pin p ₁ has a negative potential and the parasitic npn transistor is turned on.

That is, as shown in FIG. 1, the base width of the parasitic npn transistor Qx (W
B) is effectively wide and effective parasitic npn transistor
It can reduce h _FE of Qx and reduce parasitic current. In addition, since the element connected to the output transistor (power transistor) can be arranged in the vicinity of the power transistor as the element arrangement, the wiring distance of the Al wiring becomes short.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

〔The invention's effect〕

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to reduce h _{FE of the} parasitic npn transistor, reduce the parasitic current, and eliminate the Al wiring.

[Brief description of drawings]

FIG. 1 is a partial sectional view of a power IC showing an embodiment of the present invention. FIG. 2 is a plan view of the same. FIG. 3 is a circuit diagram of a conventional power IC. FIG. 4 is a partial sectional view of a conventional power IC. 1 ... p ^- type Si substrate (substrate), 2a, 2b ... n ^- type epitaxial layer (island region), 2c ... floating.
Epitaxial layer (island region), 3 ... Isolation p layer.

(72) Kunio Seki, Inventor Kunio Seki 111 No. Nishiyokote-cho, Takasaki City, Gunma Hitachi Takasaki Plant (56) References JP-A-58-186947 (JP, A) JP-A-60-57950 ( JP, A)

Claims (1)

[Claims] 1. A first driving NPN transistor having a collector connected to an output terminal to drive an inductance load,
A second driving NPN transistor having an emitter connected to the output terminal and driving an inductance load;
To control the base current of the driving NPN transistor
Control PNP transistor and a second control NPN transistor for controlling the base current of the second driving NPN transistor, wherein each transistor is formed on one main surface of the first conductivity type semiconductor substrate. A semiconductor device forming an inductance load drive circuit in which an isolation region made of a diffusion layer of the same first conductivity type as that of the substrate is provided between these transistors to separate the elements, On the main surface of the substrate between the second conductivity type collector region of the second driving transistor and the second conductivity type collector region of the second control transistor, an isolation layer of the first conductivity type is formed. It is characterized in that a second conductivity type semiconductor region which is surrounded by the region and this isolation region and which is electrically floating is provided. The semiconductor device according to.