JPS63254535A - Interruption circuit - Google Patents
Interruption circuitInfo
- Publication number
- JPS63254535A JPS63254535A JP62088100A JP8810087A JPS63254535A JP S63254535 A JPS63254535 A JP S63254535A JP 62088100 A JP62088100 A JP 62088100A JP 8810087 A JP8810087 A JP 8810087A JP S63254535 A JPS63254535 A JP S63254535A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- circuit
- line
- interrupt
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 abstract description 3
- 230000000630 rising effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、割り込み回路、特にエツジモードの割り込み
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interrupt circuit, particularly an edge mode interrupt circuit.
〔従来技術の説明と問題点］
従来、この種の回路は割り込みを発生させる回路と、割
り込みを認識する回路が、割り込み信号ラインで直接つ
ながれており、割り込み信号ラインにインパルスノイズ
が加わると、誤って割り込みを′認識し、その結果誤動
作するという欠点があった。[Description and problems of the prior art] Conventionally, in this type of circuit, the circuit that generates an interrupt and the circuit that recognizes the interrupt are directly connected by an interrupt signal line, and when impulse noise is added to the interrupt signal line, an error occurs. It had the disadvantage that it recognized interrupts, resulting in malfunctions.
（問題点を解決するための手段）
本発明は、上述従来例の欠点を除去することを目的とし
て、割り込み信号の信号幅を検出する回路をそなえるこ
とにより、あらかじめ定められた信号幅を越えた時、割
り込みを認識するようにした。(Means for Solving the Problems) In order to eliminate the drawbacks of the above-mentioned conventional example, the present invention provides a circuit for detecting the signal width of an interrupt signal. Interrupts are now recognized.
第１〜２図は本発明の実施例で、１は種々の信号を基に
割り込み信号を発生させる回路、２は人力信号の立ち上
がりに同期して１個のパルスを出力するワンショットタ
イマ、３はＤ−タイプフリップフロップ、４は割り込み
信号の立ち上がりより、割り込みを認識する回路、βｌ
は割り込み信号ライン、！２はワンショットタイマ出力
、Ｉ１３はノイズ分の除去された割り込み信号ラインで
ある。1 and 2 show an embodiment of the present invention, in which 1 is a circuit that generates an interrupt signal based on various signals, 2 is a one-shot timer that outputs one pulse in synchronization with the rising edge of a human input signal, and 3 is a circuit that generates an interrupt signal based on various signals. is a D-type flip-flop, 4 is a circuit that recognizes an interrupt from the rising edge of the interrupt signal, βl
is the interrupt signal line,! 2 is a one-shot timer output, and I13 is an interrupt signal line from which noise has been removed.
第２図は本回路の動作例である。第２図のようにＪＺｌ
にＡ、Ｂ、Ｃのようなインパルスノイズが加わったとす
る。その立ち上がりに同期して２はｆｌ、２を出力する
。このとき、Ｄ−タイプフリップフロップにより、Ｉｌ
、３にはＩｌ２の立ち上がりでｆｌｌの状態が出力され
る。したがって、２の出力パルスより短いＡ、Ｂ、Ｃの
ノイズによりｆｌ３には変化が起らす（割り込みは発生
せず）、正式に割り込みの発生したＤの時点でのみ、４
に認識される割り込みＥが発生する。FIG. 2 shows an example of the operation of this circuit. JZl as shown in Figure 2
Suppose that impulse noises such as A, B, and C are added to. 2 outputs fl and 2 in synchronization with the rising edge. At this time, Il
, 3, the state of fll is output at the rising edge of Il2. Therefore, the noise of A, B, and C, which are shorter than the output pulse of 2, causes a change in fl3 (no interrupt occurs), and only at the time point D when an interrupt officially occurs, 4
An interrupt E is generated which is recognized as follows.
（発明の効果）
以上説明したように、エツジモードの割り込み回路に簡
単な回路を付加することで、ノイズにより誤動作を防止
する効果がある。(Effects of the Invention) As described above, adding a simple circuit to the edge mode interrupt circuit has the effect of preventing malfunctions caused by noise.
第１図は本発明の回路構成を示す図、第２図は各信号の
波形を示す図である。
１−一一割り込み発生回路、
２−ｍ−シヨツトタイマ、
３−−−Ｄ−タイプフリップフロップ、４−一一割り込
み認識回路。FIG. 1 is a diagram showing the circuit configuration of the present invention, and FIG. 2 is a diagram showing the waveforms of each signal. 1-11 interrupt generation circuit, 2-m-shot timer, 3--D-type flip-flop, 4-11 interrupt recognition circuit.
Claims (1)
み回路において、割り込み信号の信号幅を検出する回路
をそなえることにより、あらかじめ定められた信号幅を
こえた時、割り込みを認識するようにしたことを特徴と
する割り込み回路。The interrupt circuit recognizes an interrupt at the changing edge of the interrupt signal, and is characterized by having a circuit that detects the signal width of the interrupt signal, so that the interrupt is recognized when the signal width exceeds a predetermined signal width. interrupt circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62088100A JPS63254535A (en) | 1987-04-10 | 1987-04-10 | Interruption circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62088100A JPS63254535A (en) | 1987-04-10 | 1987-04-10 | Interruption circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63254535A true JPS63254535A (en) | 1988-10-21 |
Family
ID=13933449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62088100A Pending JPS63254535A (en) | 1987-04-10 | 1987-04-10 | Interruption circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63254535A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019082659A1 (en) * | 2017-10-26 | 2019-05-02 | オムロン株式会社 | Data acquisition method and data acquisition device |
-
1987
- 1987-04-10 JP JP62088100A patent/JPS63254535A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019082659A1 (en) * | 2017-10-26 | 2019-05-02 | オムロン株式会社 | Data acquisition method and data acquisition device |
| JP2019080242A (en) * | 2017-10-26 | 2019-05-23 | オムロン株式会社 | Data acquisition method and data acquisition device |
| US11056159B2 (en) | 2017-10-26 | 2021-07-06 | Omron Corporation | Data acquisition method and data acquisition apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3976734B2 (en) | Driver driving method, driver circuit, and transmission method | |
| JPS63254535A (en) | Interruption circuit | |
| JPH0537306A (en) | Flip-flop circuit | |
| JPS58155381A (en) | Arithmetic unit | |
| JPH02128287A (en) | Microcomputer | |
| JPS59132224A (en) | Digital circuit | |
| SU1585901A1 (en) | Device for convolution of fibonacci code | |
| JPS6327930A (en) | Interruption control circuit | |
| KR900005307Y1 (en) | Frequency alternating detective circuit | |
| JP2578990B2 (en) | Pulse width modulation circuit | |
| JPH04288727A (en) | A/d converter | |
| JPS6359017A (en) | Pulse generating circuit | |
| JPS62272617A (en) | Clock switching circuit | |
| JPH01245737A (en) | Serial data transfer circuit | |
| JPH04291654A (en) | Interruption control circuit | |
| JPH04321314A (en) | Selection circuit | |
| JPH0511683B2 (en) | ||
| JPH04156649A (en) | Interruption control circuit | |
| JPS62131623A (en) | Pulse noise elimination circuit | |
| JPS6354034A (en) | Detection circuit for plural pulse trains | |
| JPH0250613A (en) | Noise input preventing circuit | |
| KR930013936A (en) | SCSI reset circuit | |
| JPH048822B2 (en) | ||
| JPS62150924A (en) | N-train pulse detector | |
| JPH03119825A (en) | Semiconductor integrated circuit device |