JPS62272617A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To perform a clock switching without noise, by switching the first clock, and the second clock, by the second change point detection signal obtained from the first change point detection signal, and the second clock, after obtaining the first change point detection signal from the first clock, and a clock switching signal. CONSTITUTION:The titled circuit is formed by a change point de tecting means 6 which obtains the second change point detection signal by detecting the change point of the second clock from the first change point detection signal, and the second clock, after obtaining the first change point detection signal by detecting the change point of the first clock from the first clock, and the clock switching signal out of inputted first clock, second clock, and clock switching signal, and a switching means 5 which switches the first clock, and the second clock by the second change point detection signal from the change point detecting means. And by driving the switching means 5 by the second change point detection signal, and switching the first clock, and the second clock, the clock switching without noise can be performed.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In the clock switching circuit, after obtaining the first change point detection signal from the first clock and the clock switching signal, this first change inspection is performed. By switching between the first clock and the second clock using the second change point detection signal obtained from the output signal and the second clock, noise-free clock switching is performed.

(Industrial Application Field) The present invention relates to an improvement in a clock switching circuit that switches between two types of clocks having different frequencies, for example.

Generally, when transmitting data from a processing device to a terminal with a different data speed, the processing device switches the clock and sends the data to the terminal. Clock switching must be performed without noise so that operating parts do not malfunction.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a time chart of FIG. 5. Note that the numbers on the left side of FIG. 6 indicate the waveforms of the portions with the same numbers in FIG.

The operation shown in FIG. 5 will be explained below with reference to FIG.

First, a first clock (hereinafter abbreviated as GK-1) as shown in FIG. 2
) and clock switching signal (hereinafter referred to as C0NT
C0
When NT is "L", it is inverted to "H" by the inverting circuit 4 and applied to the AND circuit 2, so this circuit is turned on and GK-2 is outputted via the OR circuit 3.

However, when C0NT switches to "H", AND circuit 2 is turned off, AND circuit 1 is turned on, CK-1 is outputted via OR circuit 3, and CK-1 and CK-2 are switched (the first Figure 6 (see al-■).

[Problem that the invention seeks to solve]

However, for example, if the phase relationship between CK-1 and CK-2 is as shown in FIG. -1 is “L”
Therefore, noise marked with * is generated as shown in FIG. 6(b)-■', and if the circuit is operated using the falling edge of this clock, for example, a malfunction will occur.

That is, a problem arises in that noise is generated due to clock switching.

[Means for solving problems]

As shown in FIG. 1, the above problem is caused by the change in the first clock from the first clock and the clock switching signal among the input first clock, second clock, and clock switching signal. After detecting the point and obtaining the first change point detection signal, detect the change point of the second clock from the first change point detection signal and the second clock to perform a second change check. A changing point detecting means 6 for obtaining an output signal, and a second changing point detection signal from the changing point detecting means detect the first clock and the second clock.
This problem is solved by the clock switching circuit of the present invention, which includes a switching means 5 for switching between the clock and the clock.

[Effect]

In the present invention, after the change point detection means 6 obtains the first change point detection signal from the first clock and the clock control signal, the rising point of the second clock is determined from this detection signal and the second clock. A second change point detection signal having matching rising points is obtained. Then, the switching means 5 uses this second change point detection signal.
The clock is driven to switch between the first clock and the second clock, so that clock switching is performed without noise.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a time chart of FIG. 2, and ta+ in FIG.
Fig. 3 (bl corresponds to fbl in Fig. 6, respectively. AND circuit 1.2, OR circuit 3, and inverting circuit 4)
is the switching means 5, and the flip-flops 61 and 62 are the constituent parts of the change point detection means. Also, the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the operation of FIG. 2 will be explained with reference to FIG. 3 assuming that GK-2 is switched to GK-1.

First, GK-1 and GK shown in Fig. 3 (al-■, ■, ■)
-2 and C0NT are input, a D type flip-flop (hereinafter abbreviated as D-FF) 61 punches C0NT as data by CK-2, and as shown in FIG.
As shown in (2), a second change point detection signal that coincides with the rising edge of GK-2 is applied from terminal Q to [1-FF62.

Since CK-1 is added here, Figure 3 (al
As shown in -■, an output that coincides with the rising point of CK-1 is obtained, but the "L" portion passes through the inverting circuit 4 and turns on the AND circuit 2. Therefore, CK-2 is outputted via AND circuit 2 and OR circuit 3, but at the rising point of fa+-〇 in Fig. 3, AND circuit 2 is turned off, AND circuit 1 is turned on, and CK-2 is output from CK-2. The signal is switched to CK-1 and output via the OR circuit 3.

Next, the phase relationship between CLI and CK-2 in FIG. 3 (bl) is the same as that in FIG. 6 (bl).

That is, Fig. 3 fbl-■, ■1. CK-1,G shown in ■
When K-2 and C0NT are input, the D-FF 61 obtains the first change point detection signal shown in FIG. 3
A second change point detection signal is obtained, not shown in Figure (bl-■1).Then, this is used to switch AND circuits 2 and 1 to obtain the output of Figure 3 (bl-■°, but Figure 6 (bl-■
Since the noise marked with an * disappears, clock switching is performed without noise, and circuits that operate on the falling edge of this clock do not malfunction.

FIG. 4 is a block diagram of another embodiment of the present invention, in which the D-FF
Since inversion circuits 7 and 8 are connected to the clock input sides of clocks 61 and 62, respectively, this is effective when a circuit connected to this clock switching circuit requires a rising clock.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that clock switching can be performed without noise.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart of Fig. 2, Fig. 4 is a block diagram of another embodiment of the invention, FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a time chart of FIG. 5. In the figure, 5 is a switching means, 6 is a change point detection means, and 61 and 62 are D type flip-flops. I ν [((Jl+1 e OO■ O■ ○ b Ri Ri Ri Ri 5 time now w-1 Figure B

Claims (1)

[Claims] Among the input first clock, second clock, and clock switching signal, a changing point of the first clock is detected from the first clock and the clock switching signal to generate a first changing point detection signal. change point detection means (6) for obtaining a second change point detection signal by detecting a change point of the second clock from the first change point detection signal and the second clock; A clock switching circuit comprising: switching means (5) for switching between the first clock and the second clock in response to a second change point detection signal from the change point detection means.