JPH01245737A - Serial data transfer circuit - Google Patents

Abstract

PURPOSE:To attain normal operation as to the transfer after a section of a serial data transfer group is detected even if a serial data transfer circuit malfunction by adding a circuit generating a section detection signal of a serial data transfer group to the serial data transfer circuit. CONSTITUTION:T flip-flop circuits 4, 5 with reset and a two-input OR circuit 6 are added to a conventional circuit to constitute the transfer circuit. The flip-flop 4 receives a time base signal (g) at its T input, the flip-flop 5 applying 1/2 frequency division receives an output of the flip-flop 4 at its T input to generate a section detection signal of the serial data transfer group. When a leading edge of the time base signal (g) is detected twice, although the section detection signal of the serial data transfer group is outputted, since an OR output (j) between the serial transfer clock (b) and a system reset (f) is provided in the reset of the flip-flops 4, 5 the section detection signal (h) of the serial data transfer group is outputted if the serial data transfer is not applied for a maximum of 2t' (t' is the period of the time base signal (g)) and for a minimum of t'.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a serial data transfer circuit in which a circuit for generating a signal for clearly demarcating serial data transfer groups is added to the serial data transfer circuit.

2. Description of the Related Art In recent years, data transfer circuits often use serial data transfer circuits that have a function of transmitting and receiving data with a small number of terminals.

A conventional serial data transfer circuit will be explained below.

FIG. 3 shows an example of a serial data transfer circuit, in which shift registers 1. Data bus 2. It consists of 3 counters. Input a is serial reception data, input is serial transfer clock, output C is serial transmission data,
Output d is a serial interrupt signal, and input/output e is shift register data.

The operation of the serial data transfer circuit configured as described above will be described below.

The shift register 1 performs a shift operation using a serial transfer clock b, and a counter 3 counts the number of shift operations. When the bit length of data is reached, a serial interrupt signal d is generated.

This serial interrupt signal d causes a program or circuit to interrupt the shift register 1 and the data bus 2.
READ of serial transfer data via input/output signal e
(reception mode)/WRITE (transmission mode) is performed.

Problems to be Solved by the Invention However, in the above conventional configuration, the timing of the serial interrupt signal d generated by the counter 3 changes when the voltage level of the serial transfer clock changes or when the serial transfer clock is affected by noise. I'm tired,
There is a problem that the serial data transfer circuit may malfunction.

The present invention solves the above problem, and even when the above malfunction occurs, it is possible to detect a break in a serial data transfer group and to perform normal operation for serial data transfer after the break is detected. The purpose is to provide a serial data transfer circuit that can

Means for Solving the Problems To achieve this object, the serial data transfer circuit of the present invention has a circuit configuration that generates a delimiter detection signal for a serial data transfer group using a time base signal having a specific frequency as a reference. have.

With this configuration, even if the above-mentioned malfunction occurs, the serial transfer circuit can be initialized programmatically or circuit-wise using the signal that detects the delimitation of the serial data transfer group. The serial data transfer after detecting the break can operate normally, and is particularly effective when serial data is transferred within a range divided by a certain period.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which 1 is a shift register, 2 is a data bus, 3 is a counter, input a is serial reception data, b is serial transfer clock, output C is serial transmission data, and output d is a serial interrupt signal, and input/output e is shift register data, which are the same as the conventional configuration.

This includes T flip-flops 4 and 5 with reset and 2 inputs O
It is constructed by adding an R circuit 6, the input f is a system reset, the input g is a time base signal, and the output is a serial data transfer group delimitation detection signal.

FIG. 2 shows signal waveforms at various parts of the serial data transfer circuit shown in FIG. 1 when the data bit length is 4 bits and one serial data transfer group is formed by two serial data transfers.

In FIG. 2, t is the time interval of serial data transfer in the serial data transfer group, T is the time interval of the serial data transfer group, and t' is the period of the time base signal.

When the rising edge of the time base signal g is detected twice,
The delimiter detection signal of the serial data transfer group is output, but
Since the reset of T flip-flop 4-4.5 includes the logical sum (OR) output J of the serial transfer clock b and the system reset f, serial If data transfer is not performed, the delimiter detection signal of the serial data transfer group will be output.

In other words, when t, t', and T have the relationship 2t<2t'<T, a serial data transfer group delimitation detection signal is output at h.

As described above, according to this embodiment, the above 2t<2t'<T
By using a serial data transfer group delimitation detection circuit that uses a time base signal having a frequency that satisfies the following conditions, the serial data transfer group delimitation detection signal can be used to programmatically or circuitically detect the serial data. By initializing the transfer circuit, even if a malfunction occurs in the serial data transfer circuit, serial data transfer after detecting the end of a serial data transfer group will be performed.
Can perform normal operations.

Note that the effects of this embodiment are effective when transmitting and receiving serial data transfer.

Furthermore, even in serial data transfer that does not form a transfer group, a break can be detected for each serial data transfer.

Further, in this embodiment, the input f is used as a system reset signal, but any signal other than the system reset signal may be used as long as it is a signal for setting the initial value of the T flip-flop with reset 4.5.

Effects of the Invention As is clear from the above explanation, according to the present invention, by adding a circuit to the serial data transfer circuit to generate a delimiter detection signal for a serial data transfer group, it is possible to prevent the serial data transfer circuit from malfunctioning. Also, regarding serial data transfer after detecting the end of a serial data transfer group,
This makes it possible to realize an excellent serial data transfer circuit that can operate normally.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a serial data transfer delimiter detection circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part in the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of a conventional serial data transfer circuit. It is a circuit diagram. 1...Shift register, 2...Data bus, 3...Counter, 4, 5...T flip-flop with reset, 6...・Order circuit.

Claims (1)

[Claims] a first T flip-flop that receives a time base signal having a specific frequency at its T input and divides the frequency of the time base signal by half, and receives the output of the first T flip-flop at its T input; a second T flip-flop that generates a delimiter detection signal for a serial data transfer group; a two-input OR circuit that has two inputs: a serial transfer clock and a system reset; and resets the first and second T flip-flops. A serial data transfer circuit comprising: