JPS63252477A - Bipolar semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To fine an IC element, and to increase the working speed of the IC element by isolating a transistor element by a dielectric insulating layer surrounded from the cross direction and the longitudinal direction on a substrate. CONSTITUTION:A P<+> diffusion layer is formed to a P-type Si substrate 1, and an N<+> buried layer 3 and an N<-> epitaxial layer 4 are shaped in succession. An oxide film 9 is attached onto the surface of the epitaxial layer 4, and vertical trenches 6 are cut through ion etching. Only the P<+> diffusion layer is etched selectively to form transverse trenches while Si oxide films 5 are affixed onto the whole wall surfaces of the trenches. The ions of a P<+> type impurity are implanted to shape channel-stoppers 10, poly Si is vapor-grown, and the insides of the trenches are buried with the poly Si layers 6. An N-P-N bipolar transistor respectively using an N<+> diffusion layer 7, a P diffusion layer 8 and the N<-> epitaxial layer as emitter, base and collector regions is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar semiconductor integrated circuit device, and particularly to the structure of an isolation region between elements.

[Conventional technology]

Conventionally, element isolation regions of bipolar semiconductor integrated circuit devices are formed by a substrate using a PN junction, a high concentration layer of opposite conductivity type, or a thick oxide film commonly called the LOCOS method.

[Problem that the invention seeks to solve]

However, these conventional structures of element isolation regions each have major drawbacks in response to recent demands for miniaturization and increased speed. In other words, the former type using a P-N junction requires a lateral spread of the depletion layer to ensure dielectric strength, so the transistor element cannot be miniaturized, and the insulation capacitance component is also large. Therefore, it is very difficult to form high-speed circuits such as switching circuits, and although the latter LOCOS method can considerably improve the high-speed performance of switching circuits and the like compared to the former, it is still far from being sufficient and is not suitable for miniaturization. However, it is still in an insufficient state. In other words, in the LOCOS method, although the device can be sufficiently isolated in the lateral direction using a dielectric layer made of a thick oxide film, isolation from the substrate is still achieved using a P-N junction, which makes it difficult to configure high-speed circuits and devices. There are limits to the miniaturization of

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a bipolar semiconductor integrated circuit device that includes a dielectric isolation region that can sufficiently insulate transistor elements in the horizontal and vertical directions.

[Means for solving problems]

According to the present invention, the bipolar semiconductor integrated circuit device includes:
A semiconductor substrate, a horizontal bipolar transistor element formed on the semiconductor substrate, a silicon oxide film attached to the wall surface of a cut groove surrounding the bipolar transistor element in the horizontal and vertical directions, and polysilicon filling the inside. and an element isolation region of a dielectric insulating layer.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a partial sectional view of a bipolar semiconductor integrated circuit device showing an embodiment of the present invention. According to this embodiment, the bipolar semiconductor integrated circuit device includes a P-type silicon substrate 1
A vertical groove and a horizontal groove are formed by vertically penetrating the P+ diffusion layer 2, N+ buried layer 3, and N- epitaxial layer 4 formed on this substrate surface, and cutting the P+ diffusion layer 2 laterally. An element isolation region formed from a silicon oxide film 5 formed on the entire wall surface of the trench and a polysilicon layer 6 buried in these trenches, an N" diffusion layer 7, a P type diffusion layer 8 and an N
- NPN bipolar transistors with epitaxial layer 4 as their emitter, base and collector regions, respectively. Here, 9 and 10 represent a silicon oxide insulating film and a P+ channel stopper, respectively, and E, B, and C represent emitter, base, and collector electrode wirings, respectively.

According to this embodiment, the element isolation region can dielectrically isolate the transistor elements not only in the horizontal direction but also in most of the vertical direction, so that the vertical capacitance of the transistor can be reduced to about 1/2 of the conventional capacitance.

The structure of this embodiment can be formed as follows. That is, first, P+ diffusion N (impurity concentration 5 x 1018"/c113~1
×1020f/cIII3) After forming N+ buried layer 3
(I x 1018”/crs3~5 x 1019
” 7 cm thick and N-epitaxial layer 4 (IXIO
""/c113 to 1×1017'/Cll3) are sequentially formed. Next, an oxide film 9 is formed on the surface of the N-type epitaxial layer 4, and ion etching is performed using PR technology to form vertical grooves 6.
dig. The depth of this groove may be deep enough to reach the previous P'' type diffusion layer or deeper than that. After that, only the P+ diffusion layer is selectively etched using a hydrazine solution, and the bottom of the groove is widened laterally to form a lateral groove. At the same time, the silicon oxide film 5 is oxidized in an oxidizing atmosphere to adhere to all the walls of the vertical and horizontal grooves.Next, using the thick oxide film 9 on the surface as a mask, P+ type impurities are ion-implanted to reduce the parasitics between each element. After providing the channel stopper 10 for preventing the effect, vapor phase growth of polysilicon is performed to completely fill the inside of the vertical and horizontal grooves with the polysilicon layer 6. Through the above steps, the formation of the isolation region between elements is completed. Therefore, the structure of the semiconductor integrated circuit device of this embodiment is completed by performing various diffusion steps for the base, emitter, and collector contact layers and wiring the electrodes according to conventional techniques.

FIG. 2 is a partial sectional view of a bipolar semiconductor integrated circuit device showing another embodiment of the present invention. According to this embodiment,
A structure of an element isolation region that provides dielectric isolation in all vertical directions is shown. That is, a lateral groove portion of a dielectric isolation layer consisting of silicon oxide film 5 and polysilicon layer 6 is formed over the entire surface of silicon substrate 1. Therefore, according to this embodiment, the vertical capacitance of the transistor is reduced to about 1/3 of that of the conventional one, making it possible to achieve extremely high speed. The structure of this embodiment can be easily formed as follows.

FIG. 3 is a partial process diagram showing one method for forming the structure of the embodiment shown in FIG. 2, in which the vertical grooves are formed in two steps.

That is, first, a P1 diffusion layer 2 (with an impurity concentration of 5 x 1018'/cm3 to I x 10
20'/cm3) is patterned as shown, and then the N+ buried layer 3 (I x 1018"/cm'~
5 X 1019"/cm') and N-epitaxial layer 4 (IX 1015"/am3~lX
I Q"/cn+re are respectively formed. Then,
An oxide insulating film 9 is attached to the surface of the N-type epitaxial layer 4, and vertical grooves 12 are dug by ion etching using PR technology. The depth of this groove may be as deep as reaching the P1 diffusion layer 2 or deeper than that. Thereafter, only the P+ diffusion layer 2 is selectively etched using a hydrazine solution, and the bottoms of the vertical grooves 12 are laterally expanded to form horizontal grooves. At this time, the entire pattern of the P" diffusion layer 2 is removed. Here, as in the previous embodiment, the silicon oxide film 3 is oxidized in an oxidizing atmosphere to form a silicon oxide film 3 on the entire surface of the vertical grooves 12 and the formed horizontal grooves. Next, using the oxide insulating film 9 on the surface as a mask, P+ type impurities are ion-implanted to provide a channel stopper 10, and then vertical trenches 12 and horizontal trenches are completely filled with a polysilicon layer 6 by vapor phase growth of polysilicon. Next, a PR mask is applied to the silicon oxide insulation M9 again, and a vertical groove (indicated by a dotted line) 13 is dug on the patterned insulation part of the P+ diffusion layer 2. Thereafter, a silicon oxide film 5 is formed on the entire inner wall of the vertical groove 13 using exactly the same method. , to form a channel stopper 11, and further fill the inside of the groove with a polysilicon layer 6.
The structure is completed by forming a transistor element within the region surrounded by vertical grooves 12 and 13.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the bipolar transistor element is dielectrically isolated in both the horizontal and vertical directions on the substrate, so that the insulation capacitance in the vertical direction is 1/2 to 1/2 that of the conventional one. /3. Furthermore, since the width of the dielectric isolation region can be significantly reduced compared to conventional insulation systems, it is possible to easily obtain miniaturized and faster semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a partial sectional view of a bipolar semiconductor integrated circuit device showing one embodiment of the present invention, FIG. 2 is a partial sectional view of a bipolar semiconductor integrated circuit device showing another embodiment of the invention,
FIG. 3 is a partial process diagram showing one method of forming the embodiment structure of FIG. 2. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... P'' diffusion layer, 3...
...N" buried layer, 4...N- epitaxial layer (collector region), 5... silicon oxide film, 6... polysilicon layer, 7... N1 diffusion layer (emitter region), 8・
...P-type diffusion layer (base region), 9...Silicon oxide insulating film, 10.11...Channel stopper, 12
゜13...m groove, E...emitter electrode wiring, B...
・Base electrode wiring, C...Collector electrode wiring. Agent Patent Attorney Susumu Uchihara 1st Q Ko1ri 9th Den ψ Tetsumi eζ

Claims (1)

[Claims] A semiconductor substrate, a horizontal bipolar transistor element formed on the semiconductor substrate, a silicon oxide film attached to the wall surface of a cut groove surrounding the bipolar transistor element in the horizontal and vertical directions, and polysilicon filling the inside. 1. A bipolar semiconductor integrated circuit device comprising an element isolation region of a dielectric insulating layer.