JPS6286760A - Transistor with polycrystalline side wall and manufacture ofthe same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to electronic devices;
More particularly, the present invention relates to an improved apparatus and method for providing compact high performance devices with sidewall contacts suitable for use in large scale integrated circuits. SUMMARY OF THE INVENTION By making lateral contacts to columnar single crystal device regions using polycrystalline (e.g., polysilicon) multiple layers,
An improved bipolar transistor is created with minimal base-collector and collector-substrate junction area. Lateral polysilicon contacts are separated from each other and from the substrate and extend to the top surface of the device for external connections. This structure involves depositing two dielectric-polysilicon layer sandwiches, etching and oxidizing portions of the polysilicon layer to create separate overlapping polysilicon regions, and penetrating both polysilicon regions. It is created by etching a first hole down to the substrate, etching a second hole down to the underlying polysilicon layer, and filling the first and second holes with monocrystalline silicon and polycrystalline silicon, respectively. Sidewall oxide is created around the top of the single crystal pillar to define the emitter location without additional steps. BACKGROUND OF THE INVENTION There continues to be a desire in semiconductor technology to manufacture transistors of smaller dimensions. In many applications, this means that smaller devices can
This is because it is possible to obtain circuits that are more complex, faster in performance, and consume less power. It is also generally desirable that individual devices be electrically isolated from each other. For example, in high-speed, low-power bipolar transistors and integrated circuits, individual devices are manufactured using junction isolation and oxide-filled trenches etched into the semiconductor substrate.
usually separated by a combination of es). Typically, metal interconnections are made to the emitter, base, and collector contact regions on the upper surface of the active region of the device. The minimum device size is the smallest lithographic dimensions that can be obtained.
) and alignment tolerances between successive mask layers. Although currently available device structures and methods allow the creation of highly complex integrated circuits, these circuits still have a number of significant limitations. For example, in a typical planar bipolar transistor, the base-collector junction area and collector-substrate junction area are needed only for the desired transistor operation due to the need to leave room on the top surface of the device for the contact area. larger than the area These larger than desired junction areas can introduce undesirable parasitic capacitance that limits device or circuit performance. These larger areas reduce the storage density and circuit complexity that can be obtained. A partial solution to this problem has been proposed in the prior art by using "pillar" transistors with lateral polysilicon-based contacts. However, these prior art structures still suffer from excessive collector substrate capacitance. Accordingly, there remains a need for device structures and manufacturing methods that overcome or avoid one or more limitations of the prior art. Accordingly, the circuit of the present invention provides an improved apparatus and method for minimal feature semiconductor devices with reduced base-collector and collector substrate junction areas. Another object of the present invention is to provide improved means and methods for making transistors in which electrical connections to buried active device areas are made on the sides. Another object of the present invention is to provide improved means and methods for making bipolar transistors using buried sidewall contacts to buried device regions. Another object of the present invention is to provide an improved means and method for creating individually separable device structures. Another object of the invention is to provide a symmetrical bipolar device in which the collector and emitter functions are easily interchangeable, ie with similar characteristics in collector-up or collector-down operation. The term “polycrystalline” or “poly” used here
)" is intended to include all single crystal forms of solids. As used herein, the term "dip etching" is intended to include all forms of blanket etching.
wet chemical etching (wet chemical etching) or erosion.
It is not intended to be limited to only chemical etching. SUMMARY OF THE INVENTION The above and other objects and advantages are achieved by providing a monocrystalline substrate, a monocrystalline semiconductor pillar having a lower surface resting on the substrate, the lower surface being spaced from the substrate, and upper and lower surfaces. The present invention has first and second device regions extending laterally through the single crystal column to the sidewalls with sidewalls between the first and second device regions. a first electrically insulated from the substrate;
A polycrystalline conductor region is provided for contacting the first device region of the single crystal column at the sidewall and has an extension extending to the top surface of the device. A second polycrystalline conductor region, electrically insulated from the substrate and the first polycrystalline conductor region, contacts a second device region of the single crystal column at a sidewall. Optionally, another dielectric layer is provided above the second polycrystalline conductor layer extending to the upper surface of the single crystal column. The dielectric layer has an opening above the central portion of the top surface of the pillar, an opening above a portion of the second polycrystalline conductor region, and an extension of the first polycrystalline conductor region that reaches the top surface of the device. It has an opening above. Electrical connections to the device are made through these openings. The foregoing and other objects and advantages are achieved by the present invention, which provides a process for manufacturing a semiconductor device, which process comprises a single crystal substrate and a second semiconductor device electrically insulated from the substrate. a second polycrystalline conductor region having a first portion insulated from the substrate and the first polycrystalline conductor region and overlapping a first portion of the first polycrystalline conductor region; above the substrate. A first opening is formed through at least a portion of the overlapping first and second polycrystalline conductor regions and a first portion of the intervening dielectric layer, the opening extending through to the substrate. A first opening laterally separated from the second polycrystalline conductor region extends through the dielectric layer separating the two polycrystalline conductor regions and into the first polycrystalline conductor region. A portion of the first opening is filled with a single crystal semiconductor material that contacts the edges of both the first and second polycrystalline body regions exposed in the first opening. A portion of the second opening is in contact with the first polycrystalline conductor region.
filled with body material. These filled portions extend near the top surface of the device. An overlying dielectric layer is provided in which contact holes are made to allow electrical connection with the single crystal semiconductor material and the polycrystalline conductor region. In the case of an NPN bipolar transistor, the substrate is P-doped and the first polycrystalline conductor region is N-doped.
The second polycrystalline conductor layer makes a sidewall contact to the N-type collector portion of the device structure as a +-doped polycrystalline conductor, and the second polycrystalline conductor layer makes a sidewall contact to the P-type base region of the device as a P+-doped polycrystalline conductor. It is convenient. A single masking layer is used to define the location and size of the first and second openings. The lateral dimensions of the first and second polycrystalline conductor layers are preferably defined by masking them with an oxidation-resistant mask and converting the exposed parts to a dielectric oxide, which dielectric oxide is a continuous conductive layer. Provides electrical insulation between layers.

[Brief explanation of drawings]

For purposes of explanation, the device structure illustrated here is shown as a bipolar device having a particular combination of N and P layers. However, these device structures and doped layer combinations are presented merely as an aid to understanding and are not intended to be limiting, and the combinations of N and P layers or regions with other device types are provided merely as an aid to understanding and are not intended to be limiting. Those skilled in the art will appreciate that combinations may similarly be used and made according to the teachings of the present invention. Figure 1 A~
FIG. 1B shows a simplified schematic side sectional view and top view of a portion of a typical semiconductor device made in accordance with the prior art. The semiconductor device portion IO includes a P-type substrate 11 covered by an epitaxial layer 12 and having a buried N+ region 16, an N-type substrate 11, and an N-type substrate 11 covered by an epitaxial layer 12. area 17, P-shaped base area 19. N
10 emitter region 23, N0 collector contact region 18, P+
It consists of a base contact area 20 and a dielectric layer 13. Dielectric layer 13 is transparent in FIG. 1B. Device portion 10 is surrounded by a dielectric isolation wall 14 . Collector contact region 18 is separated from emitter 23 by an additional dielectric separating wall 15 . electrical contact 22a,
22b and 22c are provided to base contact region 20, emitter region 23 and collector contact region 18, respectively. Means for fabricating such devices are well known in the art. FIG. 1C is a simplified schematic side cross-sectional view of another bipolar device structure known in the prior art. The device part 30 includes a single crystal substrate 21 on which a buried collector region 26 is placed, a dielectric layer 31 is a collector part 2
8, surrounding a columnar single crystal device region 27 consisting of a base portion 29 and an emitter portion 33. In contrast to the structure of the device 10 of FIG. 1A, the base portion 29 of the device of FIG. 1C does not extend directly to the top surface of the device 30. Instead, the contact to the base portion 29 is made by a P-polycrystalline silicon layer 34 which abuts the base portion 29 of the single-crystal device region 27 at the lateral periphery. Electrical contacts to device 30 include metal 32a in contact with polycrystalline region 34, metal 32b in contact with emitter 33, and buried collector region 26.
This is done by the metal 32c that is in contact with the metal 32c. A drawback of the structure of FIG. 1A is that the active base and collector regions are elongated, resulting in large base-collector and collector-substrate junction areas. The structure of FIG. 1C requires an additional base to provide a base contact.
This is an improvement to the extent that no collector junction area is required. However, the structure of FIG. 1C does not significantly reduce the collector substrate junction area. This point, along with other points, can reduce device performance and increase device size. These and other problems are solved by the present invention in FIG.
~ Solved by the structure shown in the second diagram. Figures 2A-2 show simplified schematic cross-sectional views of NPN device portion 40 including substrate 41 with heavy layers 42-46. The dielectric regions 42-46 are suitable for silicon oxide, silicon nitride, or a combination thereof. Other dielectric materials that can withstand the processing used to create pillars 49 can also be used. A single crystal semiconductor pillar 49 passes through the dielectric regions 42-46 and has an N0 buried collector 49a, an N type collector region 49b, a P type base region 49c and an N0 emitter region 49d formed therein. There is. Collector area 4
Electrical contact to 9a-b and base region 49c is made laterally at the periphery of single crystal column 49 by polycrystalline regions 47a-b and 48a-b, respectively. Collector contact areas 47a-b consist of relatively thin lateral contact portions 47a and capital areas 47b. The pillar 47b is the side contact portion 47a.
is brought into contact with the external contact 50c. Polycrystalline base contact regions 48a-b consist of relatively thin lateral contact portions 48a and optional vertical contact portions 48b extending to external base contact 50a. Portion 48b may optionally be metal (see, eg, FIG. 3J), with external contact 50b contacting N0 emitter region 49d of single crystal region 49. Polycrystalline regions 47a-s and 48a-b
It is convenient to use polycrystalline silicon, but single crystal pillar 4
Other conductors that can make suitable contact to 9 and that can withstand the processing necessary to create the pillars, dielectric and conductor layers can also be used. Silicides, intermetallic compounds and metals are useful. It would be advantageous if those materials readily formed stable dielectric oxides for regions 43 and 45. Figures 2B-2 show simplified schematic plan cross-sectional views of Figure 2A taken at different levels within the structure. To facilitate understanding in Figures 2B to 2, single-crystal regions are shown as blank, dielectric regions are shown with diagonal shading, and polycrystalline conductor regions are shown with dots. This is an indication. In FIGS. 2B-2C, the position of columnar portions 47b and 48b above lateral contact portions 47a and 48a is indicated by dashed lines. The structure of FIGS. 2A-2A is such that the single crystal active device region 49 provides the necessary drive current since both the base and collector contacts are made laterally by layers 48a-b and 47a-b. The base-collector junction area and the collector-substrate junction area are small because the size of the base-collector junction area is sufficient and no additional area is required to provide a planar contact. Polycrystalline contacts 47a-b are separated from substrate 41 by dielectric region 42. Polycrystalline contacts 48a-b are separated from polycrystalline regions 47a-b and substrate 41 by dielectric regions 42-45. This combination of structural features can reduce parasitic capacitance associated with the device, thus improving performance with smaller device area. The devices of FIGS. 2A-2 are inherently self-separating, ie, there is no need for special separation walls such as 14.15 of FIG. FIG. 3A-FIG. 31 is a preferred embodiment of FIG. 2A--
Figure 2 shows simplified schematic cross-sectional views at various stages of manufacture of Figure 2 in more detail than Figure 2; Manufacturing order is NPN
) The case of a transistor is shown. As shown in FIG. 3A, device portion 60 includes a P-type substrate 61 with a P+ channel stop region 61a. Channel stop region 61a is convenient but not absolutely necessary to the invention. The substrate 61 is covered with a dielectric layer 62, an N-polycrystalline wing layer 63, and a mask layer 64. Channel stop region 61a, dielectric layer 62, polycrystalline layer 63 and mask layer 84 are made by means well known in the art. If layer 63 is a semiconductor, for example polysilicon, it is convenient to dope it with N+ to form an NPN device therein. A pattern is drawn on the mask layer 84 to provide a protective portion 84a and an opening portion 84b (FIG. 3B). Desirably, mask layer 84 is resistant to etching and oxidation. This is because the polycrystalline layer 63
This is because the exposed portion of the polycrystalline region 63a can be turned into a dielectric region, leaving the polycrystalline region 63a almost undisturbed. This is approximately 30-60% of the exposed polysilicon thickness.
This is conveniently done by first etching away the % and then converting it to oxide region 63b using gaseous oxygen at high temperature. This is desirable because the oxide occupies more space than the polycrystalline and therefore should be removed if it is desired that the top surfaces of regions 63a and 63b be approximately coplanar. It is. Dielectric layer 63h and polycrystalline region 63a
Other methods for obtaining can also be used. Mask 84a is then removed and the structure is covered by dielectric layer 64, polycrystalline conductor layer 65 and mask layer 86. If polysilicon is used for layer 65, P+ doping is convenient. The mask layer 86 is exposed and protected.
! Mask 86a is used to draw a pattern to provide region 86a and opening 86b (FIG. 3C).
The polycrystalline layer 65 is partially transformed into a dielectric region 65b using the same method used in connection with 4a, leaving a largely undisturbed polycrystalline portion 65a (FIG. 3D). After removing the mask 86a, it is desirable to cover the structure by a mask 67 with openings (i7a-b) and the dielectric layer 66. 65 cmd and portions 64a-b of layer 64 are removed as shown in Figure 3. Using an anisotropic etching technique, the openings 67a-b were made through layers 64-66 below. It is desirable that the holes have relatively straight sides as shown in Figure 3. This procedure exposes portions of the upper surface of polycrystalline semiconductor regions 63c and 63d below openings 67a-b. An additional masking layer 68 with openings 68a is then applied (FIG. 3E); the underlying masking layer 67 may be left intact, but this is not absolutely necessary. This means that the openings 67a-b are replicated in the layer 66 (
This is because the mask 6
8 must cover the opening 67b. Layer opening 68a may be larger than opening 67a. This is preferred to facilitate alignment. Using the combination of openings 68a and 67λ, the portion 63 of the region 63a below the opening 67a
c and portion 62a of layer 62 to expose region 61b of substrate 61 below opening 67a (FIG. 3, bottom);
Masks 6'/ and 68 are removed. This procedure is layer 6
an opening 67 extending through 2-66 to substrate 61;
a hole 90 having approximately the same lateral dimensions as a, and layer 64.
-Create a hole 91 with approximately the same lateral dimensions as the opening 67b extending through the layer 66 and into the layer 63 (Figure 3, bottom).
. At this stage in the process, lateral edges 63e and 65e of polycrystalline layers 63 and 65 and areas 61b of substrate 61 are exposed within hole 90, with portion 63d of layer 63 at the bottom of hole 91. It is exposed (Fig. 3F). Next, a single crystal epitaxial region 72 is formed within the hole 90 over the exposed portion 61b of the substrate 61. Figure 3A-3
For the particular combination of conductivity types shown in Figure J,
The epitaxial single crystal region 72 includes a lower N-doped region 72a and an upper P-doped region 72a. 2b is desirable. The single crystal region 72 may completely fill the hole 90, or it may partially fill the hole 90, just enough so that the single crystal region 72 reaches the lateral P+ polycrystalline contact portion 65a. It is sufficient to fill the hole 90. Single crystal epitaxial region 72 is preferably formed by selective epitaxial growth using means well known in the art. 700 silane at a temperature of 925-1100 °C) lCI
It has been discovered that epitaxial growth with a silicon to chlorine atom CC in the range 0.1 to 0.5 using a mixture with 1 gives satisfactory results. (lower than atmospheric pressure)
Vacuum growth is preferred. The growth time is adjusted to fill holes 90 to about the level of layer 66. Upper P shadow area 7
2b may be created by changing the doping type during the growth of region 72, or by doping after growth using means well known in the art, such as ion implantation. As a result of the necessary heating cycles associated with the growth of region 72 and/or subsequent doping to create P region 72b, region 72c moves from P region 65a into the relatively lightly doped material of single crystal region 72. Region 72d becomes more heavily N-doped by out-diffusion into the relatively lightly doped material of single-crystal region 72 from region 63a. This out-diffusion doping of pillars 72 ensures that low resistance ohmic contacts to base region 72b and collector region 72a are obtained. When the P-doped region 72b is not provided on a specific pillar,
Out-diffusion from the P region 65a causes PN to the N-doped portion 72a of the pillar 62 adjacent to the polycrystalline region 65a.
Make a joining contact. As will be discussed below in connection with FIGS. 4A-4B, this variation can be applied to lateral transistors, e.g.
NP) is useful for making transistors. Holes 90 are filled with monocrystalline pillars 72, while holes 91 below mask openings 71b are conveniently filled with polycrystalline regions or pillars 73. Pillar 73 is polycrystalline region 6
It is in direct contact with the portion 63d of 3a. Polycrystalline region 7
3 and single crystal region 72 are conveniently made during the same epitaxial growth hill production, but this is not absolutely necessary. It is well known that polycrystalline semiconductor materials grow from polycrystalline surfaces at the same time that single-crystalline semiconductor materials grow from single-crystal surfaces. It is desirable that little or no semiconductor be deposited on the surface of dielectric breakdown layer 66 during epitaxial and polycrystalline growth. Means for making this distinction are well known in the art. At this point in the process, a bipolar transistor may be formed in single crystal material 72 by adding an N+ dont to region 72d on top of region 72b (FIG. 3G). However, excellent device characteristics are the third
Figures H to 3 are obtained by using the procedure shown in Figure 1. After growth of monocrystalline regions 72 and polycrystalline regions 73, a dielectric layer 77 is deposited over the structure (FIG. 3H). Does layer 77 cover upper surface 74 of single crystal region 72? 7c
, has a portion 77a1 overlying dielectric layer 66 and a corner portion 77b following the exterior of the step height change between upper surface 66a of layer 66 and upper surface 74 of single crystal region 72. In order for layer 77 to trace outside the surface as shown in FIG. 3H, it is important to deposit or form layer 77 by a conformal coating method. Silicon oxide, silicon nitride or a combination thereof are suitable for layer 77. Means for providing conformal coatings of such materials are well known in the art. Layer 77 is then anisotropically etched to remove thickness 77e using, for example, reactive ion etching or ion milling (techniques well known in the art). This anisotropic etching should be performed so as to etch only substantially vertically and not horizontally. At the end of this step, the structure shown in FIG. 3I is obtained in which corner portions 77b of layer 77 remain above the periphery of single crystal region 72. The corner portion 77b serves as a convenient mask, so
For example, by ion implantation, the N0 region 75 is replaced by the single crystal region 7.
It may be placed in the central portion of the surface 74 of 2. This step is conveniently performed without additional masking. This is because implanting the N0 impurity into the exposed upper portions of the polycrystalline pillars 73 creates or promotes the desired N0 conductivity type (FIG. 3). Alternatively, polycrystalline regions or pillars 73 may be doped separately over them. Next, a hole 92 is made in the dielectric layer 66 to form a polycrystalline region 65a.
A part of the base connection part 78a is exposed and the base connection part 78a is fitted there. Emitter connection 78b is applied to emitter region 75 and collector connection 78c is applied to N-polycrystalline region 73 (FIG. 3I), connections 78a-C may be metal or other conductive material, such as polysilicon. . FIG. 3I shows another variation in which an N+ region 72g is provided at the bottom of the pillar 72 to reduce the collector series resistance. This is conveniently done using a higher N doping concentration during the initial stages of epitaxial growth of pillars 72. FIGS. 4A to 4C show N according to still another embodiment of the present invention.
1 shows a simplified schematic cross-sectional view of a PN vertical transistor 100 and a PNP lateral transistor. For clarity, the single crystal region is shown as a single point;
Embedded conductors (e.g., polysilicon) are shown with a small number of dots, dielectric regions are shown with diagonal shading, and surface conductor regions (e.g., metal) are shown with a large number of dots. be. The layers and regions shown in FIGS. 4A-4C generally correspond to the layers and regions shown in FIGS. 3A-3J. The vertical transistor 100 is shown in FIG.
Made according to the procedure described in connection with FIG. 3J. Single crystal column 72 of vertical transistor 100 has N regions 72e and 72g, N region 72a and P region 72b. Either N+ region 72e or 72g can serve as an emitter or collector since the shape of this structure is approximately symmetrical. A lateral transistor 101 is fabricated in another single crystal region 72 by the same procedure, except that the P TsM region 72b is omitted. Separate P-polycrystalline regions 651 and 652 create P-doped regions 72h and 72i in N If, 77, region 72a of pillar 72 of transistor 101 by out-diffusion. Area 72h
-t serves as the emitter and collector of the lateral PNP transistor 101. FIG. 4A shows devices 100 and 101 as independent, isolated devices, and FIG. 4B shows the same device 100 interconnected by a buried polycrystalline region 103.
and 101 are shown. This creates a more compact structure, but still has an embedded collector of 10 transistors.
105 and an independent contact 104 to the buried base 72a of transistor 101. Is the metal region 106 also the base region of the transistor 101? Can be used as an independent contact to 2a. FIG. 4C shows the transistor 100 of FIGS. 4A to 4B.
Two vertical transistors 100a-b similar to are interconnected so that the collector (or emitter) of transistor 100b is
Figure 2 shows yet another embodiment of the invention internally connected to the base of 0a. This arrangement may be used, for example, to make Darlington circuits; since the l contacts serve to make internal connections, there is a net space saving compared to making the same connections on the top surface. The left portion of FIG. 4C shows how the means and methods of the present invention create buried multilayer connections that are formed simultaneously with sidewall contacts. Portions 113 and 114 of metal layer 110 include polycrystalline region 63a and polycrystalline pillars 73 and 1
07 and are interconnected by polycrystalline regions 115a-c formed simultaneously. Buried interconnect portions 116 are made at the same time as polycrystalline region 65a, and surface interconnect portions 111 are made at the same time as metal layer 110. Therefore, device 10
At the same time that 0a-b is fabricated, three levels of interconnects (115a
-c, 116, and 111) are obtained. This demonstrates the great flexibility and power of the means and methods of the present invention. Having described the present invention above, the present invention provides common self-separated (s) on a semiconductor substrate of
It is clear that the present invention provides a means and method for fabricating elf-isolated devices. Separate separating walls are unnecessary. The method described is particularly suitable for use in high density integrated circuits. Multilayer interconnects are obtained without additional process steps. Although the means and methods of the present invention have been described with respect to specific combinations of conductivity and device type, these are intended to be illustrative only; Those skilled in the art will appreciate that other combinations of shapes and other arrangements of PN junctions and lateral contacts may also be used. It is therefore intended that all such modifications be included within the scope of the claims. Embodiments of the present invention will be shown below. 1. A method according to claim 1, wherein said step of filling said first and second openings is carried out automatically (
process).

[Brief explanation of drawings]

1A-1C show simplified schematic side and top cross-sectional views of a portion of a semiconductor device according to the prior art. 2A-2 show simplified schematic and top sectional views of a portion of a semiconductor device according to the invention. 3A-3J show simplified schematic cross-sectional views of a portion of a semiconductor device according to the invention at various stages of manufacture. 4A-4C depict simplified schematic cross-sectional views of various semiconductor devices and interconnects according to another embodiment of the present invention. Patent Applicant Motorola Incorporated Agent
Patent Attorney Tama Mushi Hisa Gobe FIG, IB FIG, 2D FIG, 5U) 1 (>, 5L) FIG, 31) IG, 3J F, G-4B72a 72a 63aFIG,
4C

Claims (1)

[Claims] 1. A step of providing a single crystal substrate; a step of providing above the substrate a first conductor region electrically insulated from the substrate; and a step of providing a first conductor region electrically isolated from the substrate and the first conductor region. providing above the substrate a second conductor region having a first portion overlapping the first portion of the first conductor region; and at least a portion of the first portion of the first and second conductor regions. creating a first opening extending through the substrate to reach the substrate; creating a second opening laterally separated from the second conductor region and penetrating to the first conductor region; filling a portion of the first opening with a single-crystalline semiconductor material that contacts the first and second conductor regions in the first opening; filling a portion of an opening; forming a device in the single crystal material within the first opening; and making electrical connections to the single crystal semiconductor material, the second conductor region and the polycrystalline material. A method of making a semiconductor device, comprising: a step of making a semiconductor device. 2. A single crystal substrate, having a lower surface resting on the substrate, an upper surface remote from the substrate, and a side wall between the lower surface and the upper surface, the side wall extending laterally through the column. a pillar of monocrystalline semiconductor material having a collector and base region extending to the substrate; and an extension electrically insulated from the substrate and contacting the collector region of the pillar on the sidewall to a top surface of the device. a first polycrystalline conductor region; a second polycrystalline region electrically insulated from the substrate and the first polycrystalline conductor region and in contact with the base region of the pillar on the sidewall; 2 a first opening located above the polycrystalline conductor region and extending to a peripheral portion of the upper surface of the pillar and above a central portion of the upper surface of the pillar;
a dielectric region having a second opening above the extended portion of the polycrystalline conductor region; and an electrical connection between the central portion and the extended portion of the first polycrystalline conductor region and the second polycrystalline conductor region. A sidewall contact semiconductor device having a contact.