JPS63252455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63252455A JPS63252455A JP8826687A JP8826687A JPS63252455A JP S63252455 A JPS63252455 A JP S63252455A JP 8826687 A JP8826687 A JP 8826687A JP 8826687 A JP8826687 A JP 8826687A JP S63252455 A JPS63252455 A JP S63252455A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- island
- package
- pellet
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000008188 pellet Substances 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 238000005336 cracking Methods 0.000 abstract description 14
- 230000008646 thermal stress Effects 0.000 abstract description 8
- 238000005452 bending Methods 0.000 abstract description 3
- 238000000465 moulding Methods 0.000 abstract description 3
- 239000012141 concentrate Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にフラット型モールド樹
脂パッケージ構造を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a flat molded resin package structure.
従来、この種の半導体装置はリードフレームのアイラン
ドに半導体ペレットを搭載しパッケージを形成する際、
熱ストレスによるパッケージ割れが問題になるので、こ
のパッケージ割れ防止対策としてパッケージの原型化、
リードフレームのファイン化、ペレットサイズの縮少化
およびモールド樹脂の材質等に着目し対処していた。Conventionally, in this type of semiconductor device, when forming a package by mounting a semiconductor pellet on an island of a lead frame,
Package cracking due to heat stress is a problem, so as a measure to prevent package cracking, it is necessary to create a prototype of the package.
The focus was on improving lead frames, reducing pellet size, and molding resin materials.
上述した従来の半導体装置は同一パッケージに大きさの
異なるペレットをそれぞれ封入した場合、熱ストレスに
よるパッケージ割れの程度はペレットの大きさで異なっ
ている。しかしながら、ペレットの大きさがある大きさ
以上になると従来の技術ではパッケージ割れを防止でき
なくなるという欠点がある。また、パッケージ割れが発
生することにより、耐湿性においてポンディングパッド
のコロ−ジョン等の問題も発生するという欠点がある。In the conventional semiconductor device described above, when pellets of different sizes are enclosed in the same package, the degree of package cracking due to thermal stress differs depending on the size of the pellets. However, when the size of the pellet exceeds a certain size, the conventional technology has the disadvantage that it is no longer possible to prevent the package from cracking. Furthermore, due to the occurrence of package cracking, problems such as corrosion of the bonding pad may occur in terms of moisture resistance.
本発明の目・的はかかるパッケージ割れなどを防止する
半導体装置を゛提供することにある。An object of the present invention is to provide a semiconductor device that prevents such package cracking.
本発明はフラット型モールド樹脂パッケージ楕造を有す
る半導体装置において、ペレットを搭載するアイランド
部の周辺の少なくとも一部に曲げ部もしくは丸み部を形
成して構成されている。The present invention is a semiconductor device having an oval shape of a flat molded resin package, in which a bent portion or a rounded portion is formed in at least a portion of the periphery of an island portion on which a pellet is mounted.
次に、本発明の実施例についで図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第一の実施例を説明するための半導体
装置の縦断面図である。FIG. 1 is a longitudinal sectional view of a semiconductor device for explaining a first embodiment of the present invention.
第１図に示すように、かかる半導体装置はリードフレー
ムのアイランド５の両側にともに内側に折り曲げられた
曲げ部６を形成しており、このアイランド５上に半導体
ペレット４をマウントする。次に、このペレット４の電
極とリードフレームのリード部２とをボンディングワイ
ヤ３により接続し、しかる後、ワイヤ３の保護とペレッ
ト４の保護を兼ねてモールド樹脂１により樹脂封止し半
導体装置として形成する。かかる半導体装置において、
熱ストレスによるパッケージ割れは熱ストレスが一個所
に集中するために発生すると考えられるので、本実施例
では熟ストレスを一個所に集中しないように配慮したも
のである。As shown in FIG. 1, such a semiconductor device has bent portions 6 bent inwardly on both sides of an island 5 of a lead frame, and a semiconductor pellet 4 is mounted on this island 5. Next, the electrode of this pellet 4 and the lead part 2 of the lead frame are connected with a bonding wire 3, and then the semiconductor device is sealed with a molding resin 1 to protect the wire 3 and the pellet 4. Form. In such a semiconductor device,
It is thought that package cracking due to thermal stress occurs because the thermal stress is concentrated in one place, so in this embodiment, care was taken to prevent the aging stress from being concentrated in one place.
第２図は第１図に示すアイランド部の拡大斜視図である
。2 is an enlarged perspective view of the island portion shown in FIG. 1. FIG.
第２図に示すように、ペレットを搭載するアイランド部
５の両側（長辺側）に曲げ部６を形成し熱ストレスの一
個所集中を避けている。As shown in FIG. 2, bent portions 6 are formed on both sides (long side) of the island portion 5 on which the pellets are mounted to avoid concentration of thermal stress in one location.
このように、本実施例はペレット４の長辺側のリードフ
レームにおけるアイランド部５をペレット４側に曲げる
ことにより、熱ストレスが加わっても、その力を吸収も
しくは和らげ、パッケージ割れを防止することができる
。In this way, in this embodiment, by bending the island portion 5 of the lead frame on the long side of the pellet 4 toward the pellet 4 side, even if thermal stress is applied, the force can be absorbed or alleviated, and package cracking can be prevented. Can be done.
第３図は本発明の第二の実施例を説明するための半導体
装置の縦断面図である。FIG. 3 is a longitudinal sectional view of a semiconductor device for explaining a second embodiment of the present invention.
第３図に示すように、かかる半導体装置は、リードフレ
ームにおけるアイランド部５およびリード部２の角をな
くし、丸み部７を持たせたものである。その他は第一の
実施例と同様である。As shown in FIG. 3, in this semiconductor device, the island portion 5 and lead portion 2 of the lead frame have rounded portions 7 instead of corners. The rest is the same as the first embodiment.
前述のように、パッケージ割れは熱ストレスが一個所に
集中するために発生すると考えられるので、本発明は角
部による熱ストレス集中を避けたものである。すなわち
、この種のパッケージ割れは、リードフレーム（アイラ
ンド部）の長辺の角から発生することが多いため、リー
ドフレーム全体の角をなくし全てに丸みを持たせること
により前述の第一の実施例と同様の効果が得られる。As mentioned above, it is believed that package cracking occurs because thermal stress is concentrated in one place, so the present invention avoids the concentration of thermal stress at corners. In other words, this type of package cracking often occurs from the long side corners of the lead frame (island part), so by eliminating the corners of the entire lead frame and making it all rounded, The same effect can be obtained.
以上説明したように、本発明はリードフレームのアイラ
ンド部の周辺のすくなくとも一部に曲げ部もしくは丸み
部を形成することにより、パッケージ割れを防止できる
効果がある。As described above, the present invention has the effect of preventing package cracking by forming a bent portion or a rounded portion in at least a portion of the periphery of the island portion of the lead frame.
従って、かかるパッケージ割れの防止により耐湿性にお
いても向上した半導体装置を得られる効果がある。Therefore, by preventing such package cracking, it is possible to obtain a semiconductor device with improved moisture resistance.
第１図は本発明の第一の実施例を説明するための半導体
装置の縦断面図、第２図は第１図におけるアイランド部
の拡大斜視図、第３図は本発明の第二の実施例を説明す
るための半導体装置の縦断面図である。
１・・・モールド樹脂、２・・・リードフレーム（リー
ド部）、３・・・ボンディングワイヤー、４・・・ペレ
ット、５・・・リードフレーム（アイランド部）。
７オみ音Ｐ
第３ ワFIG. 1 is a vertical cross-sectional view of a semiconductor device for explaining a first embodiment of the present invention, FIG. 2 is an enlarged perspective view of the island portion in FIG. 1, and FIG. 3 is a second embodiment of the present invention. FIG. 2 is a longitudinal cross-sectional view of a semiconductor device for explaining an example. DESCRIPTION OF SYMBOLS 1... Mold resin, 2... Lead frame (lead part), 3... Bonding wire, 4... Pellet, 5... Lead frame (island part). 7 Omion P 3rd Wa
Claims (1)
体装置において、ペレットを搭載するアイランド部の周
辺のすくなくとも一部に曲げ部もしくは丸み部を形成し
たことを特徴とする半導体装置。1. A semiconductor device having a flat molded resin package structure, characterized in that a bent portion or a rounded portion is formed at least in part of the periphery of an island portion on which a pellet is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8826687A JPS63252455A (en) | 1987-04-09 | 1987-04-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8826687A JPS63252455A (en) | 1987-04-09 | 1987-04-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63252455A true JPS63252455A (en) | 1988-10-19 |
Family
ID=13938087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8826687A Pending JPS63252455A (en) | 1987-04-09 | 1987-04-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63252455A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02114694A (en) * | 1988-10-25 | 1990-04-26 | Mitsubishi Electric Corp | Manufacture of circuit board |
| US5358905A (en) * | 1993-04-02 | 1994-10-25 | Texas Instruments Incorporated | Semiconductor device having die pad locking to substantially reduce package cracking |
| KR100304922B1 (en) * | 1998-12-29 | 2001-11-02 | 마이클 디. 오브라이언 | Lead frame and semiconductor package with such lead frame |
-
1987
- 1987-04-09 JP JP8826687A patent/JPS63252455A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02114694A (en) * | 1988-10-25 | 1990-04-26 | Mitsubishi Electric Corp | Manufacture of circuit board |
| US5358905A (en) * | 1993-04-02 | 1994-10-25 | Texas Instruments Incorporated | Semiconductor device having die pad locking to substantially reduce package cracking |
| KR100304922B1 (en) * | 1998-12-29 | 2001-11-02 | 마이클 디. 오브라이언 | Lead frame and semiconductor package with such lead frame |
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