JPS6079733A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6079733A JPS6079733A JP58186713A JP18671383A JPS6079733A JP S6079733 A JPS6079733 A JP S6079733A JP 58186713 A JP58186713 A JP 58186713A JP 18671383 A JP18671383 A JP 18671383A JP S6079733 A JPS6079733 A JP S6079733A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- pellet
- semiconductor device
- lead terminals
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、半導体装置の信頼性向上、特にペレットをワ
イヤボンディングにて外部端子と電気的に接続してなる
半導体装置に適用して有効な技術に関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when applied to improving the reliability of semiconductor devices, particularly to semiconductor devices in which pellets are electrically connected to external terminals by wire bonding. It is.
［背景技術］
ペレットの周囲に配列された外部リード端子と該ペレッ
ト上のポンディングパッド（以下バンドともいう。）と
をワイヤボンディングすることにより、電気的に接続さ
れている半導体装置においては、半導体装置の高集積化
が進むに伴いワイヤボンディングが難しくなってくる。[Background Art] In a semiconductor device in which external lead terminals arranged around a pellet and bonding pads (hereinafter also referred to as bands) on the pellet are electrically connected by wire bonding, the semiconductor As devices become more highly integrated, wire bonding becomes more difficult.
−その理由の１つに、隣接するバンドにその一端がボン
ディングされているワイヤどうしが、空間的に近接した
配置になるため、互いに接触し、ワイヤ間でショートを
起こし易くなることが角えられる。- One of the reasons for this is that wires whose ends are bonded to adjacent bands are placed spatially close to each other, making it easier for them to come into contact with each other and cause a short circuit between the wires. .
特に、ペレット上に配列されたパッドの中の２個以上を
、該バンドの配列（ペレットの一辺）と略直行する方向
に延在されているリード端子とワイヤボンディングして
なる構造を有する半導体装置の場合は、ワイヤとパッド
との接触、ワイヤ相互の交差による接触等の問題がある
ことを、本発明者は見い出した。In particular, a semiconductor device having a structure in which two or more of the pads arranged on a pellet are wire-bonded to a lead terminal extending in a direction substantially perpendicular to the arrangement of the bands (one side of the pellet). In this case, the inventors have found that there are problems such as contact between wires and pads, and contact due to mutual crossing of wires.
［発明の目的］
本発明の目的は、半導体装置の信頼性向上に通用して有
効な技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a technique that is generally applicable and effective for improving the reliability of semiconductor devices.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ベレット上のポンディングパッドのうち２以
上を、該ポンディングパッドの配列と略直行する方向に
延在されたリード端子とワイヤボンディングしてなる半
導体装置において、各ワイヤの間隔が広がるような配置
でボンディングすることにより、ワイヤどうしの接触を
防止し、半導体装置の信頼性の向上を達成するものであ
る。That is, in a semiconductor device in which two or more of the bonding pads on the pellet are wire-bonded to lead terminals extending in a direction substantially perpendicular to the arrangement of the bonding pads, the distance between each wire is widened. By bonding the wires in a specific manner, contact between the wires can be prevented and reliability of the semiconductor device can be improved.
［実施例１］
第１図は、本発明の一実施例である半導体装置の概略断
面図である。[Example 1] FIG. 1 is a schematic cross-sectional view of a semiconductor device that is an example of the present invention.
本実施例１に示す半導体装置は樹脂封止型半導体装置で
あって、リードフレームのタブ２上に金−長すコン共晶
等のろう材３で取り付けられたベレット４、および該ベ
レット４上のポンディングパッド５とリードフレームの
リード端子６とを電気的に接続するためにボンディング
しているワイヤ７を、樹脂８でモールドした後リードフ
レームを折り曲げ成形することにより得られるものであ
る。The semiconductor device shown in Example 1 is a resin-sealed semiconductor device, and includes a pellet 4 attached to a tab 2 of a lead frame with a brazing material 3 such as gold-converter eutectic, and a pellet 4 mounted on the tab 2 of a lead frame. The bonding pad 5 and the lead terminal 6 of the lead frame are molded with a resin 8, and then the lead frame is bent and formed.
第２図は、本実施例１である半導体装置におけるワイヤ
７のボンディングの状態を、樹脂モールド前におけるタ
ブ吊りリード９で支持されたタブ２上に取り付けられた
ベレットの一部を拡大平面図で示し゛たものである。FIG. 2 is an enlarged plan view of a part of the pellet attached to the tab 2 supported by the tab suspension lead 9 before resin molding, showing the bonding state of the wire 7 in the semiconductor device of Example 1. This is what was shown.
前記の拡大平面図に示すワイヤのボンディング状態は、
ペレット上にベレットの一辺に略平行に配列形成された
ポンディングパッド５ａ、５ｂ、５Ｃ１５ｅ並びに該配
列と略平行に対向して配列されたリード端子６ａ、６ｂ
、６Ｃおよび前記ポンディングパッド５ａ〜５ｅの配列
に平行なベレットの一辺に隣接する他の一辺に直交する
方向、ずなわち該配列と略直角方向に配列されたリード
端子５ｄ、５ｅの組合せにおいて、５ａ、５ｂおよび５
Ｃについては、略平行に配列されたリード端子５ａ、５
ｂおよび６Ｃの順にボンディングし、５ｄおよび５ｅに
ついては、略直角方向に配列したリード端子と、それぞ
れ６ｅおよび６ｄの順にボンディングしたものである。The bonding state of the wires shown in the enlarged plan view is as follows:
Bonding pads 5a, 5b, 5C15e formed on the pellet in an array substantially parallel to one side of the pellet, and lead terminals 6a, 6b arranged substantially parallel to and opposite the array.
, 6C and the lead terminals 5d and 5e arranged in a direction perpendicular to the other side adjacent to one side of the bullet parallel to the arrangement of the bonding pads 5a to 5e, that is, in a direction substantially perpendicular to the arrangement. , 5a, 5b and 5
Regarding C, lead terminals 5a, 5 arranged substantially in parallel
Bonding was performed in the order of b and 6C, and 5d and 5e were bonded with the lead terminals arranged approximately at right angles in the order of 6e and 6d, respectively.
本実施例１に示すようなパッドとリード端子の配置であ
る半導体装置において、パッドとリード端子のボンディ
ングを各々対応するワイヤどうしで行うと、５ｄ−６ｄ
のワイヤおよび５ｃｍ５ｅのワイヤが互いに接近または
交差して接触し易くなる。In a semiconductor device in which the pads and lead terminals are arranged as shown in Example 1, if the bonding between the pads and lead terminals is performed using the corresponding wires, the bonding will be 5d-6d.
wires and wires of 5cm5e approach each other or cross each other, making it easier for them to contact each other.
しかし、第２図に示す前記のボンディングを行うことに
より、パッド５ｄおよび５ｅにその一端がボンディング
されたワイヤ７ｄおよび７ｅは相互の間隔が広くなるよ
うにリード端子とボンディングされているのでワイヤと
パッドまたはワイヤどうしの接触によるショートを避け
ることができる。However, by performing the bonding shown in FIG. 2, the wires 7d and 7e whose one ends are bonded to the pads 5d and 5e are bonded to the lead terminals such that the distance between them is widened, so that the wires and the pads Alternatively, short circuits due to contact between wires can be avoided.
なお、本発明を適用する場合、たとえば第２図に示すワ
イヤ７ｄのように長い距離をワイヤでつなく必要が生じ
た場合は、タブの位置を下げることにより、該ワイヤと
ベレットとの接触をより有効に防止できるので、さらに
信頼性の高い半導体装置とすることができる。In addition, when applying the present invention, if it becomes necessary to connect a long distance with a wire, such as the wire 7d shown in FIG. 2, the contact between the wire and the pellet can be prevented by lowering the position of the tab. Since this can be prevented more effectively, it is possible to provide a semiconductor device with even higher reliability.
［実施例２］
第３図は、実施例１と同様な半導体装置についての本発
明の実施例を、第２図と同様な状態図で示したものであ
る。[Example 2] FIG. 3 shows an example of the present invention regarding a semiconductor device similar to that of Example 1, using a state diagram similar to that of FIG. 2.
本実施例２による半導体装置のワイヤボンディングの状
態は、パッド５ａ、５ｂおよび５ｄは略平行に配列され
たリード端子６ａ、６ｂおよび６Ｃに順にボンディング
され、残っている２つのパッド５Ｃおよび５ｅが、バン
ドの配列とほぼ直角方向に配列されたリード端子とボン
ディングされている。そのワイヤは、パッド５ｄが離れ
ている方のリード端子６ｅと、パッド５ｅが近接する方
のリード端子６ｄとボンディングされた配置になってい
る。In the wire bonding state of the semiconductor device according to the second embodiment, pads 5a, 5b, and 5d are bonded in order to lead terminals 6a, 6b, and 6C arranged approximately in parallel, and the remaining two pads 5C and 5e are It is bonded to lead terminals arranged approximately perpendicular to the band arrangement. The wire is bonded to a lead terminal 6e that is farther from the pad 5d and a lead terminal 6d that is closer to the pad 5e.
このようなボンディング方法を採用することにより、実
施例１と同様にパッド５ｃ、５ｄおよび５ｅのそれぞれ
にその一端がボンディングされているワイヤ７ｃ、７ｄ
および７ｅは、互いに大きく間隔をおいて配置すること
ができる。By employing such a bonding method, wires 7c, 7d whose one ends are bonded to pads 5c, 5d, and 5e, respectively, as in the first embodiment.
and 7e may be widely spaced from each other.
［実施例３］
第４図は、本発明の実施例３による半導体装置について
、ペレットのワイヤボンディングの状態を、その一部の
拡大平面図で示したものである。[Example 3] FIG. 4 is an enlarged plan view of a portion of a semiconductor device according to Example 3 of the present invention, showing the state of wire bonding of a pellet.
本実施例３は、前記実施例１および２と同様の樹脂封止
型半導体装置について、配列されたパッド５のうち３つ
のパッドを該配列と略直角方向に形成されたリード端子
とボンディングした半導体装置であって、本発明を適用
した一例を示すものである。Example 3 is a resin-sealed semiconductor device similar to Examples 1 and 2, in which three pads among the arranged pads 5 are bonded to lead terminals formed in a direction substantially perpendicular to the arrangement. This is a device showing an example to which the present invention is applied.
本実施例３の半導体装置におけるワイヤボンディングの
状態は、配列形成されたパッド５ａ〜５ｆのうち５ａ〜
５ｃを該配列と略平行に配列されたリード端子６ａ〜６
ｃに順次ボンディングし、残ったベレット端部に近い５
ｄ〜５ｆの３つのパッドを、該配列と略直角方向に配列
したリード端子と離れている方から順次５ｄと６ｆ、５
ｄと６ｅおよび５ｆと６ｄの如くボンディングしたもの
である。The state of wire bonding in the semiconductor device of Example 3 is as follows: 5a to 5f of the arranged pads 5a to 5f.
5c and lead terminals 6a to 6 arranged substantially parallel to the arrangement.
Bonding is performed sequentially to c, and 5 near the remaining end of the pellet is bonded.
The three pads d to 5f are arranged in the order of 5d, 6f, and 5 from the lead terminals arranged in a direction substantially perpendicular to the arrangement.
d and 6e and 5f and 6d are bonded.
本実施例３のように、略直角方向に配列されたリード端
子に、パ・ノド５ｄ、５ｅおよび５ｆにその一端がボン
ディングされたワイヤ７ｄ、７ｅおよび７ｆを引き出す
場合、同一接尾記号のワイヤどうしの組合せになるよう
に順次ボンディングした場合ば、ワイヤ７ｄはパッド５
ｅおよび５ｆに非常に接近し、ワイヤ７ｅと７１は完全
に交差した状態になるが、本発明を適用することにより
、第４図に示すような各ワイヤ間の距離を十分に保持し
た配置とすることができる。As in the third embodiment, when drawing out the wires 7d, 7e and 7f whose ends are bonded to the pad nodes 5d, 5e and 5f from the lead terminals arranged in a substantially perpendicular direction, the wires with the same suffix symbol If bonding is performed sequentially so that the combination of
wires 7e and 5f are very close to each other, and wires 7e and 71 completely cross each other. However, by applying the present invention, it is possible to create an arrangement that maintains a sufficient distance between each wire as shown in FIG. can do.
［効果コ
（１）、複数個が略列状に配列形成されたポンディング
パッドのうち２以上を、該パッドの配列と略直角方向に
配列されたリード端子とワイヤボンディングしてなる半
導体装置について、各ワイヤの間隔が広くなるようにボ
ンディングすることにより、ワイヤどうしの接触等を防
止することができるので、半導体装置の信頼性を向上さ
せることができる。[Effect (1) Regarding a semiconductor device formed by wire bonding two or more of a plurality of bonding pads arranged in a substantially row shape to lead terminals arranged in a direction substantially perpendicular to the arrangement of the pads. By bonding the wires so that the distance between the wires is wide, it is possible to prevent the wires from coming into contact with each other, thereby improving the reliability of the semiconductor device.
（２）、前記＋１１のワイヤボンディングを、リード端
子の配列側のペレット端部に近いポンディングパッドで
行うことにより、ワイヤの使用量を少なくすることがで
きる。(2) By performing the +11 wire bonding at a bonding pad near the end of the pellet on the side where the lead terminals are arranged, the amount of wire used can be reduced.
（３）０本発明を適用する半導体装置のペレット取り付
は部の位置を低くすることにより、さらに信頼性を向上
させることができる。(3) The reliability of the pellet mounting of the semiconductor device to which the present invention is applied can be further improved by lowering the position of the part.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、ポンディングパッドの数は、図に示したもの
に限るものでなく、さらに多パッド製品に適用して極め
て有効な技術である。For example, the number of bonding pads is not limited to what is shown in the figure, and this technique is extremely effective when applied to multi-pad products.
本発明は、そのポンディングパッドが四辺形であるペレ
ットの相対向する二辺にのみ配置された半導体装置、特
に半導体記憶装置に用いて大きな効果がある。すなわち
、ＤＲＡＭ、ＳＲＡＭ、ＲＯＭ等の半導体記憶装置にお
ム（ては、ボンディングバンドはペレットのｉつの短辺
にのみ配置され、一方、何本かの短リード端子はペレッ
トのポンディングパッドのない二辺に対向するように設
けざるを得ないので、本発明は特に有効である。The present invention has great effects when used in semiconductor devices, particularly semiconductor memory devices, in which bonding pads are arranged only on two opposing sides of a quadrilateral pellet. In other words, in semiconductor storage devices such as DRAM, SRAM, and ROM, bonding bands are placed only on the i short sides of the pellet, while some short lead terminals are placed on the short sides of the pellet without bonding pads. The present invention is particularly effective since the two sides have no choice but to be provided opposite each other.
［利用分野］
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である樹脂封止型半導体装
置に適用した場合について説明したが、それに限定され
るものではなく、たとえば、セラミックパッケージから
なる半導体装置であっても、サーディプタイプ等のワイ
ヤボンディングで電気的な接続を行っている半導体装置
に適用して有効な技術である。[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a resin-sealed semiconductor device, which is the field of application that formed the background of the invention, but the invention is not limited to this, and for example, This technique is effective when applied to semiconductor devices that are electrically connected by wire bonding, such as a cerdip type, even if the semiconductor device is made of a ceramic package.
第１図は、本発明を適用した半導体装置の一例を示す断
面図、
第２図は、本発明の実施例１である半導体装置のワイヤ
ボンディングの状態を示す部分拡大平面図、
第３図は、本発明の実施例２である半導体装置のワイヤ
ボンディングの状態を示す部分拡大平面図、
第４図は、本発明の実施例３による半導体装置のワイヤ
ボンディングの状態を示す部分拡大平面図である。
２・・・タブ、３・・・ろう材、４・・・ペレット、５
．５ａ〜５ｆ・・・ポンディングパッド、６．６ａ 〜
６ｆ −−−リード端子、７．７ｃ〜７ｆ・・・ワイヤ
、８・・・樹脂、９・・・タブ吊りリード。
、−′）
代理人 弁理士 高 橋 晶”＜−大
箱１図
第 ２ 図
第 ３ 図
第 ／ｉ 図FIG. 1 is a cross-sectional view showing an example of a semiconductor device to which the present invention is applied; FIG. 2 is a partially enlarged plan view showing a state of wire bonding of a semiconductor device according to Embodiment 1 of the present invention; FIG. FIG. 4 is a partially enlarged plan view showing the state of wire bonding of a semiconductor device according to Embodiment 3 of the present invention. FIG. . 2... Tab, 3... Brazing metal, 4... Pellet, 5
．． 5a-5f...ponding pad, 6.6a-
6f --- Lead terminal, 7.7c to 7f... Wire, 8... Resin, 9... Tab hanging lead. , -') Agent Patent Attorney Akira Takahashi"<- Large Box Figure 1 Figure 2 Figure 3 Figure /i Figure
Claims (1)
、該ポンディングパッドの配列と略平行および略直角方
向の２方向のペレット周囲に配列されたリード端子とワ
イヤボンディングしてなる半導体装置において、２以上
のポンディングバンドが略直角方向に配列されたリード
端子と、各ワイヤの間隔が広くなるようにワイヤボンデ
ィングされていることを特徴とする半導体装置。 ２、略直角方向に配列されたリード端子とワイヤボンデ
ィングされるポンディングパッドが、８亥リード端子の
配列側のペレット端部に近いポンディングバンドである
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。[Claims] 1. Bonding pads formed in an array on the pellet are wire-bonded to lead terminals arranged around the pellet in two directions, substantially parallel and substantially perpendicular to the arrangement of the bonding pads. 1. A semiconductor device characterized in that two or more bonding bands are wire-bonded to a lead terminal in which two or more bonding bands are arranged substantially perpendicularly so that the intervals between the wires are wide. 2. Claim 1, characterized in that the bonding pad that is wire-bonded to the lead terminals arranged in a substantially perpendicular direction is a bonding band close to the end of the pellet on the arrangement side of the 8-lead terminals. 1. Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58186713A JPS6079733A (en) | 1983-10-07 | 1983-10-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58186713A JPS6079733A (en) | 1983-10-07 | 1983-10-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6079733A true JPS6079733A (en) | 1985-05-07 |
Family
ID=16193333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58186713A Pending JPS6079733A (en) | 1983-10-07 | 1983-10-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6079733A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473514A (en) * | 1990-12-20 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
-
1983
- 1983-10-07 JP JP58186713A patent/JPS6079733A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473514A (en) * | 1990-12-20 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5613295A (en) * | 1990-12-20 | 1997-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board and method for manufacturing same |
| US5646830A (en) * | 1990-12-20 | 1997-07-08 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5715147A (en) * | 1990-12-20 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0174341B1 (en) | Personalized area leadframe coining or half etching for deduced mecress at device edge | |
| US6121690A (en) | Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge | |
| JP2007180077A (en) | Semiconductor device | |
| JPS6079733A (en) | Semiconductor device | |
| JPS6010651A (en) | Semiconductor device | |
| JPH061801B2 (en) | Lead frame | |
| JPH0629429A (en) | Semiconductor device | |
| JPS6230496B2 (en) | ||
| JP2879787B2 (en) | Semiconductor package for high density surface mounting and semiconductor mounting substrate | |
| KR19990034731A (en) | Lead-on chip lead frames and packages using them | |
| JPS62122253A (en) | Semiconductor device | |
| JP2941479B2 (en) | Semiconductor device | |
| JPS63160262A (en) | Lead frame and semiconductor device using the same | |
| JP2002100719A (en) | Resin-sealed semiconductor device | |
| JPS61269349A (en) | Lead frame | |
| JP2871984B2 (en) | Semiconductor device | |
| JP3052633B2 (en) | Semiconductor device | |
| JPS63126257A (en) | Semiconductor device | |
| JPH01206652A (en) | Semiconductor device | |
| JPS60226152A (en) | Lead frame | |
| JPH0669411A (en) | Semiconductor device | |
| JPH04287356A (en) | Semiconductor integrated circuit device | |
| KR20000035352A (en) | Lead frame for semiconductor device and semiconductor device using the same | |
| JPH01270256A (en) | Semiconductor device | |
| JPH07176678A (en) | Lead frame for semiconductor device |