JPS6298651A - Plastic package - Google Patents

Plastic package

Info

Publication number
JPS6298651A
JPS6298651A JP60238655A JP23865585A JPS6298651A JP S6298651 A JPS6298651 A JP S6298651A JP 60238655 A JP60238655 A JP 60238655A JP 23865585 A JP23865585 A JP 23865585A JP S6298651 A JPS6298651 A JP S6298651A
Authority
JP
Japan
Prior art keywords
semiconductor chip
die pad
wall
surrounded
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60238655A
Other languages
Japanese (ja)
Inventor
Tatsuo Yamada
山田　達雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60238655A priority Critical patent/JPS6298651A/en
Publication of JPS6298651A publication Critical patent/JPS6298651A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To absorb stress from a molding resin by the outer wall of a die pad, and to prevent the generation of cracks in an inactive film for a semiconductor chip and the deformation of a metallic wiring section by surrounding the outer circumferential section of the semiconductor chip by the outer wall of the die pad. CONSTITUTION:A die pad 7 is formed by a bottom plate 7a, on an upper surface thereof a semiconductor chip 2 is fixed, and an outer wall 7c surrounding the outer circumferential section of the semiconductor chip 2, interposing a groove 7b. Consequently, since the outer circumferential section of the semiconductor chip 2 is surrounded by the outer wall 7c of the die pad 7, stress in the horizontal direction mainly applied from a molding resin 6 is absorbed, thus reducing stress applied to the semiconductor chip. The die pad 7 having a shape that the whole periphery of the semiconductor chip 2 is surrounded is represented, but the same effect can be acquired even when only the four corners of the semiconductor chip 2 are surrounded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はダイパット上に固着された半導体チップの外
周部を樹脂により一体にモールドする半導体装置のプラ
スチックパッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a plastic package for a semiconductor device in which the outer periphery of a semiconductor chip fixed on a die pad is integrally molded with resin.

〔従来の技術」 第３図〜第５図はプラスチックパッケージの従来例を示
すもので２図において、（１）はプラスチックパッケー
ジ、（２）〜（６）はプラスチックパッケージの構成部
分を示し、（２）は半導体チップ、（３）は半導体チッ
プ（２）を固着するダイパット、（４）は外部に引出さ
れるリードフレーム、（５）は半導体チップ（２）とリ
ードフレーム（４）とを接続する金等で形成された接続
ｓ、　＋６１はこれら半導体チップ（２）、ダイパット
（３）、リードフレーム（４）、接続線（５）等を一体
にモールドするモールド樹脂でりる。[Prior Art] Figures 3 to 5 show conventional examples of plastic packages. In Figure 2, (1) shows the plastic package, (2) to (6) show the constituent parts of the plastic package, and ( 2) is a semiconductor chip, (3) is a die pad that fixes the semiconductor chip (2), (4) is a lead frame that is pulled out to the outside, and (5) is a connection between the semiconductor chip (2) and the lead frame (4). The connections s and +61 made of gold or the like are molded resin for integrally molding the semiconductor chip (2), die pad (3), lead frame (4), connection wire (5), etc.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上のように構成された従来のプラスチックパッケージ
（１１においては、第４図、第５図に示されるようにダ
イパット（３）上に固着された半導体チップにモールド
樹脂による応力が発生する。図において、　Ａ、　Ｂ、
　Ｃ，Ｄは半導体チップ（２）およびダイパット（３）
に発生する応力の分布を示し、いずれも端部の角部（２
ａ）（３ａ）を中心として応力が発生する。In the conventional plastic package (11) constructed as described above, stress is generated by the molding resin on the semiconductor chip fixed on the die pad (3) as shown in FIGS. 4 and 5. , A, B,
C and D are semiconductor chips (2) and die pads (3)
shows the distribution of stress generated at the corner of the end (2
a) Stress is generated around (3a).

その結果、半導体チップ（２）が変形し、半導体チップ
（２）の外周部をおおう図示しない不活性膜にクラツク
が発生したり２図示しないアルミニウム等の金属配線部
分が変形するなどの問題点がめった。As a result, the semiconductor chip (2) is deformed, causing problems such as cracks occurring in the inert film (not shown) covering the outer periphery of the semiconductor chip (2), and deformation of metal wiring parts (not shown) such as aluminum. Rarely.

この発明は２以上のような問題点を解決するためになさ
れたもので、モールド樹脂によ）半導体チップにかかる
応力を減少させるようにしたプラスチックパッケージを
提供するものである。The present invention was made to solve two or more problems, and provides a plastic package that reduces stress applied to a semiconductor chip (due to molding resin).

〔問題点を解決するための手段〕[Means for solving problems]

この発明によるプラスチックパッケージは、半導体チッ
プの外周部をグイバットの外壁により囲むよう形成した
ものでりる。The plastic package according to the present invention is formed so that the outer periphery of a semiconductor chip is surrounded by an outer wall of a rubber band.

〔作用〕[Effect]

モールド樹脂からの応力をダイパットの外壁で吸収する
ことにより半導体チップにかかる応力は減少する。By absorbing the stress from the molding resin at the outer wall of the die pad, the stress applied to the semiconductor chip is reduced.

〔実施例〕〔Example〕

以下、この発明の一実施例を第１図、第２図により説明
する。図において、第３図〜第５図と同一符号は同一ま
たは相当部分を示し、（７）は半導体チップ（２）を上
面に固着する底板（７ａ）と、半導体チップ（２）の外
周部を溝（７ｂ）を隔てて囲う外壁（７ｃ）とにより形
成したダイパットで、その他の部分については従来のも
のと同様である。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In the figure, the same reference numerals as in FIGS. 3 to 5 indicate the same or corresponding parts, and (7) indicates the bottom plate (7a) that fixes the semiconductor chip (2) to the upper surface and the outer peripheral part of the semiconductor chip (2). This die pad is formed by an outer wall (7c) separating and enclosing a groove (7b), and the other parts are the same as the conventional ones.

以上のように、半導体チップ（２）の外周部をグイバッ
ト（力の外壁（７ｃ）により囲うようにしたので。As described above, the outer periphery of the semiconductor chip (2) is surrounded by the outer wall (7c).

モールド樹脂（６）からかかる主に水平方向の応力が吸
収され、半導体チップにかかる応力を小さくすることが
できる。Mainly horizontal stress applied from the molding resin (6) is absorbed, and stress applied to the semiconductor chip can be reduced.

なお、第２図においては、半導体チップ（２）の周囲の
すべてを囲む形状のダイパット（７）を示したが。In addition, in FIG. 2, the die pad (7) is shown in a shape that surrounds the entire periphery of the semiconductor chip (2).

半導体チップ（２）の四隅だけを囲うようにしても。Even if only the four corners of the semiconductor chip (2) are enclosed.

同様の効果を得ることができる６゜ 〔発明の幼果Ｊ この発明は以上説明したように、半導体チップの外周部
をダイパットの外壁で囲むようにしたので、モールド樹
脂からの応力をダイパットの外壁で吸収することができ
、半導体チップの不活性膜のクラックの発生や、金属配
線部分の変形を防止することができ２品質の安定と向上
をはかることができるという効果かめる。Similar effects can be obtained.6゜[Young fruit of the invention J] As explained above, in this invention, the outer periphery of the semiconductor chip is surrounded by the outer wall of the die pad, so that the stress from the molding resin is absorbed by the outer wall of the die pad. It is possible to prevent cracks in the inert film of the semiconductor chip and deformation of the metal wiring portion, thereby stabilizing and improving quality.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図はこの発明の一実施例を示し。 第１図は要部の縦断面図、第２図は要部の斜視図。 第３図〜第５図は従来例を示し、第３図は縦断面図、第
４図はモールド樹脂による応力の発生状態を示す正面説
明図、第５図は同じく平面説明図でるる。 図において、同一符号は同一または相当部分を示し、（
２）は半導体チップ、（６）はモールド樹脂、（７）は
ダイパット、　（７ａ）は底板、　（７ｂ）は溝、　（
７ｃ）は外壁である。FIGS. 1 and 2 show an embodiment of the present invention. FIG. 1 is a longitudinal sectional view of the main part, and FIG. 2 is a perspective view of the main part. 3 to 5 show a conventional example, in which FIG. 3 is a longitudinal sectional view, FIG. 4 is a front explanatory view showing the state of stress generated by the mold resin, and FIG. 5 is a plan explanatory view. In the figures, the same reference numerals indicate the same or equivalent parts, (
2) is a semiconductor chip, (6) is a mold resin, (7) is a die pad, (7a) is a bottom plate, (7b) is a groove, (
7c) is the outer wall.

Claims (2)

【特許請求の範囲】[Claims] （１）ダイパット上に方形の半導体チップを固着し、外
周部を樹脂によりモールドするプラスチックパッケージ
において、上記ダイパットを半導体チップを固着する底
板と、半導体チップの外周部を囲う外壁とにより構成し
たことを特徴とするプラスチックパッケージ。(1) In a plastic package in which a rectangular semiconductor chip is fixed on a die pad and the outer periphery is molded with resin, the die pad is composed of a bottom plate to which the semiconductor chip is fixed and an outer wall surrounding the outer periphery of the semiconductor chip. Features a plastic package. （２）ダイパットの外壁を半導体チップの四隅を囲むよ
うに形成したことを特徴とする特許請求の範囲第１項に
記載のプラスチックパッケージ。(2) The plastic package according to claim 1, wherein the outer wall of the die pad is formed to surround the four corners of the semiconductor chip.
JP60238655A 1985-10-24 1985-10-24 Plastic package Pending JPS6298651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60238655A JPS6298651A (en) 1985-10-24 1985-10-24 Plastic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60238655A JPS6298651A (en) 1985-10-24 1985-10-24 Plastic package

Publications (1)

Publication Number Publication Date
JPS6298651A true JPS6298651A (en) 1987-05-08

Family

ID=17033355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60238655A Pending JPS6298651A (en) 1985-10-24 1985-10-24 Plastic package

Country Status (1)

Country Link
JP (1) JPS6298651A (en)

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