JPS63252082A - Video signal transmission circuit - Google Patents

Abstract

PURPOSE:To keep the output at a constant level by switching an output being noninverting and inverting amplification of an input video signal with a synchronizing signal and controlling a DC offset voltage level in response to the value adding the peak difference of synchronizing signals in the output at a reference value. CONSTITUTION:An input signal 11 is subjected to noninverting amplification 1 and amplified by a noninverting amplifier 3 and an inverse amplifier 4 separately. A synchronizing signal included in the output of the noninverting amplifier 3 is detected (9) and its peak value is subjected to sample-and-hold (SH) 13. The peak value from the inverse amplifier 4 is subjected to SH 12. The SH value 13 and a reference value Vref are synthesized (16), the difference from the SH value 12 is amplified (14), and given to a noninverting input of the inverse amplifier 4 via an LPF 10. Moreover, the noninverting and inverse amplifiers 3, 4 are switched by a switch 5 synchronously with the synchronizing signal 9 and its output is subjected to buffer amplification 6 and the result is outputted (17). Thus, the peak level of the horizontal synchronizing signal of the inverting and noninverting amplifiers is kept to 1VP-P.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a video signal transmission circuit, and in particular to a horizontal opening 1!11
The present invention relates to a video signal transmission circuit configured to alternately invert and output input video signals at signal timings.

Saramekatsu I In order to equalize the frequency modulated wave spectrum when transmitting television video signals using a frequency modulation method using microwaves, etc., or for the purpose of concealing pay TV, etc., the timing of the horizontal synchronization signal is also changed. In both cases, the polarity of the video signal is alternately inverted and transmitted.

Conventionally, a circuit as shown in FIG. 2 has been used for this purpose.

In FIG. 2, a video signal to be transmitted is input to an input terminal 11, and this signal is amplified by a non-inverting amplifier 1. The output thereof is input to the duplexer 2 and the sample-and-hold circuit 8, respectively, and at the same time, it is also input to the synchronization detection circuit 9. The synchronization detection circuit 9 extracts only the synchronization signal, and the sample and hold circuit 8 samples and holds the video signal at the timing of the synchronization signal. be done. This DC voltage is applied to the inverting input terminal of the non-inverting amplifier 1, thereby forming a negative feedback loop that keeps the DC component at the tip of the synchronization signal in the video signal constant, thereby forming a feedback compression type clamper circuit. That will happen.

On the other hand, the video signals separated by the demultiplexer 2 are amplified by the non-inverting amplifier 3 and the inverting amplifier 4, respectively, and the polarities are opposite to each other at both outputs J3. The switch 5 is a switch for selecting one of the two video signals with opposite polarities, and its switching cycle is controlled by the control circuit 7 using the 1111 signal which is the output of the 1rJJ detection circuit 9. It's about to be controlled.

By doing this, the buffer amplification f! From ii6,
A video signal whose polarity is inverted at the cycle of the horizontal synchronization signal is output. Figure 3 shows the output signal of this transmission circuit, and in this figure, the DC offset voltage of the inverted and non-inverted signals is the difference voltage V between the peak potentials of each synchronizing signal.
D (V), and this t voltage vO is 111 by applying a certain DC offlet voltage to the non-inverting amplifier 3 or the inverting amplifier 4.

Now, the output of amplifier 1 in Figure 2 goes to feedback compression? Although the DC voltage at the tip of the synchronizing signal is controlled to be constant by the clamper circuit, the offset voltage of the non-inverting amplifier 3 or the inverting amplifier 4 is newly added to the output of the buffer amplifier 6 mentioned above. Therefore, if the DC offset voltage of the non-inverting amplifier 3 or the inverting amplifier 4 is subject to fluctuations due to temperature changes, power supply voltage fluctuations, etc., this will directly lead to the above-mentioned fluctuations in the differential voltage VD.

In FIG. 3, the level of the video signal in the non-inversion section is IV
, -, even after the polarity conversion, the output will be at the same level as before the polarity conversion.

However, if VD fluctuates due to the above-mentioned reason, both an increase or a decrease in the differential voltage will result in an increase in the maximum voltage of the video signal after polarity conversion, resulting in a voltage exceeding 1vl).

This increase in the level of the video signal causes an increase in distortion characteristics and frequency characteristics, and when input to a frequency modulator, it causes a change in the maximum frequency deviation and an increase in the transmission spectrum. There are drawbacks.

OBJECTS OF THE INVENTION An object of the present invention is to provide a video signal transmission circuit that suppresses fluctuations such as increases in the video signal level and always maintains a constant level.

Structure of the Invention According to the present invention, first and second amplifiers non-invert and invert amplify an input video signal, respectively, and outputs of the first and second amplifiers are amplified by a synchronization signal included in the input video signal. and a switching means for alternately switching and outputting the first and second signals according to the timing of the first and second signals.
level holding means for detecting and holding the peak voltage levels of the synchronization signals of the outputs of the amplifiers; and signal generation means for generating an output signal of adding the difference between these two peak voltage levels and a predetermined reference voltage. The DC offset voltage level of one of the first and second amplifiers is set to II according to this addition output signal.
A video signal transmission circuit characterized in that it has a control means for controlling I is obtained.

1 Yutaka 1 The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

To describe only the parts that are different from the conventional example in FIG. (that is, the peak level of the synchronization signal) is sampled and held in the sample-and-hold circuit 13.

Another sample and hold circuit 12 samples and holds the peak level of the synchronizing signal included in the output of the inverting amplifier 4. After the output of one sample hold circuit 13 is added to the reference voltage V ref in the synthesizer 16,
The other sample hold circuit 1 in the differential amplifier 14
A calculation of the difference with the output of 2 is performed, and a difference signal is output.

This difference signal is inputted to the inverting side input terminal of the non-inverting amplifier 3 via the low-frequency converter 15, thereby forming a negative feedback type clamp circuit.

The output of the sample-and-hold circuit 12 is supplied to the non-inverting input terminal of the inverting amplifier 4 via the low-frequency two-channel filter 10, thereby forming a negative feedback loop.

Note that the control circuit 7 includes a synchronization detector 9 as in the conventional example shown in FIG.
The switch 5 is til-controlled based on the timing of the horizontal synchronizing signal detected from the horizontal synchronizing signal, and the other configuration is the same as that shown in FIG. 2, and the explanation thereof will be omitted.

Here, a DC voltage is generated at the output of the differential amplifier 14 by adding a reference voltage V ref to the peak voltage level difference VD between the synchronous signals of the non-inverting amplifier 3 and the inverting amplifier 4, This voltage controls the DC offset voltage of the non-inverting amplifier 3, so that the peak voltage level difference of the outputs of both amplifiers 3 and 4 is always equal to the reference voltage V rat. It is controlled.

On the other hand, the output voltage of the sample-and-hold circuit 12 is input to the non-inverting input terminal of the inverting amplifier 4 via the low-frequency transducer 10 and forming a negative feedback loop. By controlling the offset voltage, it becomes possible to keep the tip potential of the synchronizing signal of the inverting amplifier 4 constant.

By doing this, the output DC potential of the non-inverting and inverting amplifiers 3 and 40 can be kept at a constant @V ref while maintaining the output DC potential of the inverting amplifier 4 constant, so an extremely stable video signal can be transmitted. It becomes possible.

In the inverting amplifier 4, a feedback loop is formed to keep the DC offset voltage constant by the output of the low-frequency amplifier 10, which suppresses the DC potential of the video output 17 of the buffer amplifier 6 to a constant level. and this output 1
A clamp circuit may be provided at a stage subsequent to 7.

According to the present invention, it is possible to easily suppress the fluctuation of the DC component of the video signal caused by the offset fluctuation of the amplifier, so that the horizontal synchronization signals of the inverted and non-inverted video signals can be easily suppressed. Always keep the peak level difference at a constant value (1■)
This has the effect of maintaining p-p.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional technique, and FIG. 3 is an example of the output waveform of a video signal obtained by the blocks in FIGS. 1 and 2. Explanation of symbols of main parts 3...Non-inverting amplifier 4...Inverting amplifier 5...Switcher 9...Synchronization detector 12.13... ...Sample hold circuit 14...
...Differential amplifier 10.15...Low frequency two-channel wave generator 16...Synthesis fixed

Claims (1)

[Claims] first and second amplifiers that non-invert and invert amplify an input video signal, respectively; outputs of the first and second amplifiers are alternately switched according to the timing of a synchronization signal included in the input video signal; a video signal transmission circuit having a switching means for outputting, a level holding means for detecting and holding the peak voltage levels of the synchronizing signals output from the first and second amplifiers, and a level holding means for detecting and holding the peak voltage levels of the synchronizing signals output from the first and second amplifiers; a signal generating means for generating a sum output signal of the difference in voltage level and a predetermined reference voltage; and a control means for controlling a DC offset voltage level of one of the first and second amplifiers in accordance with the sum output signal. A video signal transmission circuit comprising: