JPH0462632B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video signal transmission circuit, and more particularly to a video signal transmission circuit configured to alternately invert and output an input video signal at the timing of a horizontal synchronization signal.

Prior Art In order to equalize the frequency modulated wave spectrum when a television video signal is transmitted using a frequency modulation method using microwaves, etc., or for the purpose of concealing pay television etc., the timing of the horizontal synchronizing signal is Therefore, the polarity of the video signal is alternately inverted and transmitted.

Conventionally, a circuit as shown in FIG. 2 has been used for this purpose.

In FIG. 2, a video signal to be transmitted is input to an input terminal 11, and this signal is amplified by a non-inverting amplifier 1. The output thereof is input to the duplexer 2 and sample hold circuit 8, respectively, and at the same time, it is also input to the period detection circuit 9. In this synchronization detection circuit 9, only the synchronization signal is extracted, and in the sample and hold circuit 8, the video signal is sampled and held at the timing of the synchronization signal, and this hold output is outputted as a DC voltage by passing through the low frequency converter 10. Ru. This DC voltage is applied to the inverting input terminal of the non-inverting amplifier 1, thereby forming a negative feedback loop that keeps the DC component at the tip of the synchronization signal in the video signal constant, and a feedback compression clamper circuit is activated. It will be configured.

On the other hand, the video signals separated by the splitter 2 are amplified by the non-inverting amplifier 3 and the inverting amplifier 4, respectively, and the polarities of both outputs are opposite to each other. Switcher 5
is a switch for selecting one of the two video signals whose polarities are opposite to each other, and the switching period is controlled by the control circuit 7 based on the synchronization signal output from the synchronization detection circuit 9. It's summery.

By doing this, the buffer amplifier 6 outputs a video signal whose polarity is inverted at the period of the horizontal synchronizing signal. Figure 3 shows the output signal of this transmission circuit, and in this figure, the DC offset voltage of the inverted and non-inverted signals is defined by the difference voltage VD (V) between the peak potentials of each synchronizing signal, This differential voltage VD is obtained by applying a certain DC offset voltage to the non-inverting amplifier 3 or the inverting amplifier 4.

Now, the output of the amplifier 1 in Fig. 2 is controlled by a feedback compression type clamper circuit so that the DC voltage at the tip of the synchronizing signal is constant, but the output of the buffer amplifier 6 mentioned above is non-inverted. Since the offset voltage of the amplifier 3 or the inverting amplifier 4 will be newly added, if the DC offset voltage of the non-inverting amplifier 3 or the inverting amplifier 4 is subject to fluctuations due to temperature changes, power supply voltage fluctuations, etc., the above-mentioned differential voltage will be applied as is. This will lead to fluctuations in VD.

In FIG. 3, when the video signal level in the non-inverted section is 1V _pp , even after polarity conversion, the output will be at the same level as before polarity conversion. However, if VD fluctuates due to the above-mentioned reason, both an increase or a decrease in the differential voltage will result in an increase in the maximum voltage of the video signal after polarity conversion, resulting in a voltage exceeding 1V _pp .

This increase in the level of the video signal causes an increase in distortion characteristics and frequency characteristics, and when input to a frequency modulator, it causes a change in the maximum frequency deviation and an increase in the transmission spectrum. There are drawbacks.

OBJECT OF THE INVENTION An object of the present invention is to provide a video signal transmission circuit that suppresses fluctuations such as increase in video signal level and always maintains a constant level.

Structure of the Invention According to the present invention, first and second amplifiers non-invert and invert amplify an input video signal, respectively, and the outputs of the first and second amplifiers are used as synchronization signals included in the input video signal. a video signal transmission circuit having a switching means that alternately switches and outputs the output according to the timing of the first and second amplifiers, wherein the peak voltage level of the synchronizing signal output from the first and second amplifiers is detected and maintained respectively; a holding means; a signal generating means for generating a summation output signal of the difference between these two peak voltage levels and a predetermined reference voltage; and a DC offset of one of the first and second amplifiers in accordance with the summation output means. A video signal transmission circuit characterized in that it has a control means for controlling a voltage level is obtained.

Examples Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
Parts equivalent to those in FIG. 2 are indicated by the same reference numerals.
To describe only the parts that are different from the conventional example in FIG. That is, the peak voltage level of the synchronizing signal) is sampled and held by the sample-and-hold circuit 13.

The other sample and hold circuit 12 is an inverting amplifier 4
The peak level of the synchronization signal included in the output of is sampled and held. The output of one of the sample and hold circuits 13 is applied to a reference voltage at a synthesizer 16.
After being added to Vref, the differential amplifier 14 calculates the difference between the output and the output of the other sample and hold circuit 12, and a difference signal is output.

This difference signal is input to the inverting side input terminal of the non-inverting amplifier 3 via the low frequency amplifier 15, thereby forming a negative feedback type clamp circuit.
The output of the sample and hold circuit 12 is the low frequency generator 1.
0 to the non-inverting input terminal of the inverting amplifier 4, thereby forming a negative conversion loop.

The control circuit 7 controls the switch 5 based on the timing of the horizontal synchronization signal detected from the synchronization detector 9, as in the conventional example shown in FIG. 2, and the other configurations are the same as that shown in FIG. Therefore, the explanation will be omitted.

Here, a DC voltage is generated at the output of the differential amplifier 14 by adding a reference voltage Vref to the peak voltage level difference VD between the synchronous signals of the non-inverting amplifier 3 and the inverting amplifier 4. Since the DC offset voltage of the non-inverting amplifier 3 is controlled by the voltage, the difference in peak voltage levels of the synchronizing signals output from both amplifiers 3 and 4 is controlled so that it is always equal to the reference voltage Vref. .

On the other hand, the output voltage of the sample-and-hold circuit 12 is inputted to the non-inverting input terminal of the inverting amplifier 4 via the low-frequency amplifier 10 to form a negative feedback loop. By controlling the voltage, it becomes possible to keep the tip potential of the synchronizing signal of the inverting amplifier 4 constant.

By doing this, the output DC potential of the non-inverting and inverting amplifiers 3 and 4 can be maintained at a constant value Vref while the output DC potential of the inverting amplifier 4 is maintained constant, and an extremely stable video signal is transmitted. It becomes possible.

In the inverting amplifier 4, a feedback loop is formed using the output of the low frequency amplifier 10 to keep the DC offset voltage constant; this is to keep the DC potential of the video output 17 of the buffer amplifier 6 constant. A clamp circuit may be provided at the subsequent stage of this output 17.

Effects of the Invention As described above, according to the present invention, fluctuations in the DC component of the video signal caused by offset fluctuations of the amplifier can be easily suppressed, so that the horizontal synchronization signals of the inverted and non-inverted video signals can be easily suppressed. This has the effect that it is possible to always maintain the peak level difference at a constant value (1V _pp ).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional technique, and FIG. 3 is an example of the output waveform of a video signal obtained by the blocks of FIGS. 1 and 2. Explanation of symbols of main parts, 3...Non-inverting amplifier, 4
...Inverting amplifier, 5...Switcher, 9...Synchronization detector, 1
2, 13...Sample and hold circuit, 14...Differential amplifier, 10, 15...Low frequency generator, 16...Synthesizer.

Claims (1)

[Claims] 1. First and second amplifiers that non-invert and invert amplify the input video signal, respectively, and the outputs of the first and second amplifiers are alternately switched according to the timing of a synchronization signal included in the input video signal. a switching means for outputting a synchronizing signal from the first and second amplifiers, and a level holding means for detecting and holding the peak voltage level of the synchronizing signal output from the first and second amplifiers; a signal generating means for generating a sum output signal of the difference between the head voltage levels and a predetermined reference voltage; and a control means for controlling a DC offset voltage level of one of the first and second amplifiers in accordance with the sum output signal. A video signal transmission circuit comprising: