JPH02177767A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To prevent disturbance for a video such as a sag or shading, etc., easy to generate in an AGC amplifier at a succeeding stage from occurring by applying control so as to operate either a first sampling circuit to perform sampling during the ordinary output period of an image signal or a second sampling circuit to perform the sampling of constant DC potential in a blanking period by a switching signal from the outside. CONSTITUTION:A sampling pulse from a pulse generation circuit 20 is controlled so as to be sent to a sample switch 29 in the blanking period T4 by a blanking signal from the outside and to a sample switch 25 in the output period T5 of a picture element signal by a changeover switch 21. Thereby, since a constant DC level is outputted to a hold capacitor C2 even when a noise is outputted from a CCD area image sensor 12 in the blanking period, such noise component can be eliminated from the output of a video signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing circuit that processes CCD output signals, and particularly to a signal processing circuit that handles even minute output signal levels such as in a COD area image center. Regarding.

[Conventional technology]

Conventionally, there is a signal processing circuit for a COD area image sensor as shown in the block diagram of FIG. This includes a clock generator 11 that outputs a sample timing f and a reference clock for CCD, a CCD area image sensor 12, a buffer amplifier 13 that amplifies the output of this CCD sensor 12, and a signal processing circuit 10 that processes the output of this buffer amplifier 13. ' and an AGC circuit 14 that amplifies the output of this signal processing circuit 10'. The signal processing circuit 10'' also includes a pulse generation circuit 20 that outputs control signals for the clamp switch 23 and the sample switch 25, a clamp voltage source 22, and a buffer amplifier 24.
．． 25 and capacitors C1 and C2.

FIGS. 4(a) to 4(c) show operational waveform diagrams of FIG. 3. The output signal from the CCD sensor 12 is shown in FIG.
), the zero level output period T follows the feedthrough period TI of the charge detection capacitor reset pulse.
2, and then there is a signal output period T3 due to signal charges. This is the clamp pulse (Fig. 4(b)) which is the output of the pulse generator 20 and the sample pulse (Fig. 4(C)).
) is used to turn on and off the clamp switch 23 and sample switch 25 to clamp the zero level and sample the signal period.

[Problem to be solved by the invention]

The conventional signal processing circuit 10' described above uses this clamp/
Since the sampling operation is performed continuously, the operation is actually performed during the horizontal blanking period and vertical blanking period when no pixel signal is output from the CCD sensor. However, C.O.
The D area image sensor 12 performs vertical transfer during this blanking period, and this transmission pulse has a large amplitude of 7 to 9 Vp-p.

On the other hand, the standard CCD output signal is 250 m.
The driving pulse during this blanking period affects the signal output, and noise of several mV to several + mV is usually observed in the output signal. This noise is not much of a problem at normal signal levels, but when the sensitivity is increased in low light conditions, it is amplified by about 18 dB by the AGC circuit in the subsequent stage, so the noise during the blanking period becomes the normal output signal. The level corresponds to the peak value of or higher. (See FIG. 2(b)) This causes a problem in that a voltage with a large amplitude is output to the AGC circuit 14, and in some cases, it may appear as a disturbance to the image such as sag or shading.

The purpose of the present invention is to solve such problems and focus on the fact that noise components that interfere with video signals occur not during the pixel signal output period of the CCD sensor but during the unnecessary blanking period. , constant DC during unnecessary periods
An object of the present invention is to provide a video signal processing circuit that blocks unnecessary noise component samples by switching to potential samples.

[Means for Solving the Problems] The structure of the video signal processing circuit of the present invention is a correlation system that reduces noise in the video output signal by clamping the CCD output signal immediately after reset and sampling the signal output period. The double sampling circuit includes a first sampling circuit that performs sampling during a normal image signal output period, and a second sampling circuit that samples a constant DC potential during the blanking period of the image signal. It is characterized in that the outputs of the circuits are held by a common capacitor, and one of these sample circuits is operated by a switching signal from the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
~(C) is a waveform diagram explaining the operation.
In contrast to the conventional example, the second voltage source 27 and the buffer amplifier 2
8. Two sample switches and a sample pulse changeover switch 21 for switching between the two sample switches and the sample switch 25 are added. The output signal from the CCD sensor 12 is impedance-converted by a buffer amplifier 13, then DC-cut by a capacitor Cf, and a clamping operation is performed by charging the capacitor C1 with the first voltage source 22 by a clamp switch 23. This is similar to the conventional circuit. After passing through the buffer amplifier 24, the signal period is sampled by the sample switch 25, but the same sample switch 29 is connected to the second voltage source 27 via the buffer amplifier 28, and these two sample switches 28.
29 is connected on the output side, and is connected to one hold capacitor C2.

On the other hand, the sample pulse from the pulse generation circuit 2o is controlled by the changeover switch 21 from the external blanking signal (
As shown in FIG. 2(a), the sample pulse is controlled to be sent to the sample switch 29 during the blanking period T4, and to the sample switch 25 during the pixel signal output period T.

As a result, even if noise is output from the CCD area image sensor 12 during the blanking period, a constant DC level (voltage source 27) is output to the hold capacitor C2 during this period. This noise component can be removed from the video signal output.

〔Effect of the invention〕

As explained above, the present invention provides CO during the blanking period.
Unnecessary noise components appearing in the D sensor output can be removed, which has the effect of preventing image disturbances such as sag or shading that are likely to occur in the subsequent AGC amplifier.

The figure is a waveform diagram illustrating the operation of FIG. 3.

10.10"...Signal processing circuit, 11...Clock generator, 12...CCD area image sensor, 13...Buffer amplifier, 14...AGC circuit,
20.24, 26.28... Pulse generation circuit, 21.
...Sample pulse selection switch, 22.27...Voltage source, 23...Clamp switch, 25.29...
sample switch.

Claims (1)

[Claims] A correlated double sampling circuit that reduces noise in the video output signal by clamping the CCD output signal immediately after reset and sampling the signal output period is a first sampling circuit that performs sampling during the normal image signal output period. , a second sampling circuit that samples a constant DC potential during the blanking period of the image signal,
A video signal processing circuit characterized in that the outputs of these two sample circuits are held by a common capacitor, and one of these sample circuits is operated by an external switching signal.