JPS632495B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to the reduction of pulse noise introduced from the outside into the audio signal system of audio equipment, radio receivers, television receivers, video disc players, etc. The present invention relates to a pulse noise reduction device that enables the reduction of pulse noise to be performed in an audible manner.

(Prior art) Pulse noise, such as ignition noise of a car or pulse noise generated by other electrical equipment, is generated in the audio signal system of various equipment such as electrical equipment or electronic equipment that has an audio signal system. It is well known that if this happens, the quality of the audio signal will deteriorate.

Conventionally, methods for reducing the deterioration in audio signal quality caused by the above-described pulsed noise include (a) reducing the gain of the signal transmission system during the period in which pulsed noise occurs; Alternatively, there is a method of cutting off the signal transmission system (reducing the gain to zero... employing a squelch circuit) to reduce pulse noise, (b) reducing the signal level of the signal during the period of pulse noise, Hold the signal level just before the period of pulsed noise,
Methods that attempt to reduce pulse noise have been put into practice as the most common noise reduction methods, but these methods (a) and (b) There is a problem in that signals are dropped, and even when applying the means (a) and (b) mentioned above, a sufficient noise reduction effect cannot be obtained.

By the way, in order to interpolate the signal loss that occurs during the noise period, after converting the analog signal to a digital signal, a correction signal corresponding to the signal loss portion is created by applying the linear prediction method, and the correction signal is used to interpolate the signal loss that occurs during the noise period. Interpolation of signals during periods of noise is also used in some digital devices, but this requires the use of complex and expensive circuits. , such solutions have not been applied to general audio equipment.

(Problem to be Solved by the Invention) As mentioned above, when the pulse noise mixed in the signal is reduced, signal dropouts occur depending on the period of existence of the pulse noise. Then, the problem is that even if the pulse noise is reduced, it is not possible to obtain an audio signal of good quality.
The problem is that the interpolation of missing portions of the signal requires the use of complex and expensive circuits, making it difficult to apply to general audio equipment.

(Means for Solving the Problems) The present invention provides a sample-and-hold circuit, a differentiating circuit, a gate circuit, and an integrating circuit with a variable integral time constant configured such that the integral time constant changes according to an input voltage value. Create a correction signal that can interpolate the missing part of the signal during the period of pulse noise using an analog circuit with a simple circuit configuration,
The object of the present invention is to provide a pulse noise reduction device that makes it possible to obtain an audio signal of good quality.

(Example) Hereinafter, specific contents of the pulse noise reduction device of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of the pulse noise reduction device of the present invention, in which 1 is an input terminal for an input audio signal S ₁ mixed with pulse noise; is a delay circuit,
CSG is a control signal generation circuit composed of a pulse noise detection circuit 3 and a pulse shaping circuit 4, and from this control signal generation circuit CSG,
A control signal _S2 having a pulse width corresponding to the period in which pulsed noise mixed in the input audio signal _S1 exists is generated.

As the pulse noise detection circuit 3 and the pulse shaping circuit 4 in the control signal generation circuit CSG, appropriate circuits may be selected from well-known configurations.

By the way, the control signal _S2 generated from the control signal generation circuit CSG is required to correspond correctly to the position on the time axis of the pulse noise mixed in the input audio signal. The signal generation circuit CSG detects the pulse noise mixed in the input audio signal, and generates the control signal _S2 with the pulse width corresponding to the period in which the pulse noise exists. Since there is a predetermined time delay determined depending on the operating characteristics of the pulse noise detection circuit 3 used, the pulse noise mixed in the input audio signal corresponds to the pulse noise. The input audio signal supplied to the input terminal 1 is delayed by a delay circuit 2 having a delay time approximately equal to the time difference between the control signal and the control signal generated by the control signal _S2 . To correctly perform various types of signal processing at positions where pulsed noise exists in an input audio signal. The input audio signal S ₁ shown at a in FIG. 2 is the input audio signal S ₁ given the required time delay by the delay circuit 2. The position of the pulse noise mixed in the signal S ₁ and the position on the time axis of the control signal S ₂ shown by b in FIG. 2 exactly match.

In Fig. 2, pulse noises N ₁ , N ₂ , and N ₃ are mixed into the input audio signal during each period from time t ₁ → t ₂ , time t ₃ → t ₄ , and time t ₅ → t _6. This is an example of what is being done.

In FIG. 1, the input audio signal _S1 output from the delay circuit 2 is supplied to the first sample and hold circuit 5 and the differentiating circuit 6.
_The sample-and _- hold _{circuit 5} of FIG _. is maintained under the control of the control signal _S2 for the duration of the pulsed noise.

Therefore, the first sample and hold circuit 5 described above outputs a signal S ₃ shown as c in FIG. 2, and this signal S ₃ is applied to the adder circuit 10. The differentiating circuit 6 outputs a signal S ₄ as shown in d in FIG. 2, which is obtained by differentiating _the signal S 1 shown in FIG.

The second sample and hold circuit 7 is connected to d in FIG.
The period of the pulse width of the control signal S ₂ in the signal S ₄ shown in (same as the period in which each pulse noise _{N 1 ,} N ₂ , N ₃ exists in the input audio signal S 1)
Since the second sample and hold circuit 7 operates to hold the signal level of the signal at the time position immediately before , for a period of the pulse width of the control signal _S2 , the second sample and hold circuit 7 outputs a signal as shown in e of FIG. A signal S ₅ is output and supplied to the gate circuit 8 .

Since the gate circuit 8 operates to open the gate only during the period of the control signal _S2 , the output signal from the gate circuit 8 is a signal _S6 as shown in f in FIG.
becomes.

The output signal _S6 from the gate circuit 8 is given to an integrator circuit 9 with a variable integration time constant configured such that the integrator time constant changes depending on the input voltage value, and in the integrator circuit 9 with a variable integration time constant, The input signal S ₆ as shown in f in FIG. 2 is integrated and outputted as a correction signal S ₇ as shown in g in FIG. .

The adder circuit 10 adds the output signal S ₃ (c in FIG. 2) of the first sample and hold circuit 5 described above and the correction signal S ₇ output from the integrating circuit 9 with a variable integration time constant. A signal S ₈ as shown at h in Fig. 2
is output to the output terminal 11.

The signal S ₈ output to this output terminal 11 is the pulse noise N ₁ , N ₂ , N ₃ of the input audio signal S ₁ .
is removed by the hold operation in the first sample-and-hold circuit ₅ , the differentiator circuit 6, the second sample-and-hold circuit 7, the gate circuit 8, and the integrator circuit with a variable integration time constant By adding the correction signal _S7 created by the operation of a series of circuits such as 9, a signal with a waveform approximating the waveform of the original audio signal (desired signal) and less unnatural to the ear is created. This is what has been said.

The correction signal S ₇ to be added by the adder 10 to the output signal S ₃ of the first sample-and-hold circuit 5 is such that the period of each pulse noise in the input audio signal S ₁ is determined by the first sample-and-hold circuit 5. 5
It must be possible to restore the slope information of the original signal (desired signal) that was lost due to the signal being held at the signal level just before each pulsed noise period. The correction signal S ₇ can be easily generated by a series of circuits described above, including the differentiator circuit 6, the second sample-and-hold circuit 7, the gate circuit 8, and the integrator circuit 9 with a variable integration time constant. Can be done.

A concrete explanation of the above points is as follows. The slope information of the original signal (desired signal), which is lost as described above due to the mixing of pulsed noise, is as shown in a of Fig. 2.
The pulse noise N ₁ in Figure 2 is mixed into the relatively flat top portion of the waveform of the original signal, and the pulse noise N ₂ in Figure 2a is mixed in the AC axis part of the original signal. , that is, when it is mixed in the part showing the maximum slope in the original signal, and when it is mixed in the part between the top of the waveform in the original signal and the AC axis, as in the case of pulse noise N3 in a of Fig. ₂ , Since the degree of inclination is different depending on the case where the inclination is mixed in a medium-level part, the pulse noise N ₁ ,
The correction signal S ₇ that should be generated in response to the slope information that is lost from the original signal due to the mixing of N ₂ and N ₃ corresponds to the part of the original signal that was mixed with pulse noise N ₁ . The correction signal used for the part where the slope is the most gentle, as shown in the correction signal S ₇ (g in Fig. 2) shown at time t ₁ → t ₂ in Fig. 2, and is free from pulse noise. The correction signal used for the part corresponding to the original signal part where N ₂ was mixed is:
As shown in the correction signal shown at time t ₃ → t ₄ in FIG. 2 (g in FIG. 2), the slope is the steepest,
Furthermore, the correction signal used for the portion corresponding to the original signal portion in which the pulse noise N ₃ was mixed is the correction signal S ₇ shown at time t ₅ →t ₆ in FIG.
The slope must be moderate, as shown in (g) in Figure 2.

Signals showing different slopes, such as the correction signal S ₇ shown in g in FIG. 2, are signals S ₆ (second f) in the figure can be provided as an output signal from the integrating circuit 9 by applying it to an integrating circuit 9 with a variable integrating time constant configured such that the integrating time constant changes according to the input voltage value.

Further, as mentioned above, the signal _S6 , which expresses the slope information of the original signal by the polarity and voltage value, is
The signal S ₄ obtained by differentiating the input audio signal S ₁ (a in FIG. 2) by the differentiating circuit 6, that is, shows a phase difference of 90 degrees with respect to the original signal (desired signal), and The starting position of the zero interval in the signal S ₄ (d in Figure 2) in which the differential signal of the pulsed noise in S ₁ is superimposed on the zero level generated corresponding to the period of existence of the pulsed noise. Edge information (The edge at the start position of the zero section is a rising edge or a falling edge depending on the direction of the slope of the original signal, and the degree of slope in the original signal (The length of the edge varies depending on the material.)

That is, the output signal S ₄ (second
d) in the figure is given to the second sample and hold circuit 7, and the second sample and hold circuit 7 outputs the signal _S4.
A signal S5 is created in which the zero interval in is a hold period in which the signal level of the signal _S4 immediately before the zero interval is maintained, and only the signal in the hold period in _the signal _S5 is generated. is extracted by the gate circuit 8, _a signal _S6 as shown in f in _FIG . The slope information of the original signal that the edge of the position had is indicated by the polarity and voltage value.

By integrating the signal S ₆ as shown in Figure 2 f, a correction signal as shown in Figure 2 g is obtained.
As mentioned above, the integrating circuit 9 that produces S ₇ is an integrating circuit with a variable integration time constant that changes depending on the voltage value of the input signal (signal S ₆ ) applied to it. FIG. 3 shows a specific example of the configuration of the variable integration time constant integration circuit 9 described above.

In FIG. 3, 9a is an input terminal, 9b is an output terminal, and 9c is a control signal supply terminal, and the reference numerals of these terminals 9a, 9b, and 9c represent the integral of the variable integral time constant shown in FIG. The block for circuit 9 is also included for reference.

In Fig. 3, A ₁ and A ₂ are operational amplifiers, and X ₁ to
_X4 is a transistor, _R1 to _R6 are resistors, C is a capacitor, and SW is a control signal supply terminal 9.
A switch whose opening/closing is controlled by a control signal S ₂ supplied to c _.
It performs the same operation as when it is in the off state when it is in the high level state. In addition, this switch SW
An electronic switch is used.

The collector _of transistor
It is connected to the base of X ₃ and also to the positive power supply +Vcc via resistor R ₁ .
The emitter of transistor _X2 is connected to the positive power supply +Vcc via resistor _R4 , and the emitter of transistor _X5 is connected via resistor _R5 .

The collector of _{the transistor X 4 is} connected to the _collector of the transistor is connected, and the movable contact V of the switch SW is grounded.

The emitter of the transistor X ₁ is connected to _the negative power supply −Vcc via a resistor R ₃ , and _the collector of the transistor
It is connected to the emitter of transistor X ₄ through resistor R ₆ . And the transistor mentioned above
The collector of X ₂ is connected to the base of transistor X ₄ .

The signal _S6 supplied to the input terminal 9a of the variable integration time constant integrating circuit ₉ shown in FIG.
The polarity, peak value, etc. of the audio signal S1 vary depending on the relative position on the waveform of the audio signal _S1 .

Now, the signal _S6 supplied to the input terminal 9a is amplified by the operational amplifier _A1 , outputted to the Y point, and then given to the bases of the transistors _X1 and _X2 .

The transistor X ₁ and the transistor X ₂ described above are in a state where the voltage at the Y point is zero,
Transistor X ₃ and transistor X ₄ and resistor R ₅ ,
The operation is performed in a standard operating state in which the voltage at point Z in the constant current circuit constituted by _R6 is set to zero.

When the voltage at point Y is positive, the transistor
The collector current of X ₁ increases and the transistor X ₁
The voltage drop across _the collector resistor R ₁ of R 1 increases, which increases the collector current of transistor X ₃ , and the positive polarity voltage at point Y decreases the collector current of transistor As the voltage drop across the collector resistor _R2 of _X2 becomes smaller, the collector current of transistor _X4 decreases, and the voltage at point Z in the constant current circuit becomes Y
It becomes the same positive polarity voltage as the point.

When the voltage at point Y is negative, the transistor
The collector current of X ₁ decreases and the transistor X ₁
The voltage drop across the collector resistor _R1 becomes smaller, which reduces the collector current of the transistor _X3 , and the negative polarity voltage at _the Y point increases the collector current of the transistor
As the voltage drop across the collector resistance R ₂ of X ₂ increases,
An increase in the collector current of transistor X ₄ occurs,
The voltage at point Z in the constant current circuit has the same negative polarity as point Y.

Therefore, the capacitor C connected to point Z in the constant current circuit is connected to the input terminal 9a of the integrating circuit 9.
If the signal S ₆ supplied to is zero, it will not be charged, and if the signal S ₆ is positive,
Capacitor C is connected to the signal so that a positive voltage appears on it.
It is charged with a constant current value determined according to the voltage value of S ₆ , and furthermore, when the signal S ₆ is negative polarity,
Capacitor C is connected to a signal such that a negative voltage is developed across it.
It will be charged with a constant current value determined according to the voltage value of _S6 .

By the way, at both ends of the capacitor C mentioned above,
The fixed contact F and the movable contact V of the switch SW are connected, and the switch SW is turned off only during the high level period of the control signal _S2 , and charging operation to the capacitor C is allowed only during that period. Therefore, the terminal voltage of the capacitor C has a polarity corresponding to the polarity of the signal _S6 within the pulse width of the signal _S6 supplied to the integrating circuit 9, and has a constant voltage determined according to the voltage value of the signal _S6 . Signal S ₇ showing a change characteristic that gradually increases linearly with the slope (g in Figure 2)
It is done. The reason why the change in terminal voltage of capacitor C shows a linear slope characteristic is that capacitor C
The charge for transistors X ₃ , X ₄ , resistors R ₅ ,
This is because the operation is performed using a constant current from a constant current circuit such as _R6 .

The correction signal _S7 shown in g in FIG. 2 produced by the integrator circuit 9 with a variable integration time constant approximately straightens the slope of the desired signal (original signal) during the existence period of pulse noise. Therefore, the output signal obtained by adding the output signal S ₃ of the first sample hold circuit 5 and the above-mentioned correction signal S ₇ in the adding circuit 10
_S8 has a waveform that approximates the original signal as shown in h of FIG.

(Effects) As is clear from the above detailed explanation, the pulse noise reduction device of the present invention can simply attenuate the gain of the transmission system during a period in which pulse noise is mixed. Alternatively, the pulse noise may be reduced by the conventional method described above, in which the signal level during the pulse noise period is maintained at the signal level of the signal immediately before the pulse noise. Unlike static noise reduction devices, since it also interpolates signal loss that occurs during periods of pulsed noise, it is possible to effectively reduce pulsed noise without causing any audible unnaturalness. In addition, since the circuit configuration for interpolating the missing signal can be realized with a simple analog circuit, it is possible to easily provide audio equipment with excellent performance at low cost.

Note that the pulse noise reduction device of the present invention can be expected to be sufficiently effective when the time span in which the pulse noise occurs is narrow, but when the time span in which the pulse noise occurs is wide, it cannot be corrected. The effect may be slightly reduced. However, ignition noise from cars and motorcycles, pulse noise generated from electrical equipment with a built-in electric motor, pop noise caused by dust or scratches on the audio disk, audio when the video disk signal is lost, etc. Of course, the present invention can be effectively applied to dropout noise and other pulsed noises occurring in signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the pulse noise reduction device of the present invention, FIG. 2 is a waveform diagram for explaining operation, and FIG. 3 is a circuit of an example configuration of an integrating circuit with a variable integration time constant. It is a diagram. 1...Input terminal, 2...Delay circuit, CSG...
Control signal generation circuit, 3... Pulse noise detection circuit, 4... Pulse shaping circuit, 5, 7... First and second sample and hold circuits, 6... Differentiation circuit, 8
...Gate circuit, 9...Integrator circuit with variable integration time constant, 10...Addition circuit, 11...Output terminal.

Claims (1)

[Scope of Claims] 1. Means for detecting pulsed noise in an input audio signal containing pulsed noise and generating a control signal having a pulse width corresponding to the period during which the pulsed noise occurs; A delay circuit having a control signal generated by the control signal generating means described above in response to pulsed noise in an audio signal, and a delay time approximately equal to the time difference between the control signal and the corresponding pulsed noise. After delaying the input audio signal containing pulsed noise by
Means for applying the control signal to a first sampling and holding circuit and a differentiating circuit to which the control signal is supplied as a sampling pulse, and means for applying an output signal of the first sample and holding circuit to an addition circuit as one input signal thereof. and means for applying the output signal of the differentiating circuit to a second sample-hold circuit to which the above-described control signal is supplied as a sampling pulse; is supplied as a gate signal to a gate circuit, and the output signal of the gate circuit is supplied to an integrating circuit with a variable integration time constant configured such that the integration time constant changes depending on the input voltage value. means for obtaining a correction signal by applying the correction signal to an adder circuit as the other input signal thereof; A pulse noise reduction device comprising means for outputting an audio signal with reduced noise. 2. The pulse noise reduction device according to claim 1, using an integrating circuit with a linear integration characteristic as the variable integration time constant. 3. The pulse according to claim 1, which uses an integrating circuit with a variable integration time constant that is configured to obtain an integrated output signal with a polarity corresponding to the polarity of a signal input thereto. Sexual noise reduction device.