JPS6322742B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to the reduction of pulse noise introduced from the outside into the audio signal system of audio equipment, radio receivers, television receivers, video disc players, etc. The present invention relates to a device for reducing pulse noise that can be performed audibly well.

(Prior art) Pulse noise, such as ignition noise of a car or pulse noise generated by other electrical equipment, is generated in the audio signal system of various equipment such as electrical equipment or electronic equipment that has an audio signal system. It is well known that if this happens, the quality of the audio signal will deteriorate.

Conventionally, methods for reducing the deterioration in audio signal quality caused by the above-described pulsed noise include (a) reducing the gain of the signal transmission system during the period in which pulsed noise occurs; Alternatively, there is a method of cutting off the signal transmission system (reducing the gain to zero... employing a squelch circuit) to reduce the pulse noise, (b) reducing the signal level of the signal during the pulse noise period. The most common noise reduction methods have been put into practice, such as maintaining the signal level at the level just before the noise period to reduce pulse noise. The method (b) has the disadvantage that the signal is lost during the period of pulsed noise, and the application of the above-mentioned methods (a) and (b) does not sufficiently reduce the noise. The problem was that they were unable to do so.

By the way, in order to interpolate the signal loss that occurs during the noise period, after converting the analog signal to a digital signal, a correction signal corresponding to the signal loss portion is created by applying the linear prediction method, and the correction signal is used to interpolate the signal loss that occurs during the noise period. Interpolation of signals during periods of noise has been adopted in some digital devices, but this requires the use of complex and expensive circuits. Such solutions have not been applied to general audio equipment.

Now, as mentioned above, when the pulse noise mixed in the signal is reduced, the signal dropout will occur depending on the period of existence of the pulse noise. The problem is that it is not always possible to obtain an audio signal of good quality, and the use of complex and expensive circuitry is required to interpolate the missing portions of the signal to solve the above-mentioned problems. This means that the problem is that it is difficult to apply to general audio equipment.

In order to solve the above-mentioned conventional problems, the present applicant's company first uses a differentiating circuit, a sample hold circuit, and a signal having slope information of the desired signal during a period in which pulse noise occurs in the input audio signal. and control signals are supplied,
An analog circuit with a simple circuit configuration that includes a signal correction circuit that is configured to remove pulse noise in the input audio signal and linearly interpolate the desired signal during periods where pulse noise occurs. We proposed a pulse noise reduction device that uses a circuit to generate a correction signal that can interpolate the missing portion of the signal during the period where pulse noise occurs, thereby obtaining a high quality audio signal. did.

FIG. 1 is a block diagram of the previously proposed pulse noise reduction device. In FIG. 1, 1 is an input terminal for an input audio signal S1 mixed with pulse noise, and 2 is a delay circuit. ,
CSG is a control signal generation circuit composed of a pulse noise detection circuit 3 and a pulse shaping circuit 4, and from this control signal generation circuit CSG,
A control signal S2 having a pulse width corresponding to the period in which pulsed noise mixed in the input audio signal S1 exists is generated.

As the pulse noise detection circuit 3 and the pulse shaping circuit 4 in the control signal generation circuit CSG, appropriate circuits may be selected from well-known configurations.

By the way, the control signal S2 generated from the control signal generation circuit CSG is required to correspond correctly to the position on the time axis of the pulse noise mixed in the input audio signal. By the time the generation circuit CSG detects the pulse noise mixed in the input audio signal and generates the control signal S2 having a pulse width corresponding to the period in which the pulse noise exists, Since there is a predetermined time delay determined depending on the operating characteristics of the pulse noise detection circuit 3 used, the pulse noise mixed in the input audio signal and the pulse noise generated in correspondence with the pulse noise are generated. The input audio signal supplied to the input terminal 1 is delayed by the delay circuit 2 having a delay time substantially equal to the time difference between the input audio signal and the control signal S2, and various signals to be performed by the control signal S2 are delayed. Processing is performed correctly at the location of pulsed noise in the input audio signal.

The input audio signal S1 indicated by a in FIG.
The information input audio signal S1 is given a necessary time delay by the delay circuit 2, and the location of pulse noise mixed in the input audio signal S1 shown in a in FIG. 2; This corresponds correctly to the position on the time axis of the control signal S2 indicated by b in FIG.

In FIG. 2, for the input audio signal, time t1 → time t2, time t3 → time t4,
Pulse noise N occurs in each period from time t5 to time t6.
1, N2, and N3 are included.

In FIG. 1, the input audio signal output from the delay circuit 2 is supplied to the input terminal 5a of the signal correction circuit 5. A concrete example of the configuration of the signal correction circuit 5 is as shown by the circuit in block 5 in FIG. 3, in which the control signal S2 generated by the control signal generation circuit CSG is ,
The signal S2 (e in FIG. 2) having the slope information of the desired signal is supplied to the control signal input terminal 5c and the signal S2 (e in FIG. 2) is supplied to the terminal 5d, so that the output terminal 5b receives the signal shown in c in FIG. A signal S3, such as
That is, the output signal S3 is outputted from which the pulse noise in the input audio signal S1 has been removed, and the desired signal during the period in which the pulse noise occurred has been linearly interpolated. For details of the signal correction circuit 5 described above,
This will be described below with reference to FIG.

Output signal S3 from the signal correction circuit 5 described above
is outputted to the output terminal 8 of the device and also supplied to the differentiating circuit 6. Differentiator circuit 6 outputs differential signal S4 as shown in FIG. 2c.

The differential signal S4 described above is the original signal (desired signal)
It shows a phase difference of 90 degrees with respect to the output signal S3 from the signal correction circuit 5, etc., and also shows a signal section that is linearly interpolated in the signal S3 (where pulse noise was present in the original signal). A signal section exhibiting a constant signal level corresponds to a signal portion exhibiting a constant slope in the period (period).

The signal level of the signal section showing the above-mentioned constant signal level in the differential signal S4 may be a positive signal level or a negative signal level depending on the direction of the slope in the original signal.
Thus, the polarity differs depending on the direction of the slope of the original signal, and the signal level of the signal section showing a constant signal level in the differential signal S4 described above differs depending on the degree of slope of the original signal. The size of the gap between the two levels is changing.

Differential output signal S4 output from the differentiating circuit 6
is supplied to the sample and hold circuit 7, and the sample and hold circuit 7 outputs a signal S5 as shown in e of FIG. This signal S5 is the above-mentioned signal S5 when the device is operating in a steady state.
Same as 4.

The sample and hold circuit 7 is essential for operation until the device enters steady state operation. The signal S2 generated by the control signal generation circuit CSG is used as the sampling pulse for the sample and hold circuit 7 described above.

The signal S5 outputted from the sample hold circuit 7 has a signal section showing a constant signal level corresponding to a signal section showing a constant signal level in the differential signal S4 mentioned above, and As shown in FIG.
The output signal S5 from the sample hold circuit 7 is also
The signal section indicating the constant signal level described above contains slope information of the desired signal.

Signal S output from sample hold circuit 7
5, that is, when the signal S5 having the slope information of the desired signal is supplied to the terminal 5d of the correction circuit 5, the signal correction circuit 5 calculates, based on the slope information of the desired signal contained in the signal S5, By creating a correction signal that can linearly interpolate the missing portion of the signal that occurred during the pulse noise mixing period in the input audio signal, and linearly interpolating the missing portion of the signal using the correction signal, A signal S3 as shown in FIG. 1 is sent to the output terminal 8.

Next, with reference to FIG. 3, an example of the configuration of the differentiating circuit 6 and the sample and hold circuit 7, and the configuration and operation of the signal correction circuit 5 will be described. In FIG. 3, block 6 is a differentiating circuit 6, and a capacitor
The block 7 is a sample and hold circuit 7, which is composed of a switch SWs, a capacitor Cs, and an amplifier A4.

Reference numeral 7a denotes an input terminal for the control signal S2 given as a sampling pulse, and the sample-and-hold circuit 7 is connected to the capacitor Cs when the switch SWs is turned off during the high level period of the control signal S2. Maintain signal level.

Block 5 is a signal correction circuit 5, and in the figure, 5a is an input terminal for input audio signals;
5b is an output terminal, 5c is a supply terminal for the control signal S2, 5d is a supply terminal for the signal S5, and A
1 is a first amplifier and A2 is a second amplifier, the first amplifier A1 having a low output impedance, and the second amplifier A2 having a high input impedance.

The output side of the first amplifier A1 and the second amplifier A2
A control signal S2 is connected to the signal transmission path between the input side of
A switch SW is provided which is turned off when The output side of the variable constant current circuit VC is connected to the input side of the second amplifier A2.

In the example shown in Figure 3, the variable constant current circuit VC includes a phase inversion amplifier -A with a gain of -1 and a positive power supply +
A transistor X1 whose emitter is connected to V _DC via a resistor R1, a transistor X2 whose collector is connected to the collector of the transistor X1, and a transistor X2 whose collector is connected to the collector of the transistor X1.
Resistor R2 connected between the emitter of 1 and negative power supply -V _DC , resistor R3 connected between positive power supply +V _DC and negative power supply -V _DC , variable resistor VR, and resistor R4. The base of transistor X1 is connected to the connection point between resistor R3 and variable resistor VR, and the base of transistor X2 is connected to resistor R.
4 and the connection point between variable resistor VR.

The variable resistor VR is used to correct imbalances in the circuit due to variations in the characteristics of the circuit components, and if the circuit can be balanced correctly, it can be replaced with two fixed resistors. .

The variable constant current circuit VC operates in a standard operating state in which the voltage at point Z is zero when the voltage at terminal 5d is zero, and when the voltage at point 5d is positive, Z The voltage at the point has the same positive polarity as the voltage at the terminal 5d, and when the voltage at the terminal 5d has negative polarity, the voltage at point Z has the same negative polarity as the voltage at the terminal 5d.

Therefore, at the Z point of the variable constant current circuit VC,
Since a voltage appears with a polarity and a voltage value corresponding to the polarity and magnitude of the signal in the signal section indicating a constant signal level in the signal S5 applied to the terminal 5d, there is a voltage between the Z point and the ground. When the capacitor C is connected, the capacitor C is charged with a constant charging current that is determined corresponding to the signal level of the signal section in which the signal S5 shows a constant signal level.

In the signal correction circuit 5 in FIG. 3, when the input audio signal S1 is not mixed with pulse noise, the control signal S2 is supplied to the terminal 5c.
is at a low level, the switch SW is turned on, and therefore the input terminal 5a
The input audio signal S1 supplied to the input terminal 5a passes through the signal transmission path of the first amplifier A1 → switch SW → second amplifier A → output terminal 5b.
The signal is transmitted from the output terminal 5b to the output terminal 5b.

At this time, the charge storage capacitor C connected between the signal transmission path and the ground exhibits a terminal voltage value according to the voltage value of the signal transmitted to the signal transmission path. In addition, in the above state where no pulse noise is mixed in the input audio signal S1, the output terminal of the variable constant current circuit VC has an extremely low output of approximately zero ohm through the switch SW which is in the on state. Since it is connected to the output side of the first amplifier A1 having impedance, the variable constant current circuit VC
The current generated in the variable constant current circuit VC in response to the signal S5 applied to the terminal 5d through the terminal 5d and output from the high output impedance variable constant current circuit VC is caused by the low output impedance of approximately zero ohm described above. Since the voltage generated when injected into the output side of the first amplifier A1 having a
This does not cause any hindrance to the desired signal transmitted to No. 2.

Therefore, as a signal to be supplied to the variable constant current circuit VC, it is not necessary to extract and supply only the signal in the signal section showing a constant signal level in the signal S5.
The output signal S5 of the sample-and-hold circuit 7 may be supplied as is to the sample-and-hold circuit 7.

Next, when pulse noise is mixed in the input audio signal S1, a control signal S2 is generated corresponding to the period in which the pulse noise N1 to N3 is occurring, and the signal is generated during the high level period of the control signal S2. The switch SW is turned off. previous switch
By turning off SW, capacitor C
The terminal voltage of is maintained at the signal level when the switch SW is turned off (when the control signal S2 is set to high level).

Furthermore, since the terminal 5d of the variable constant current circuit VC is given a signal in a signal section indicating a constant signal level in the signal S5 in that state,
The variable constant current circuit VC outputs a current having a polarity corresponding to the polarity of the signal S2 applied to its terminal 5d and a constant current value corresponding to the signal level,
As a result, the charge storage capacitor C is charged. The charging operation for the charge storage capacitor C is performed over a period when pulse noise is occurring, and the terminal voltage of capacitor C increases linearly, but there is no pulse noise mixed in. At the moment when the voltage is low, the control signal S2 becomes low level and the switch SW is turned on, so that the accumulated charge in the capacitor C is instantly discharged by the low output impedance of the first amplifier A1.

The variable constant current circuit VC is driven by the signal S5 supplied to the terminal 5d, that is, the signal S5 that includes slope information in the desired signal with a polarity and a constant signal level, so that the variable constant current circuit VC generates a pulse S5. A current with a polarity and a constant current value that corresponds to the polarity and signal level flows into the charge storage capacitor C, and the terminal voltage of the capacitor C is the polarity of the signal in the signal section in which the signal S5 shows a constant signal level, and , is increased linearly with a slope corresponding to the signal level, but before the terminal voltage of the capacitor C is increased by the inflow of current from the variable constant current circuit VC, the terminal voltage of the capacitor C is: Since this is the signal level of the input audio signal immediately before the switch SW is turned off, the signal loss that occurs in the signal corresponding to the period of pulse noise mixed in the input audio signal S1 is detected by the signal correction circuit. It is clear that linear interpolation is performed well by the above-described operation of 5, and the signal S3 sent to the output terminal 8 has a waveform that approximates the original signal.

In Fig. 2, f shows the correction signal for linear interpolation generated in the signal correction circuit 5 as a solid line, and the waveform of the desired signal in the absence of pulse noise as a dotted line. FIG. 2f is an explanatory diagram to facilitate understanding of the operation; in actual operation, the signal correction circuit 5 outputs a signal S3 as shown in FIG. 2c.

(Problems to be Solved by the Invention) In the previously proposed pulse noise reduction device explained with reference to FIGS. When the noise level ratio is small and there is white noise with a relatively high signal level in the high range of the audio frequency band, the white noise present in the high range is caused by the differential operation of the differentiator circuit 6. As a result, the output signal from the sample-and-hold circuit 7 during the period in which pulsed noise is generated is a state in which the held portion of the amplified white noise is added to the held output signal of the desired signal. As a result, a malfunction occurs in the interpolation operation performed during the period when pulse noise occurs, and not only does the interpolation of the signal during the period where the signal is missing occur incorrectly, but also due to the randomness of white noise. The disadvantage of the prior art device is that it can be applied well to signals from signal sources with a small signal level to white noise level ratio because of problems such as the introduction of new noise.

(Means for Solving the Problems) The present invention provides a low-pass filter that connects a signal correction circuit and a differentiation circuit so that a low-frequency signal component in an output signal from a signal correction circuit is directly given to a differentiation circuit. In addition, a high-frequency signal component in the output signal from the signal correction circuit is provided between the signal correction circuit and the differentiation circuit in order to provide the high-frequency signal component in the output signal from the signal correction circuit to the differentiation circuit via the nonlinear circuit. By providing a series connection circuit of a filter and a non-linear circuit, the non-linear characteristics of the non-linear circuit allow even if the signal from the signal source has a small signal level to white noise level ratio. , it is possible to easily obtain an output signal that is not degraded by white noise.

(Example) Hereinafter, specific contents of the pulse noise reduction device of the present invention will be described in detail with reference to the accompanying drawings. FIG. 4 is a block diagram of an embodiment of the pulse noise reduction device of the present invention, and also includes:
FIG. 5 is a circuit diagram of an exemplary configuration of a nonlinear circuit used in the pulse noise reduction device of the present invention, and FIG. 6 is an explanatory diagram of the operation of the nonlinear circuit.

In FIG. 4, components that are equivalent to each component in the pulse noise reduction device shown in FIG. 1 already described are given the same drawing symbols as those used in FIG. 1. .

In FIG. 4, 1 is an input terminal for an input audio signal S1 mixed with pulse noise, 2 is a delay circuit, and CSG is composed of a pulse noise detection circuit 3 and a pulse shaping circuit 4. A control signal generation circuit, this control signal generation circuit
The CSG generates a control signal S2 having a pulse width corresponding to the period in which pulsed noise mixed in the input audio signal S1 exists.

The delay circuit 2, signal correction circuit 5, differentiation circuit 6, sample hold circuit 7, etc. in FIG. Signal correction circuit 5, differentiation circuit 6, sample hold circuit 7
The specific configuration contents and operation explanation of each of these components are as described in detail with reference to FIGS. 1 and 3, etc.

In FIG. 4, the output signal S of the signal correction circuit 5
3 is sent to the output terminal 8, and is also applied to a low-pass filter (low-pass filter) 9 and a high-pass filter (high-pass filter) 10, and the output signal from the high-pass filter 10 is S3b, that is, the high frequency component S3b in the output signal S3 of the signal correction circuit 5 is supplied to the nonlinear circuit 11. The output signal S3a from the low-pass filter 9 described above is given to the addition circuit 12 as one input thereof, and the addition circuit 1
The output signal S3c of the nonlinear circuit 11 is given as the other input to the nonlinear circuit 11.

The adder circuit 12 adds the two signals S3a and S3c supplied thereto and supplies the resultant signal to the differentiator circuit 6 as a signal S3'. Differential circuit 6
Then, a signal S4' obtained by differentiating the signal S3' described above is outputted and supplied to the sample and hold circuit 7, and a signal S5' outputted from the sample and hold circuit 7 is supplied to the terminal 5d of the signal correction circuit 5. Accordingly, the signal correction circuit 5 performs the operation described above and sends out the signal S3 from the terminal 5b to the output terminal 8.

Now, the nonlinear circuit 11 described above may have the configuration shown in FIG. 5 as an example of its configuration. In Figure 5, Da and Db are diodes, Ra and Rb are resistors, and this nonlinear circuit 1
The non-linear characteristic of 1 is as shown by curve A in FIG.

The operation of the nonlinear circuit 11 described above will be explained below with reference to the characteristic curve diagram in FIG.
That is, when the high-frequency component S3b of the output signal S3 of the signal correction circuit 5 is given to the nonlinear circuit 11, the signal S3b has a slight crossover distortion B due to the nonlinear characteristic A of the nonlinear circuit 11.
is supplied from the nonlinear circuit 11 to the adder circuit 12 as an output signal S3c in a state where . On the other hand, the white noise component N given to the nonlinear circuit 11
corresponds to the flat region C in the nonlinear characteristic A of the nonlinear circuit 11, and therefore does not appear in the output signal S3c of the nonlinear circuit 11.

So, through the high-pass filter 10, the nonlinear circuit 1
The output signal S from the signal correction circuit 5 supplied to
If white noise is mixed in the high-frequency component S3b of No. 3, the white noise N will be removed by the flat region C of the nonlinear characteristic A in the nonlinear circuit 11.

The influence of white noise on signal interpolation increases as the signal level of signal S1 supplied to input terminal 1 decreases (as the ratio between the signal level of signal S1 and the white noise level decreases). The fact that the white noise N mixed in the signal S3 is removed by the existence of the flat region C in the nonlinear characteristics of the nonlinear circuit 11 has a great effect on the pulse noise reduction device.

The influence of the nonlinear characteristic A of the nonlinear circuit 11 on the interpolation accuracy will be described as follows. That is, when the signal level of the input signal S1 is below the middle level, the crossover distortion in the output signal S3c of the nonlinear circuit 11 cannot be ignored, and the interpolation accuracy deteriorates slightly, but as described above, the signal correction circuit 5 By giving the high-frequency signal S3b in the output signal S3 of According to the present invention, the above-mentioned conventional problems can be satisfactorily solved.

(Effects) As is clear from the above detailed explanation, the pulse noise reduction device of the present invention simply attenuates the gain of the transmission system during the period when pulse noise is mixed, or , the signal level during the pulse noise period is maintained at the signal level immediately before the pulse noise, thereby reducing the pulse noise using the conventional method described above. Unlike a reduction device, since it also interpolates the signal loss that occurs during the period of pulse noise, it is possible to effectively reduce pulse noise without causing any unnaturalness to the auditory sense. Furthermore, since the circuit configuration for interpolating missing signals can be realized with a simple analog circuit, it is possible to easily provide audio equipment with excellent performance at low cost.

Further, when the pulse noise reduction device of the present invention is applied to a signal from a signal source with a small ratio of input signal level to white noise level, interpolation is completely performed on the resistance component of the signal, and the signal Interpolation with sufficient precision can be easily performed for the high-frequency components of It goes without saying that it can be effectively applied to reduce noise, pop noise caused by dust or scratches on the audio disk, drop-out noise that occurs in the audio signal when the video disk signal is defective, and other pulsed noises. It is.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the previously proposed pulse noise reduction device, Figs. 2 and 6 are waveform diagrams for explaining operation, and Fig. 3 is a circuit of an example configuration of a signal correction circuit and its related circuits. 4 is a block diagram of the pulse noise reduction device of the present invention, and FIG. 5 is a circuit diagram of an example of the configuration of a nonlinear circuit. 1...Input terminal, 2...Delay circuit, CSG...
Control signal generation circuit, 5...Signal correction circuit, 6...
Differential circuit, 7...Sample hold circuit, 8...
Output terminal, 9...Low pass filter, 10...High pass filter, 11...Nonlinear circuit, 12...Addition circuit.

Claims (1)

[Scope of Claims] 1. Means for detecting pulsed noise in an input audio signal containing pulsed noise and generating a control signal having a pulse width corresponding to the period during which the pulsed noise occurs; A control signal generated by the control signal generating means described above in response to pulse noise in an audio signal, and a delay circuit having a delay time approximately equal to the time difference between the control signal and the corresponding pulse noise. The control signal described above is supplied as a timing signal for operation, and a means for delaying an input audio signal containing pulse noise is provided. The delay described above is applied to a signal correction circuit configured to perform a pulse noise removal operation and a linear interpolation operation for a desired signal during a period in which pulse noise is occurring by being supplied with a signal having slope information. means for providing an output signal of the circuit, means for sending an output signal from the signal correction circuit to an output terminal, and providing the output signal from the signal correction circuit to an adder circuit via a low-pass filter; , means for applying the output signal from the signal correction circuit to the addition circuit via a series connection circuit of a high-pass filter having the same cutoff frequency as the low-pass filter and a nonlinear circuit;
means for applying the output signal from the above-mentioned addition circuit to a differentiating circuit; and means for applying the output signal of the above-mentioned differentiating circuit to a sample-hold circuit to which the above-mentioned control signal is supplied as a sampling pulse;
Pulse noise comprising means for outputting a signal having slope information of a desired signal during a period when pulse noise is occurring in the input audio signal from the sample and hold circuit, and providing the signal to the signal correction circuit. reduction device. 2. The signal correction circuit is designed so that the charging operation using the output current of the variable constant current circuit for the charge storage capacitor is performed only during the period when pulse noise is occurring, and the discharging operation is performed instantaneously at the end of the aforementioned period. 2. A pulse noise reduction device according to claim 1, which uses a device configured as follows. 3. As a non-linear circuit, it is configured to transmit only signals with a signal level higher than a preset reference input level, and to attenuate and block low-level desired signals such as white noise level or white noise. A pulse noise reduction device according to claim 1, which uses a device for reducing pulse noise. 4 The signal correction circuit includes a first amplifier with low output impedance, a second amplifier with high input impedance, and a second amplifier from the first amplifier described above.
The switch circuit is provided in the signal transmission path to the amplifier, and is equipped with a switch circuit that cuts off signal transmission during the period when pulse noise is occurring, and a switch circuit that cuts off the signal transmission during the period when pulse noise is occurring. A patent using a circuit in which the output side of a variable constant current circuit that operates so that the output current value is determined by a signal having slope information and a charge storage capacitor are connected to the input side of the second amplifier described above. A pulse noise reduction device according to claim 1. 5. As a variable constant current circuit, one configured such that the current value is set according to the signal level of the input signal to the circuit and a constant current output of the polarity of the input signal to the circuit is obtained is used. A device for reducing pulse noise according to claim 1.