JPS63248134A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63248134A
JPS63248134A JP8231987A JP8231987A JPS63248134A JP S63248134 A JPS63248134 A JP S63248134A JP 8231987 A JP8231987 A JP 8231987A JP 8231987 A JP8231987 A JP 8231987A JP S63248134 A JPS63248134 A JP S63248134A
Authority
JP
Japan
Prior art keywords
oxide film
films
etching
chip
analysis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8231987A
Other languages
Japanese (ja)
Inventor
Yasumasa Tsunekawa
恒川 安正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8231987A priority Critical patent/JPS63248134A/en
Publication of JPS63248134A publication Critical patent/JPS63248134A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the analysis of a product by a method wherein oxide films, whose thicknesses are different from each other, are continuously formed on the periphery of a semiconductor chip constituting a semiconductor device extending from the center of the chip to its outer periphery and these films are used as a monitor for the amount of etching. CONSTITUTION:A region 4, through which a semiconductor chip is exposed, is provided on the central part of the chip using the periphery of the chip and an about 0.1 mum thick oxide film 1 is formed encircling this region by an oxidation production method (LOCOS method). Then, a 0.4 mum thick oxide film 2 is formed around this film 1 by a LOCOS method and moreover, a 1.4 mum thick oxide film 3 is formed by a LOCOS method. In such a way, the films 1-3 are used as a monitor for etching and the thicknesses of the films are confirmed by a change in the colors at the time they are etched, that is, a generated milk white, a reflected color and so on. According to such a way, a means for peeling the films for analysis is not needed and to know simply the aim of the amount of etching becomes possible.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に、製品解析時、表面酸
化膜のエツチング量をモニターすることの出来る半導体
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which the amount of etching of a surface oxide film can be monitored during product analysis.

〔従来の技術〕[Conventional technology]

半導体装置(以下半導体チップと称す)の解析をする場
合、半導体表面に形成された酸化膜を剥がしながら素子
表面の観察を行なうことがある。
When analyzing a semiconductor device (hereinafter referred to as a semiconductor chip), the surface of the device may be observed while peeling off an oxide film formed on the surface of the semiconductor.

たとえば接合破壊型のメモリセルを有するバイポーラF
ROMのメモリセルを解析する場合その解析手段の一つ
としてメモリセルの顕微鏡観察を行なうことがある。こ
のとき、メタライズを除去した後、表面酸化膜をエツチ
ングしながら、その状態を観察するのであるがエッチさ
れた酸化膜量をその都度知ることは重要なことである。
For example, bipolar F with junction-destructive memory cells
When analyzing a memory cell of a ROM, microscopic observation of the memory cell is sometimes performed as one of the analysis methods. At this time, after removing the metallization, the state of the surface oxide film is observed while etching, and it is important to know the amount of the oxide film etched each time.

また、もう一つの例として半導体チップの素子表面につ
いた傷、よごれ等を解析調査することがある。この場合
も酸化膜を剥がしながら素子表面観察を行なうのである
が、やはシどの程度酸化膜がエッチされたかを知る必要
があるし、また傷がどの酸化膜形成工程で出来たのかを
知ることは重要なことである。従来はこのような解析を
行なうのに、半導体チップ内のあらかじめ酸化膜厚の解
っている部分を比較参照しながら酸化膜エッチを行なっ
ていたが、その参照すべき部分が半導体チップ内に広く
ちらばっている場合は、この方法は煩雑であシ、誤まり
の原因となる。またこの方法は、製造プロセスの熟矧が
要求されるので、解析者とプロセス担当者が違う場合は
むずかしい作業となる。
Another example is the analysis and investigation of scratches, dirt, etc. on the element surface of a semiconductor chip. In this case as well, the device surface is observed while peeling off the oxide film, but it is necessary to know how much the oxide film has been etched, and also to know in which oxide film formation process the scratches were created. is important. Conventionally, to perform such analysis, the oxide film was etched while comparing and referencing parts of the semiconductor chip whose oxide film thickness was known in advance, but the parts to be referenced were scattered widely within the semiconductor chip. If so, this method is cumbersome and error-prone. Additionally, this method requires thorough understanding of the manufacturing process, which can be difficult if the analyst and the person in charge of the process are different.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明は従来の上記問題点を解決する為になされたもの
であり、従って本発明の目的は半導体チップ表面酸化膜
エツチング量の目安を知る適当なチェックパタ/を具備
した半導体装置を提供することにある。
The present invention has been made to solve the above-mentioned conventional problems, and therefore, an object of the present invention is to provide a semiconductor device equipped with an appropriate check pattern for determining the amount of etching of the oxide film on the surface of a semiconductor chip. It is in.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の半導体装置は半纏体チップ周辺に酸化膜を形成
し得る工程を適当に組み合せることにより半導体表面に
複数棟のL賀化膜厚を形成せしめたチェックバタンを含
んで構成される。
The semiconductor device of the present invention includes a check button in which a plurality of layers of oxide film thickness are formed on the semiconductor surface by appropriately combining steps for forming an oxide film around the semi-integrated chip.

〔実施例〕〔Example〕

次に本発明の実施例につき図面をもちいて説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例であり、ロコス法により製造
される場合のチェックパタンを示している。第1図(a
)は平面図であシ、第2図(b)はその人−A’ 断面
図である。2は第10コス膜形成バタンであり、2以外
の部分く約1.4μの酸化膜を形成する。1は第20コ
ス膜形成バタンであり、1−2間(右上り斜線部)に約
0.4μの酸化膜を形成する。2−3間(左上り斜線部
)のバタンはコンタクトエツチングバタンであり、約0
.7μの酸化膜がエツチングされ、従って第10コス膜
は約0.7μ残る(図(b)のC)。また2はコレクタ
リンバタンも兼ねている為、1−4間は約0.1μの酸
化膜が形成されている。4はコンタクトエツチングバタ
ンであシ、従って4内部は、はぼシリコン地となってい
る。以上のようなバタンの組合せによシ1−4間0. 
i p (図(b)のa)1−2間0.4/J(図(b
)のb)、2−3間0.7 tt (図(b)のC)、
3外部1.4μ(図(b)のd)の計4種類の酸化膜厚
を形成することができる。
FIG. 1 is an embodiment of the present invention, and shows a check pattern when manufactured by the Locos method. Figure 1 (a
) is a plan view, and FIG. 2(b) is a sectional view taken along the line A' of the person. 2 is a tenth coating film forming button, and an oxide film of about 1.4 μm is formed on the parts other than 2. 1 is the 20th COS film forming button, and an oxide film of about 0.4 μm is formed between 1 and 2 (shaded area on the upper right). The button between 2 and 3 (shaded area on the upper left) is a contact etching button, and the thickness is approximately 0.
.. An oxide film of 7 μm is etched away, and therefore about 0.7 μm of the 10th cos film remains (C in FIG. 2B). Further, since 2 also serves as a collector barrier, an oxide film of about 0.1 μm is formed between 1 and 4. 4 is a contact etching button, so the inside of 4 is entirely made of silicon. The combination of the above-mentioned clicks will result in 0.
i p (a in Figure (b)) 0.4/J between 1 and 2 (Figure (b)
), b), 0.7 tt between 2-3 (C in figure (b)),
A total of four types of oxide film thicknesses of 1.4 μm (d in Figure (b)) can be formed on the outside.

従って酸化膜エツチング時、このバタンを参照すれば、
1−2間がシリコン地(乳白色)になれば、0.4μ程
度エツチングされたことがわかる訳である。しかも解析
目的の素子部も同様にシリコン地(乳白色)となれば、
その部分は第20コス工程による酸化膜であることもわ
かる。また一つの酸酸化膜厚ともう一つの酸化膜厚との
間のエツチング量は酸化膜反射色により判別出来る。尚
バタンのサイズは縦横(X及びY)共に数十μ程度でよ
い。むろん当チェックパタンはウェハー内の酸化膜厚バ
ラツキのモニターとしてもちいることが出来るさらにま
たこのチェックパタンを半導体チップ周辺に複数個もう
けることにより、同一チップ内部の酸化膜バラツキとも
モニターすることが出来るので半導体チップを製造する
上においても有益な情報が得られる。
Therefore, if you refer to this button when etching the oxide film,
If the area between 1 and 2 becomes a silicon base (milky white), it can be seen that it has been etched by about 0.4μ. Moreover, if the element part for analysis purposes is also made of silicon (milky white),
It can also be seen that that portion is an oxide film formed by the 20th cost process. Further, the amount of etching between one acid oxide film thickness and another oxide film thickness can be determined by the oxide film reflection color. Note that the size of the baton may be approximately several tens of microns both vertically and horizontally (X and Y). Of course, this check pattern can be used to monitor oxide film thickness variations within a wafer.Furthermore, by providing multiple check patterns around a semiconductor chip, it is also possible to monitor oxide film variations within the same chip. Useful information can also be obtained when manufacturing semiconductor chips.

〔実施例2〕 第2図は本発明の第2の実施例であシ、アインプレーナ
法によシ製造さnる場合のチェックパタンを示す。(a
)は平面図であり(b)はそのB−B’  断面図であ
る。11はアイソプレーナ酸化膜バタンであり、11以
外の部分に約1.2μの酸化膜を形成する。12は第2
0コス膜パタンであり、この部分(右上り斜線部)に約
0.5μの酸化膜を形成する。14はマスク酸化膜部で
あり、このN3分(左上り点線部)に約0.2μの酸化
膜を形成する。
[Embodiment 2] FIG. 2 is a second embodiment of the present invention, and shows a check pattern when manufactured by the in-planar method. (a
) is a plan view, and (b) is a BB' sectional view thereof. Reference numeral 11 denotes an isoplanar oxide film, and an oxide film of about 1.2 μm is formed on the portion other than 11. 12 is the second
This is a 0 cost film pattern, and an oxide film of about 0.5 μm is formed in this portion (the upper right diagonal line). 14 is a mask oxide film portion, and an oxide film of about 0.2 μm is formed in this N3 portion (upper left dotted line portion).

13はCVD5iOz形成バタンでsb、下地マスク酸
化膜と合せて約0.3μの酸化膜を形成する。また15
はコンタクトエツチングバタンであり、0.4μ程度酸
化膜をエッチする。従りてこの部分(一点鎖線部)は0
.8μ程度のアイソブレーナ酸化膜が残る。
Reference numeral 13 denotes a CVD 5iOz forming step sb, which forms an oxide film of about 0.3 μm together with the underlying mask oxide film. Also 15
is a contact etching button, which etches the oxide film by about 0.4μ. Therefore, this part (dotted chain line part) is 0
.. An isobrener oxide film of about 8μ remains.

以上のようなバタンの組合せにより14に0.2μ(図
(b)のg)、13に0.3(図(b)のf)、12に
0.4 μ(図(b)のe)、15に0.8μ(図(b
)のh)11以外に1.2μ(図(b)のi)の計5種
類の酸化膜厚を形成することが出来る。
With the combination of the above-mentioned slams, 0.2μ for 14 (g in figure (b)), 0.3 for 13 (f in figure (b)), and 0.4 μ for 12 (e in figure (b)) , 0.8 μ in 15 (Figure (b)
In addition to h) 11 in ), it is possible to form a total of five different oxide film thicknesses of 1.2μ (i in Figure (b)).

第1の実施例同様、このバタ/を参照しながらエツチン
グを行なうことにより、解析をより正確かつ便利にする
という利点をもつ。また、製造モニターとしても有効で
あるという利点も合せもつ。
As in the first embodiment, etching is performed while referring to this pattern, which has the advantage of making the analysis more accurate and convenient. It also has the advantage of being effective as a manufacturing monitor.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、半導体チップ周辺
に酸化膜モニター用のバタンをもうけておくことにより
、解析時便利であると同時に、製造時1ヌ化膜形成状態
のモニターとしても利用できるという効果がある。
As explained above, according to the present invention, by providing a button for monitoring the oxide film around the semiconductor chip, it is convenient for analysis, and at the same time, it can be used to monitor the state of monolayer film formation during manufacturing. There is an effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例であシ(3)は平面図で
るシ、(b)はそのA −A’ 断面図である。涼2図
は本発明の第2の実施例であシ、(a)は平面図、(b
)はそのB −B’ 断面図である。 1・・・・・・第20コスパタン、2・・・・・・第1
ロコスパタン、コレクタリンバタン、3,4・・・・・
・コンタクトエツチングバタン、5・・・・・・エピタ
キシャル層、6・・・・・・埋込層、7・・・・・・絶
縁層、a・・・・・・マスク酸化膜厚、b・・・・・・
第20コス膜厚、C・・・・・・コンタクトエツチング
された第1ロコス臆厚、d・・・・・・第10コス膜厚
、11・・・・・・アイソプレーナ酸化バタン、12・
・・・・・嬉20コスパタン、13・・・・・・CVD
5iO□形成バタン、14・・・・・・マスクρ化膜部
、15・・・・・・コンタクトエツチングバタン、e・
・・・・・詔20コス膜、f・・・・・・CV D S
 io を膜厚、g・・・・・・マスクげノ化膜厚、h
コンタクトエツチングされたアイソプレーナ酸化肋厚、
i・−・・・・アイソプレーナ酸化g+ 厚、16・・
・・・・エピタキシャル層、17・・・・・・埋込層、
18・・・・・・チャンネルストッパー。 −ゝ\ 代理人 弁理士  内 原   B   ’ 4−5′
FIG. 1 shows a first embodiment of the present invention, and (3) is a plan view, and (b) is a sectional view taken along line A-A'. Figure 2 shows a second embodiment of the present invention, (a) is a plan view, (b)
) is its BB' cross-sectional view. 1...20th Cospatan, 2...1st
Locospatan, Collectorinbatan, 3,4...
・Contact etching pattern, 5...Epitaxial layer, 6...Buried layer, 7...Insulating layer, a...Mask oxide film thickness, b...・・・・・・
20th coating film thickness, C... Contact etched first coating thickness, d... 10th coating thickness, 11... Isoplanar baton oxide, 12.
・・・・・・20 happy costumes, 13・・・CVD
5iO□ formation button, 14...Mask ρ film part, 15...Contact etching button, e.
...Edict 20 Cosmembrane, f...CV D S
io is the film thickness, g...Mask genation film thickness, h
Contact-etched isoplanar oxidized ribs,
i・−・Isoplanar oxidation g+ thickness, 16・・
...Epitaxial layer, 17...Buried layer,
18... Channel stopper. −ゝ\ Agent Patent Attorney Uchihara B'4-5'
increase

Claims (1)

【特許請求の範囲】[Claims] 酸化膜を形成し得る工程を適当に組み合せることにより
、半導体表面に複数種の酸化膜厚を形成せしめたチェッ
クパタンを含むことを特徴とする半導体装置。
A semiconductor device comprising a check pattern in which a plurality of oxide film thicknesses are formed on a semiconductor surface by appropriately combining processes capable of forming an oxide film.
JP8231987A 1987-04-02 1987-04-02 Semiconductor device Pending JPS63248134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8231987A JPS63248134A (en) 1987-04-02 1987-04-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8231987A JPS63248134A (en) 1987-04-02 1987-04-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63248134A true JPS63248134A (en) 1988-10-14

Family

ID=13771245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8231987A Pending JPS63248134A (en) 1987-04-02 1987-04-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63248134A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081058A (en) * 1987-12-17 1992-01-14 Nec Corporation Method of manufacturing an insulated gate field effect transistor allowing precise control of operating characteristics

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014811A (en) * 1983-06-25 1985-01-25 エルンスト・ライツ・ヴエツラ−・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Hanging belt attaching apparatus
JPS61237428A (en) * 1985-04-15 1986-10-22 Sharp Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014811A (en) * 1983-06-25 1985-01-25 エルンスト・ライツ・ヴエツラ−・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Hanging belt attaching apparatus
JPS61237428A (en) * 1985-04-15 1986-10-22 Sharp Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081058A (en) * 1987-12-17 1992-01-14 Nec Corporation Method of manufacturing an insulated gate field effect transistor allowing precise control of operating characteristics

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