JPH0358416A - Side etching amount control method and semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to measure the correct amount of side etching by a method wherein the connection between the recessed regions of the controlling layer to be etched is observed with an optical microscope from above a substrate, and the amount of side etching is controlled. CONSTITUTION:On a controlling layer 6 to be etched which is identical to the layer 6 to be etched, on which a field region having no semiconductor element is formed, controlling aperture masks Za, b, having the shape identical to or correlated with an aperture mask for element, are laminated side by side in such a manner that their aperture regions are arranged with prescribed intervals. Thus, recessed regions are formed in the layer 6 to be etched, and at the same time, recessed regions are formed in the controlling layer 6 to be etched. Then, the state of connection to be made between the recessed regions of the controlling layer 6 through side etching is observed with an optical microscope from above the substrate, and the amount of side etching is controlled. As a result, the amount of side etching can be measured simply and accurately in non-destructive manner.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a side etching amount control method in a semiconductor device manufacturing process using side etching, and a semiconductor device using the control method. It is especially used in processes and semiconductor devices that require highly accurate side etching. (Conventional technology) Various self-alignment technologies have been developed as semi-four-body devices become smaller and faster. For example, JP-A-60-8186
The external base opening region of the ultrahigh-speed bibolar device disclosed in No. 2 is formed in a self-aligned manner by side etching of the silicon nitride film on the base region and emitter region. A conventional method for controlling the amount of side etch, which requires high precision, involves cutting a preceding wafer or a sampled wafer, observing the cross section with a scanning microscope (SEM), and measuring and controlling the amount of side etch. Moreover, as a simpler means, the image of side etching from the surface is observed with an optical microscope to determine the approximate amount of etching.

In the case of measurement using a conventional SEM, since the wafer is broken and measured, not only a large number of wasted wafers are required, but also the measurement takes time, resulting in poor productivity. When using a simpler optical microscope, the image of the side etch was blurred by the film on top of the etch film, making it impossible to accurately measure and control the amount of side etch. (Problems to be Solved by the Invention) As mentioned above, in the conventional side etch amount control method, the method of dividing the wafer and measuring the side etch amount with SEM and controlling it has a high process cost, process time, etc. There is a problem that it takes a lot of time and productivity is poor, and the method of non-destructively measuring and controlling the side etching amount using an optical microscope has a problem that it is not possible to accurately measure the side etching amount.

An object of the present invention is to provide a control method that solves the above-mentioned problems in the manufacturing process of a semiconductor device using side etching, and allows simple and accurate process control of the amount of side etching, and a semiconductor device using the method. [Structure of the Invention] <Means for Solving the Problems and Their Effects> The method for controlling the amount of side etching of the present invention provides a method for controlling the amount of side etching by etching a surface layer on a semiconductor substrate or a layer to be etched selectively in the substrate. A semiconductor device in which a device opening mask is made of an etching-resistant material and has an opening region, and then etching including side etching is performed from the surface of the layer to be etched exposed in the opening region to form a concave region in the layer to be etched. In the manufacturing process, a control opening having a shape equal to or correlated with the element opening mask is formed on a control etching layer equal to the etching layer formed in a field region of the substrate where no semiconductor element is formed. After the masks are laminated in parallel so that their opening areas are at a predetermined interval, a step of forming a recessed region in the control layer to be etched is performed simultaneously with the step of forming a recessed region in the layer to be etched, and in the step, Use an optical microscope from above the substrate to confirm that the concave regions of the control layer to be etched are connected by side etching! It is characterized by controlling the side etching l. Further, the semiconductor device of the present invention is manufactured using the side etching amount control method described above, and is characterized in that the semiconductor device includes a recessed region of the control layer to be etched. The present invention was made based on the following findings. That is, the optical contrast between the recessed region used as a horizontal component of the iR element and the layer to be etched is small. Therefore, with the conventional technology using optical gR@mirror, it is difficult to accurately identify the interface between the sidewall of the recessed region formed by side etching and the layer to be etched, and delicate control of the amount of side etching is not possible. In this OJJ, a plurality of control opening masks that do not operate as functional elements are arranged in parallel so that their opening areas are at predetermined intervals, for example, at intervals of about twice the desired side etching amount, so that the side etching progresses. As a result, the distance between adjacent control concave regions decreases, the intervening film between both concave regions becomes thinner, and when the desired amount of side etching is reached, this intervening film becomes colored due to optical effects such as interference. Il! It is measured. In other words, the optical contrast between the control recessed region and the thin control etching layer interposed between the two regions is extremely large, and therefore it can be seen from above the substrate that the control recessed regions are connected by side etching.
Accurate wA8 at the bell! This makes it possible to finely control the amount of side etching. In addition, when the aperture areas of the control aperture masks are arranged in parallel at a predetermined interval, it is desirable to carry out the following procedure. The predetermined interval is about twice the desired amount of side etching, or a plurality of sets of control opening areas are provided in which the predetermined interval is changed around twice the desired amount of side etching, or the predetermined interval is gradually increased. At least three or more control aperture masks must be aligned without being changed.

Further, the aperture mask for an element has a multilayer thin film used as a forming element of a functional element, and this multilayer may include an oxide film, a nitride film, and a conductive film such as polysilicon or polycide. However, the surface of the opening mask including the open D pi region must be covered with an etching-resistant material whose etching rate is substantially negligible compared to the layer to be etched.

(Embodiment 1 row) FIG. 1 and FIG. 2C are a plan view and a cross-sectional view for explaining one embodiment of the side etch amount control method of the present invention. FIG. 1 is a plan view showing a set of control aperture masks 2a and 2b arranged and stacked on a control etching layer l on a semiconductor substrate. The interval W between the opening regions 3a and 3b of this set of control opening masks is determined by the desired side etching 11.
1. is set to twice that of . Etching is performed from the opening head regions 3a and 3b, and the side etched ends of the recessed regions gradually widen. In FIG. 1, etching progresses in the order of side etch ends A, B, and C, and at side etch end C, adjacent recessed regions are connected. FIG. 2 is a cross-sectional view showing a manufacturing process in which a concave region is formed after a control aperture mask is laminated in parallel on a control layer to be etched. This manufacturing process of this example is performed almost identically and simultaneously with the manufacturing process of forming the concave area after laminating the device opening mask on the layer to be etched of the device, so a description of the manufacturing process for the device will be omitted. do. Second
As shown in FIG.
After forming the r+n thermal oxide film 5, 400 nl of silicon nitride PIA6 and polysilicon M7 are deposited by the CVD method.
, 300r+ silicon oxide 11!8 by CVD method
+m are deposited sequentially. Next, as shown in FIG. 4B, a resist pattern 9 is formed by a conventional photolithography technique, and using this as a mask, silicon oxide M8 and polysilicon pa7 are sequentially removed by anisotropic etching.
The distance W between the openings of adjacent resist patterns is set to twice the desired side etching amount l0. Next, as shown in FIG. 3(c), after removing the resist 9, the side wall portion of the polysilicon film 7 is oxidized, and the barrier wall is oxidized Ii! Form 10. Here, the silicon nitride PIA 6 is the layer to be etched for control 1, and the control opening masks 2a and 2b have opening regions 3a and 3b, and the polysilicon fllA 7 whose surface is covered with a silicon oxide film and silicon This is a laminated film of oxide J8. Next, as shown in FIG. 4(d), hot phosphoric acid heated to 100 to 190° C. is applied to the silicon nitride film 6 exposed in the opening head regions 3a and 3b.
Etching the silicon nitride film 6 to form concave regions 11a, fl
Form b. As the etching progresses, the side etched end of the recessed region passes through A and B and reaches C, and the recessed regions 11a and llb are connected. Note that A and B in Figure 2
, C correspond to A, B, and C in Figure 1. During or after the etching process, the wafer is taken out and the concave areas 11 are examined using an optical microscope.
Measure the vicinity of the intervening film 12 sandwiched between a and llb. If the film thickness of the intervening WA12 is thin, similar to a thin soap film,
Vivid colors can be seen due to light interference, making it possible to accurately identify their presence. In the embodiments shown in FIGS. 1 and 2, the mask has one set of aperture areas and one type of spacing for the sake of simplicity; however, in reality, many aperture areas with different spacings are formed at the same time. By doing so, the progress of side etching can be grasped more accurately. FIGS. 3 and 4 are schematic plan views showing an embodiment in which a large number of control opening areas at different intervals are arranged in parallel. FIG. 3 shows a plurality of sets of control aperture masks arranged in parallel, in which the interval W between the control aperture regions 3 changes around twice the desired side etching amount.

FIG. 4 also shows that the control opening masks are arranged so that the interval W between the control opening regions gradually changes from a value that does not reach 2@ of the desired side etching amount l0 to a value that exceeds twice the desired side etching amount l0. They are installed side by side. The shape of the aperture region of the control aperture mask does not always need to be equal to the shape of the aperture region of the element aperture mask. There is a certain correlation between the side etching amount of the concave area obtained using the control aperture mask and the side etching amount of the concave area obtained using the element aperture mask, and There is no problem as long as the shape can be determined by trial etc. Next, an embodiment in which the present invention is applied to an ultra-high-speed bibolar 1 transistor with horizontal trench isolation will be described below. FIG. 5 is a cross-sectional view showing an outline of the manufacturing process of the transistor, and FIG. 6 is a cross-sectional view 1h1 of the transistor after the main manufacturing process is completed.

As shown in FIG. 5(a), an N1 type buried layer 22 and an N1 type epitaxial layer 23 are formed on a P type silicon substrate 2l. Next, trench isolation 24 and LOCOS oxidation 25 are performed for isolation between and within elements. Next, an oxide film 26 is formed in the element formation region and the control opening mask formation region.
is formed, and nitride M27 is laminated thereon. Nitriding weir 2
Of 7 and oxidation 1 and 26, both films on the collector extraction region m are selectively removed to form a collector opening 28. After a polysilicon film 29 is deposited on the entire surface by CVD, unnecessary portions of the polysilicon film are selectively oxidized (1). , polysilicon oxide I1*3 0.

After selectively introducing phosphorus into the polysilicon layer 29b in the collector extraction region, N1 diffusion layers 31 for collector contacts 1 to 1 are formed. Polysilicon layer 2 in element shape area
9, and boron is introduced into the polysilicon layer 29a in the region where the control opening mask of the present invention is formed. Furthermore, CVD oxidation I
A32 is deposited to form a self-alignment resist pattern 33 having openings in the emitter formation region and the control opening mask formation region. As shown in FIG. 3B, using a resist pattern 33, a CVD oxide film 32 and a polysilicon film 32 are formed. I29 and 29
a is removed by RIE, and an opening 3 reaching the nitriding layer 27 is formed.
4, 34a, and 34a2, lIl wall dioxide films 35, 35, . . . 35a2 of the polysilicon films 29 and 29a exposed in these openings are formed. Note that the layer to be etched described in claim 1 is the same for the device and for the control, and both are for the nitride film 27.
It is. The element opening mask Σdan is made of polysilicon IIl29 having an opening region 34 and whose surface is covered with Sin2.
It is a laminated film consisting of 111132 and CVD oxidation.
In addition, the opening masks 50a+ and idanmu for g1 have opening regions 34 and 34a2 of the same shape as the opening region 34, respectively, and a polysilicon film 29a whose surface is covered with Sin, and a CVD oxide film 32. It is a laminated film consisting of. Note that the distance between the opening regions 34a and 34a2 is set to twice the predetermined side etching amount. The same figure (c
), open head area 34, 3 4 a+ 13
4 Using hot phosphoric acid heated to about 150° C. from a2, the silicon/I nitride film 27 is etched to form concave regions 36 and 36.
,,, form 36a2. The amount of side etching is controlled by observing the vicinity 37 of the intervening layer sandwiched between the concave regions 36a and 36a2 from above using an optical microscope. As shown in FIG. 6, the oxide film on the bottom of the recessed region is removed to form an oxide film opening 38. Next, polysilicon is buried in the overhang part of the recessed region, and a buried polysilicon layer 39 is formed.
form. Next, after thermal oxidation is formed on the surface of the substrate exposed to the buried polysilicon layer 39 and the opening region 34, boron ions are implanted into the silicon substrate to form an internal base region. Reference numeral 40 is an oxide film formed on the side surface of the buried polysilicon layer 39. Next, a polysilicon sidewall 41 is formed, and the emitter opening 4 is formed using this as a mask.
Form 2. Next, emitter silicon 43 is deposited to form an emitter region. AI is deposited and patterned to form AI wiring 44. External pace region 4 of the bibolar transistor with the above configuration
5 is formed in a self-aligned manner using the buried polysilicon layer 39 as an impurity source. The buried polysilicon layer 39 can be formed with high precision by applying the side etching amount control method of the present invention. The present invention is not limited to the above embodiments. Generally, in an etching process involving side etching, the present invention can be applied to an etching process or a semiconductor device where it is necessary to control the amount of side etching with high precision.

[Effects of the Invention] According to the side edge amount control method and semiconductor device of the present invention, the side etch area can be measured non-destructively, simply and accurately in the manufacturing process of a semiconductor device using side etching, and the process It has become possible to reduce costs, shorten the process, and perform detailed process control.

[Brief explanation of drawings]

1 and 2 are a plan view and a cross-sectional view for explaining an embodiment of the side etch amount control method, and FIGS. 3 and 4 are
FIG. 5 is a plan view showing an embodiment of parallel arrangement of control opening regions of the present invention, FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device of the present invention, and FIG. 6 is a cross-sectional view of the semiconductor device of the present invention. ．． 1,6.27...Layer to be etched (silicon nitride II
Q), 2a, 2b, 5 0a+, 5
0a2... control aperture mask, 3a, 3b, 3
4a+, 34a2... Control opening area, 4.21.
...Semiconductor substrate, 11a, 1 lb, 36, 36a
+, 36az"' concave area, i Dan...Aperture mask for element, 34...Aperture area for element, W...Distance between aperture areas. Fig. 1 Fig. 2 <1> Fig. 2 <2> Figure 3 Figure 4 (a) (b) Figure 5 (1>

Claims (1)

[Claims] 1. On a semiconductor substrate or on a layer to be etched which is selectively etched in the substrate, the surface is made of an etching-resistant material,
In a manufacturing process of a semiconductor device, the step of manufacturing a semiconductor device includes stacking an opening mask for an element having an opening region, and then performing etching including side etching from the surface of the layer to be etched exposed in the opening region to form a concave region in the layer to be etched. A control aperture mask having a shape equal to or correlated with the element aperture mask is placed on the control wave etching layer, which is formed in a field region where no semiconductor element is formed, and whose opening area is equal to or correlated with the element aperture mask. After stacking the layers in parallel at a predetermined interval, a step of forming a recessed region in the control layer to be etched is performed at the same time as a step of forming a recessed region in the layer to be etched; Using an optical microscope, we observed from above the substrate that the regions were connected by side etching.
A side etch amount control method characterized by controlling a side etch amount. 2. A semiconductor device comprising a concave region of a control layer to be etched according to claim 1.