JPH07201823A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To monitor remaining film thickness quantitatively without the influence of experience and subjective judgment of workers in the process of etching a film for leveling the surface applied to a semiconductor substrate. CONSTITUTION:Forming a monitor pattern 6 that comprises groove shaped patterns of which width changes stepwise on a surface of a metal film 5 in advance, a resist film 7 for the leveling of the surface is applied to it. Then the resist film 7 is etchbacked. Checking whether interference color is present on a region of a monitor pattern 6, the remaining-film thickness of the resist film 7 is monitored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for application to the manufacture of a semiconductor device having a step of etching back a surface flattening film formed on a semiconductor substrate. It is a thing.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, as wirings are miniaturized, problems such as short-circuits and disconnections of upper layer wirings occur at portions where stepped shapes such as wiring intersections occur, and semiconductor devices are manufactured. It has a significant impact on yield.
Therefore, in order to solve this problem, a technique of flattening the surface of the interlayer insulating film formed on the lower wiring and then forming the upper wiring on the flattened surface is used.

That is, as shown in FIG. 7A, after wirings 102 and 103 of lower layers are formed on a semiconductor substrate 101 via an interlayer insulating film (not shown), these wirings 102 and 103 are formed.
An interlayer insulating film 104 is formed so as to cover 103. At this time, a step is formed on the surface of the interlayer insulating film 104 due to the step due to the wirings 102 and 103. Next, a fluid substance such as the resist film 1 is formed on the surface of the interlayer insulating film 104.
05 is applied to flatten the surface. Next, an anisotropic etching method such as a reactive ion etching (RIE) method is used to etch back from the surface of the resist film 105. As a result, as shown in FIG. 7B, the interlayer insulating film 1
The surface of 04 is flattened. That is, the resist film 10
The flatness of the surface of No. 5 is transferred to the lower interlayer insulating film 104. After that, the interlayer insulating film 1 thus flattened
An upper wiring (not shown) is formed on the surface of 04.

When etching back a fluid material for flattening the surface, such as the resist film 105, it is possible to monitor the remaining film thickness of the fluid material in order to control the etch back amount. is important. Conventionally, this remaining film thickness monitor is used to actually manufacture a semiconductor device by applying the same fluid material under the same conditions on a dummy substrate having a flat surface on which no unevenness due to wiring is generated. It has been carried out by putting the semiconductor substrate together with the semiconductor substrate in an etching apparatus to perform etch back, and observing a change in interference color due to a change in the remaining film thickness of the fluid substance on the dummy substrate as the etch back progresses.

[0005]

However, when the remaining film thickness of the fluid substance is judged from the change of the interference color as described above, its accuracy depends on the skill and subjectivity of the operator who makes the judgment. It will be affected. This problem can be solved if the remaining film thickness can be quantified, but for that purpose, additional equipment such as a spectroscope is required, which causes a new problem that the process is complicated.

Accordingly, an object of the present invention is to determine the remaining film thickness when etching back a fluid material formed on a semiconductor substrate, that is, a film for surface flattening. The surface of the film for surface flattening at the desired depth position can be monitored quantitatively without being affected by the conditions and without using additional equipment such as a spectroscope or complicating the process. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of transferring the flatness of the semiconductor device.

[0007]

In order to achieve the above object, the present invention provides a semiconductor device having a step of etching back a surface flattening film (7) formed on a semiconductor substrate (1). In the manufacturing method, a monitor pattern (6) composed of a plurality of groove-shaped patterns whose widths are changed stepwise is used as a base surface of a film (7) for surface flattening, or
Preliminarily formed on a base surface of a film for surface planarization formed on a semiconductor substrate different from the semiconductor substrate (1),
In the step of etching back the surface flattening film (7), the remaining film thickness of the surface flattening film (7) is monitored according to the position of the area where the interference color is generated on the monitor pattern (6). It is characterized by having done.

As the surface flattening film, a fluid substance such as a resist film is used.

In a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, the monitor pattern includes a plurality of pattern groups in which a plurality of groove-shaped patterns having the same width are arranged at equal intervals in the same group. And a width of the pattern in each of the plurality of pattern groups is gradually changed among the plurality of pattern groups.

In a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, the underlayer of the surface planarizing film is a metal film for forming a gate electrode, and a monitor pattern is formed on the surface of this metal film. .

In another embodiment of the method of manufacturing a semiconductor device according to the present invention, the underlayer of the surface flattening film is an interlayer insulating film, and a monitor pattern is formed on the surface of this interlayer insulating film.

[0012]

According to the method of manufacturing a semiconductor device of the present invention configured as described above, a monitor pattern (6) composed of a plurality of groove-shaped patterns whose widths are changed stepwise is provided, for example, on the semiconductor substrate (1). ) Pre-formed on top,
When a film (7) for flattening the surface made of a fluid material is formed thereon, the film (7) for flattening the surface of the monitor pattern (6) has a narrow groove shape due to its viscosity. The pattern is formed substantially flat on the pattern (1), but is formed in a mortar shape on the wide groove-shaped pattern of the monitor pattern (6).

Therefore, when the etch back progresses, the surface flattening film (7) is first removed from the mortar-shaped region having a small film thickness, and an interference color is generated only in that region. Since the film thickness of the surface flattening film (7) in the mortar-shaped region becomes smaller as the pattern width becomes wider, the pattern width becomes wider in the region where the interference color is generated as the etching back progresses. The pattern gradually moves from the wide area to the narrow area of the pattern. Therefore, it is possible to quantitatively monitor the remaining film thickness of the surface flattening film (7) by observing in which area on the monitor pattern (6) the interference color is generated with a microscope or the like. , It is possible to judge whether or not the remaining film thickness has reached an appropriate value. This can be easily performed without being influenced by the skill and subjectivity of the operator.
Further, in this case, neither additional equipment such as a spectroscope is required nor the process is complicated.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are sectional views showing an embodiment in which the present invention is applied to manufacture of a junction type FET (JFET) IC having a buried gate electrode structure.

In this embodiment, first, as shown in FIG. 1, an n-type impurity is selectively ion-implanted into a semi-insulating GaAs substrate 1 and, thereafter, electrical activation of the implanted impurity is performed as necessary. By annealing for
An n-type channel region 2 is formed in the ET formation region. Then, for example, a silicon nitride (SiN) film 3 is deposited on the semi-insulating GaAs substrate 1 by the CVD method, and then the S
A resist film 4 is applied on the iN film 3. Where SiN
The film thickness of the film 3 is, eg, 450 nm. The resist film 4 has, for example, a viscosity of 30 CP (centipoise).
Use the one. Next, the resist film 4 is exposed using a photomask (or reticle) having a mask pattern having a shape corresponding to the gate electrode to be formed and the monitor pattern, and then the resist film 4 is developed. As a result, the resist film 4 is patterned into a shape corresponding to the gate electrode and monitor pattern to be formed.

Next, the SiN film 3 is etched by anisotropic etching, for example, RIE, using the resist film 4 thus patterned as a mask.
As a result, as shown in FIG. 2, the opening 3a is formed in the SiN film 3 in the gate electrode formation region, and the SiN film 3 in the monitor pattern formation region is patterned into a shape corresponding to the monitor pattern.

Next, the resist film 4 is covered with an organic solvent or O ₂
After removing using plasma, as shown in FIG. 3, a metal film 5 for forming a gate electrode is deposited on the entire surface by a vacuum deposition method, a sputtering method, or the like. The film thickness of the metal film 5 is, eg, 0.2 μm (200 nm). In this case, the step shape of the SiN film 3 having the shape corresponding to the monitor pattern is transferred to the surface of the metal film 5 covering the SiN film 3 patterned in the shape corresponding to the monitor pattern in the monitor pattern formation region. As a result, the monitor pattern 6 is formed on the surface of the metal film 5. Next, a resist film 7 for surface flattening is applied on the metal film 5, and then the resist film 7 is baked. As the resist film 7, for example, a film having a film thickness of 1.2 μm and a viscosity of 30 CP is used.

FIG. 6 is a plan view showing an example of the monitor pattern 6. As shown in FIG. 6, the monitor pattern 6 has a plurality of groove-shaped patterns, and the widths of these patterns change stepwise between the groups, for a total of 10 pattern groups P _{1 to} P _1. Composed of ₁₀ . The pattern intervals in each pattern group are equal, and all are 1 μm. The pattern length is 300 μm. In this case, the width of the pattern in these pattern groups P _{1 to} P ₁₀ is, for example, 1 / the width of the embedded gate electrode to be formed.
The width is set to 10 to 10 times. Specifically, the widths of the patterns in these pattern groups P _{1 to} P ₁₀ are 0.4 μm in order from the pattern group P ₁ to the pattern group P ₁₀ .
0.6 μm, 0.8 μm, 1 μm, 2 μm, 3 μm, 4
It is set to μm, 6 μm, 8 μm and 10 μm. The depth of these patterns may be about the thickness of the metal film 5, for example, about 300 nm. This monitor pattern 6
The place where is provided is, for example, a wafer-like semi-insulating G
It is on a dummy chip area provided in an area other than the chip area that actually becomes the semiconductor device in the aAs substrate 1.

Next, the resist film 7 is etched back in the direction perpendicular to the substrate surface by, for example, the RIE method. This R
The IE is performed, for example, using O ₂ as a reaction gas under the conditions of a flow rate of 10 sccm, a pressure of 10 Pa, and an electric power of 100 W. The etching back by the RIE method is performed until the surface of the metal film 5 immediately below the resist film 7 is exposed based on the etching rate that has been examined in advance, and the remaining film thickness of the resist film 7 is controlled as described above. The following is performed using the monitor pattern 6 of No. 1.

That is, since the resist film 7 is applied in a mortar shape in the wide area of the pattern on the monitor pattern 6 formed on the metal film 5 (see FIG. 3).
A brown interference color, which is the final interference color, is generated just before the end of the etchback (the remaining film thickness of the resist film 7 when the brown interference color is generated is about 30 to 50 nm). The brown interference color generation region gradually moves on the monitor pattern 6 from the wide pattern to the narrow pattern as the etchback progresses. Therefore, after etching back for a certain period of time, the etching back is temporarily stopped, and the monitor pattern 6 is observed with a microscope or the like to confirm on which area of the monitor pattern 6 the brown interference color is generated. . As a result, the remaining film thickness of the resist film 7 on the buried gate electrode formation region at that time can be easily and quantitatively monitored without being influenced by the skill or subjectivity of the operator. If the etch back is insufficient and additional etch back should be performed, the time for the additional etch back can be easily determined.

Since the etch back can be properly performed as described above, after the etch back is completed,
As shown in FIG. 4, the resist film 7 is left on the buried gate electrode formation region.

Then, next, the remaining resist film 7 is formed.
The metal film 5 is dry-processed by, for example, an ion milling method using the as a mask. After that, the resist film 7 is removed by using an organic solvent or O ₂ plasma. Thereby, as shown in FIG. 5, the gate electrode 8 is formed by being embedded in the opening 3a of the SiN film 3.

After that, although not shown in the drawings, the process is completed through the steps of forming openings for contacting the source electrode and the drain electrode in the SiN film 3, forming the source electrode and the drain electrode, and forming the wiring. Complete the JFET IC.

As described above, according to this embodiment, in the step of etching back the resist film 7 for surface flattening applied on the metal film 5 for forming the gate electrode, the JF is used.
Since the area on the monitor pattern 6 formed in advance on the metal film 5 in the area other than the ET formation area is observed, the resist film 7 is formed.
The remaining film thickness of the film does not depend on the skill or subjectivity of the operator, does not require additional equipment such as a spectroscope, does not complicate the process, and is quantitative and highly accurate. Moreover, it can be easily monitored, and the remaining film thickness of the resist film 7 can be set to an appropriate value. By processing the metal film 5 using the resist film 7 as a mask, the gate electrode 8 can be embedded in the opening 3a of the SiN film 3 with an optimum size and almost flatly. According to this embodiment, since the remaining film thickness of the resist film 7 is not accurately controlled as in the case of using the conventional method, the resist film 7 is left in an extra portion, so that it is left on the SiN film 3. The metal film 5 remains on the metal film 5, and as a result, the gate electrode 8 is not flatly embedded in the opening 3a, or conversely, the resist film 7 is etched back more than necessary, so that the metal film 5 is removed. Is never over-removed. This makes it possible to improve the manufacturing yield of JFET ICs.

Next, another embodiment of the present invention will be described. In another embodiment, first, as shown in FIG. 7A, after forming a metal film such as an Au film having a film thickness of 0.5 μm on the semiconductor substrate 101 via an interlayer insulating film (not shown), The metal film is patterned by etching, and the wirings 102 and 103 in the lower layer are formed in the wiring formation region.
And a pattern (not shown) having a shape corresponding to the monitor pattern is formed in the monitor pattern formation region. After that, the interlayer insulating film 104 is formed on them by the CVD method. Here, this interlayer insulating film 10
The film thickness of 4 is, for example, 0.8 μm. At this time, wiring 1
02 and 103 cause a step on the surface of the interlayer insulating film 104, and a monitor pattern (not shown) having a planar shape similar to that shown in FIG. 6 is formed on the surface of the interlayer insulating film 104 in the monitor pattern forming region. ) Is formed.

Next, a resist film 105 is applied to the surface of the interlayer insulating film 104 to flatten the surface. The resist film 105 has a viscosity of 30 CP, for example. Next, for example, RI using O ₂ as a reaction gas
Etching back is performed from the surface of the resist film 105 by the E method. At this time, the remaining film thickness of the resist film 105 can be accurately monitored by confirming in which area on the monitor pattern formed on the surface of the interlayer insulating film 104 the interference color has occurred. .

By properly performing the etch back in this way, as shown in FIG. 7B, the surface of the interlayer insulating film 104 can be flattened and the film thickness thereof can be set to a desired film thickness. Thereafter, an upper wiring (not shown) is formed on the surface of the interlayer insulating film 104 thus flattened.

According to the other embodiment, similarly to the above-described embodiment, in the step of etching back the resist film 105, the remaining film thickness thereof depends on the skill and subjectivity of the operator. Without requiring additional equipment such as a spectroscope and complicating the process,
Since the surface can be quantitatively and highly accurately monitored and easily monitored, the flatness of the surface of the resist film 105 can be transferred to the interlayer insulating film 104. Then, by forming an upper layer wiring on the flat surface of the interlayer insulating film 104, it is possible to prevent the short circuit, the disconnection, and the like, thereby improving the manufacturing yield of the semiconductor device.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above two embodiments,
The monitor pattern is formed on the semiconductor substrate on which the semiconductor device is actually manufactured. However, this monitor pattern is formed on a semiconductor substrate different from the semiconductor substrate on which the semiconductor device is actually manufactured, and these semiconductor substrates are formed. You may make it put in an etching apparatus simultaneously and etch back these semiconductor substrates simultaneously. In this case, the application of the resist film for surface flattening may be performed simultaneously on these semiconductor substrates under the same conditions or separately under different conditions. In the latter case, the correspondence relationship of the remaining film thickness of the resist film on these semiconductor substrates is obtained in advance.

The arrangement of the pattern groups P _{1 to} P ₁₀ in the monitor pattern shown in FIG. 6 may be changed if necessary.

[0032]

As described above, according to the present invention, when the fluid material formed on the semiconductor substrate, that is, the film for surface flattening, is etched back, the remaining film thickness is determined by the operator. It is possible to monitor quantitatively without being influenced by the skill level and subjectivity of the instrument, without using additional equipment such as a spectroscope or complicating the process, and to flatten the surface at the desired depth position. The flatness of the surface of the film for chemical conversion can be transferred.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a JFET IC according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a JFET IC according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating the method for manufacturing the JFET IC according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating the method for manufacturing the JFET IC according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the JFET IC according to the embodiment of the present invention.

FIG. 6 is a plan view showing a monitor pattern used in a method of manufacturing a JFET IC according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a conventional surface flattening method for an interlayer insulating film.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 channel region 3 SiN film 3a opening 4, 7 resist film 5 metal film 6 monitor pattern 8 gate electrodes P _{1 to} P ₁₀ pattern group

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 29/808 21/338 29/812 H01L 21/88 K 9171-4M 29/80 C 9171-4M F

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising a step of etching back a surface flattening film formed on a semiconductor substrate, wherein the monitor is composed of a plurality of groove-shaped patterns whose width is changed stepwise. A pattern is formed in advance on the underlying surface of the surface planarizing film or on the underlying surface of the surface planarizing film formed on a semiconductor substrate different from the semiconductor substrate, In the step of etching back the film, the remaining film thickness of the surface flattening film is monitored depending on the position of the region where the interference color is generated on the monitor pattern. . 2. The monitor pattern is composed of a plurality of pattern groups in which a plurality of groove-shaped patterns having the same width are arranged at equal intervals in the same group. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the pattern is a monitor pattern in which the width of the pattern changes stepwise among the plurality of pattern groups. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the surface planarizing film is a resist film. 4. The surface of the film for flattening the surface is a metal film for forming a gate electrode, and the monitor pattern is formed on the surface of the metal film. Alternatively, the method of manufacturing a semiconductor device according to the above item 3. 5. The underlayer of the film for surface flattening is an interlayer insulating film, and the monitor pattern is formed on the surface of the interlayer insulating film.
Alternatively, the method of manufacturing a semiconductor device according to the above item 3.