JPS63244627A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63244627A
JPS63244627A JP7910587A JP7910587A JPS63244627A JP S63244627 A JPS63244627 A JP S63244627A JP 7910587 A JP7910587 A JP 7910587A JP 7910587 A JP7910587 A JP 7910587A JP S63244627 A JPS63244627 A JP S63244627A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
mask
resist
film
thicknesses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7910587A
Other languages
Japanese (ja)
Other versions
JPH084108B2 (en
Inventor
Tetsuo Higuchi
哲夫 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62079105A priority Critical patent/JPH084108B2/en
Publication of JPS63244627A publication Critical patent/JPS63244627A/en
Publication of JPH084108B2 publication Critical patent/JPH084108B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the thermal distortion of a semiconductor substrate by a method wherein the surface of the semiconductor substrate is oxidized via two or more masks whose thickness differs from one another according to film thicknesses of oxide films. CONSTITUTION:When a semiconductor device containing field oxide films having different film thicknesses is to be manufactured on a semiconductor substrate, thicknesses of masks to be used for field oxidation are decided according to the different thicknesses of desired oxide films; a field oxidation process including the masks is executed. That is to say, because the field oxidation process is executed via the masks of the different thicknesses, desired oxide films 6, 7 according to the thicknesses are formed on a semiconductor substrate 1 during one operation. By this setup, the semiconductor substrate is not influenced thermally; a photolithographic process is executed onto the flat surface; it is possible to obtain the semiconductor substrate with high accuracy and reliability.

Description

【発明の詳細な説明】 〔産業上の利用分野] この発明は半導体装置の製造方法に関し、特に半導体基
板上に膜厚の興なるフィールド酸化膜を有する半導体装
置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a field oxide film of increasing thickness on a semiconductor substrate.

[従来の技術〕 第2A図〜第2F図は従来の製造方法による概略工程断
面図である。
[Prior Art] FIGS. 2A to 2F are schematic process cross-sectional views according to a conventional manufacturing method.

以下、図を参照して製造方法について説明する。The manufacturing method will be described below with reference to the drawings.

たとえば、シリコンよりなる半導体基板1上に熱酸化す
ることによって約500人の下敷酸化膜2を形成し、さ
らにその上にCVD法等で窒化膜3を形成する。窒化1
13上には第1のレジスト4を形成してこれを写真製版
法によってパターニングを行ない、所望のマスクパター
ンとする(第2A図参照)。
For example, an underlying oxide film 2 of about 500 layers is formed by thermal oxidation on a semiconductor substrate 1 made of silicon, and a nitride film 3 is further formed thereon by a CVD method or the like. Nitriding 1
A first resist 4 is formed on the resist 13 and patterned by photolithography to form a desired mask pattern (see FIG. 2A).

次に、第1のレジスト4をマスクとして露出している窒
化113をエツチング除去した後、残存の第1のレジス
ト4を取去りパターニングされた窒化膜3を下敷酸化1
!2上に残す(第2B図参照)。
Next, using the first resist 4 as a mask, the exposed nitride 113 is removed by etching, and then the remaining first resist 4 is removed and the patterned nitride film 3 is covered with an oxide 1
! 2 (see Figure 2B).

パターニングされた窒化膜3をマスクとして半導体基板
1をフィールド酸化し、約16000Aの第1のフィー
ルド酸化膜6を所望位置に形成後、窒化1113を除去
する(第2C図参照)。
The semiconductor substrate 1 is field oxidized using the patterned nitride film 3 as a mask to form a first field oxide film 6 of about 16000 Å at a desired position, and then the nitride 1113 is removed (see FIG. 2C).

続いて、第1のフィールド酸化膜6上を含み、半導体基
板1の下敷酸化II!2上全面に窒化膜9を再び形成後
、その上に上記と同様にパターニングされた第2のレジ
スト5を形成する(第2D図参照)。
Subsequently, the underlying oxidation II of the semiconductor substrate 1 including the top of the first field oxide film 6 is performed! After forming the nitride film 9 again on the entire surface of the nitride film 2, a second resist 5 patterned in the same manner as described above is formed thereon (see FIG. 2D).

さらに、第2のレジスト5をマスクとして露出している
窒化膜9をエツチング除去した後、残存の第2のレジス
ト5を取去り、パターニングされた所望の窒化膜9を残
す(第2E図参照)。
Furthermore, after etching and removing the exposed nitride film 9 using the second resist 5 as a mask, the remaining second resist 5 is removed, leaving the desired patterned nitride film 9 (see Figure 2E). .

最後に、パターニングされた窒化膜9をマスクとして、
再度フィールド酸化を行ない、第1のフィールド酸化膜
よりは薄い約8000Aの第2のフィールド酸化膜7を
形成して、窒化[I9を取去ることによって膜厚の異な
るフィールド酸化膜の形成が完了する(第2F図参照)
Finally, using the patterned nitride film 9 as a mask,
Field oxidation is performed again to form a second field oxide film 7 of about 8000 Å thinner than the first field oxide film, and the nitrided [I9] is removed to complete the formation of field oxide films with different thicknesses. (See Figure 2F)
.

[発明が解決しようとする問題点] 上記のような従来の製造方法では、フィールド酸化工程
が2度あることから、この熱影響によって半導体基板の
受ける熱的歪が大きくなってしまい、その結晶欠陥の発
生を引き起こしていた。
[Problems to be Solved by the Invention] In the conventional manufacturing method as described above, since the field oxidation process is performed twice, the thermal strain experienced by the semiconductor substrate becomes large due to this thermal influence, resulting in the formation of crystal defects. was causing the occurrence of

また、1度目の酸化終了によって、半導体基板表面の平
坦性が損われた後、再度写真製版工程を含むため、その
マスク合わせ精度が向上しないという問題点も有してい
た。
Further, after the flatness of the semiconductor substrate surface is impaired by the completion of the first oxidation, a photolithography process is performed again, which has the problem that the precision of mask alignment cannot be improved.

この発明はかかる問題点を解決するためになされたもの
で、膜厚の異なる酸化膜を形成する際熱影響の少ない、
しかも写真製版工程におけるマスク合わせ精度を向上さ
せる1造方法を提供することを目的とする。
This invention was made to solve this problem, and it is possible to form oxide films with different thicknesses with less thermal influence.
Moreover, it is an object of the present invention to provide a manufacturing method that improves mask alignment accuracy in a photolithography process.

E問題点を解決するための手段] この発明に係る半導体装置の製造方法は、フィールド酸
化時に使用するマスクの膜厚を所望の酸化膜の異なる膜
厚に対応させた厚さに形成し、マスクも含めてフィール
ド酸化するものモある。
Means for Solving Problem E] In the method for manufacturing a semiconductor device according to the present invention, the film thickness of the mask used during field oxidation is formed to correspond to the different film thicknesses of the desired oxide film, and the mask There are some things that undergo field oxidation, including

[作用] この発明においてはm厚の異なるマスクを介してフィー
ルド酸化を行なうので、膜厚に応じた所望のフィールド
酸化膜が半導体基板1に1度で形成される。また、1度
のフィールド酸化ですむためマスク形成のための写真製
版が平坦面に対して実施できる。
[Operation] In the present invention, field oxidation is performed through masks having different thicknesses of m, so that a desired field oxide film depending on the film thickness is formed on the semiconductor substrate 1 at one time. Furthermore, since only one field oxidation is required, photolithography for mask formation can be performed on a flat surface.

[実施例] 第1A図〜第1H図はこの発明の一実施例における概略
工程断面図である。
[Embodiment] FIGS. 1A to 1H are schematic cross-sectional views of steps in an embodiment of the present invention.

以下、図を参照してこの発明の製造方法について説明す
る。
Hereinafter, the manufacturing method of the present invention will be explained with reference to the drawings.

たとえば、シリコンよりなる半導体基板1上に熱酸化す
ることによって約50OAの下敷酸化膜2を形成し、さ
らにその上にCVD法等で約80OAの窒化113を形
成する(第1A図参照)。
For example, an underlying oxide film 2 of about 50 OA is formed by thermal oxidation on a semiconductor substrate 1 made of silicon, and a nitride film 113 of about 80 OA is further formed thereon by CVD or the like (see FIG. 1A).

窒化膜3上には第1のレジスト4を形成してこれを写真
御飯法によってパターニングを行ない、フィールド酸化
膜を形成しないすなわち活性領域となる範囲に対応する
所望のマスクパターンを形成する(第1B図参照)。
A first resist 4 is formed on the nitride film 3 and patterned by photolithography to form a desired mask pattern corresponding to the area where the field oxide film will not be formed, that is, the active region. (see figure).

パターニングされた第1のレジスト4をマスクとして、
露出している窒化膜3をたとえばOF。
Using the patterned first resist 4 as a mask,
For example, the exposed nitride film 3 is OF.

ガス系によってその膜厚が20OAとなるまでドライエ
ツチングを行なう。この場合、窒化膜の工ッチングレー
トは既知であるのでエツチング時間を設定することによ
って容易に膜厚コントロールが可能である(第1C図参
照)。
Dry etching is performed using a gas system until the film thickness reaches 20 OA. In this case, since the etching rate of the nitride film is known, the film thickness can be easily controlled by setting the etching time (see FIG. 1C).

さらに、第1のレジスト4および露出している窒化11
3上全面に第2のレジスト5を形成して、またこれを写
真製版法によってパターニングを行ない、薄いフィール
ド酸化膜を形成する範囲に対応する所望のマスクパター
ンを形成する(第1D図参照)。
Furthermore, the first resist 4 and the exposed nitride 11
A second resist 5 is formed on the entire surface of the resist 3 and patterned by photolithography to form a desired mask pattern corresponding to the area where a thin field oxide film is to be formed (see FIG. 1D).

続いて、第1のレジスト4および第2のレジスト5をマ
スクとして、露出している窒化!13をたとえばCFa
ガス系のドライエツチングによって除去(第1E図参照
)した後、マスクとしていた第1のレジスト4および第
2のレジスト5を除去すると、部分的にその膜厚の興な
るパターニングされた窒化113が下敷酸化lI2上に
残存するく第1F図参照)。
Next, using the first resist 4 and the second resist 5 as masks, the exposed areas are nitrided! 13 for example CFa
After removal by gas-based dry etching (see Figure 1E), when the first resist 4 and second resist 5 that were used as masks are removed, the patterned nitride 113, which has a partially increased film thickness, becomes the underlying layer. (See Figure 1F).

パターニングされた窒化lI3をマスクと(パ1化膜3
のない領域で約16000Aの酸化膜が形成されるよう
なフィールド酸化を行なうと、窒化膜3の200△の薄
い膜厚の部分はすべて酸化されてしまい、半導体基板1
上に約6000〜8000Aの第2のフィールド酸化F
J7がff11のフィールド酸化II 6に連続して形
成される。なお、窒化FJ 3のa厚の厚い部分は完全
に酸化されずに残存窒化118として残り、その下部の
活性f!4域となるべき範囲の酸化を阻止する(第1G
図参照)。
The patterned nitride lI3 is used as a mask (the patterned nitride film 3
If field oxidation is performed to form an oxide film of about 16,000 Å in a region without oxidation, the entire portion of the nitride film 3 with a thickness of 200 Δ will be oxidized, and the semiconductor substrate 1 will be oxidized.
Second field oxidation F of about 6000-8000A on top
J7 is formed consecutively to field oxide II 6 of ff11. Note that the thick a portion of the nitrided FJ 3 is not completely oxidized and remains as residual nitrided 118, and the active f! Prevents oxidation in the range that should be in the 4th region (1st G
(see figure).

最後に、残存窒化II8を除去することににって、所望
の膜pyの興なるフィー・ルド酸化膜が半導体基板1上
に形成された半導体装置が完成する(第1H図参照)。
Finally, by removing the remaining nitride II8, a semiconductor device is completed in which a field oxide film, in which the desired film py is formed, is formed on the semiconductor substrate 1 (see FIG. 1H).

なお、上記実施例では、IS#を限定しているがこれは
一例であって窒化膜の膜厚やフィールド酸化の程度を任
意に変化させることによって、任意のフィールド酸化膜
を形成することができる。
In the above embodiment, IS# is limited, but this is just an example, and any field oxide film can be formed by arbitrarily changing the thickness of the nitride film and the degree of field oxidation. .

また、上記実施例では、窒化膜をマスクとしているが同
様のn能を有する他のマスクであっても同様の効果を奏
する。
Further, in the above embodiment, a nitride film is used as a mask, but the same effect can be obtained even if other masks having the same n-ability are used.

J二た、上記実施例では、2種の興なる膜厚をもとにさ
れているが、3種以上の異なる膜厚であつても適用でき
ることは言うまでもない。
Second, although the above embodiments are based on two different film thicknesses, it goes without saying that three or more different film thicknesses can also be applied.

さらに、上記実施例では、酸化工程に関するもののみ記
載しているが、フィールド酸化を実施する前に下敷酸化
膜や半導体基板をエツチングするなどの加工工程を含め
ることができることは言うまでもない。
Further, in the above embodiment, only the oxidation step is described, but it goes without saying that processing steps such as etching the underlying oxide film or the semiconductor substrate can be included before field oxidation.

[発明の効果] この発明は以上説明したとおり、膜厚の異なるマスクを
介して1度のフィールド酸化で膜厚の異なる所望のフィ
ールド酸化膜が形成できるので、半導体基板に熱影響を
与えることが少なく、また写真製版も平坦面に対してで
きるので精度の高い信頼のおける半導体装置となる効果
がある。
[Effects of the Invention] As described above, the present invention allows desired field oxide films with different thicknesses to be formed in one field oxidation through masks with different thicknesses, thereby preventing thermal effects on the semiconductor substrate. Moreover, since photolithography can be performed on a flat surface, there is an effect that a highly accurate and reliable semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1A図〜第1H図はこの発明の一実施例を示す概略工
程断面図、第2A図〜第2F図は従来の製造方法による
概略工程断面図である。 図において、1は半導体基板、3は窒化膜、4は第1の
レジスト、5は第2のレジスト、6は第1のフィールド
酸化膜、7は第2のフィールド酸化膜である。 なお、各図中同一符号は同一または相当部分を示す。
1A to 1H are schematic process cross-sectional views showing one embodiment of the present invention, and FIGS. 2A to 2F are schematic process cross-sectional views according to a conventional manufacturing method. In the figure, 1 is a semiconductor substrate, 3 is a nitride film, 4 is a first resist, 5 is a second resist, 6 is a first field oxide film, and 7 is a second field oxide film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (5)

【特許請求の範囲】[Claims] (1)半導体基板上に少なくとも2以上の異なる膜厚を
有する酸化膜を形成する半導体装置の製造方法であって
、 前記半導体基板上に前記酸化膜の膜厚に対応する膜厚を
有する少なくとも2以上の異なる膜厚のマスクを形成す
る工程と、 前記マスクを介して前記半導体基板上を酸化することに
よつて、前記酸化膜を形成する工程とを備え、 前記マスクの膜厚に応じて、形成される前記酸化膜の膜
厚が変化する、半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, which comprises forming on a semiconductor substrate at least two oxide films having different thicknesses, the method comprising: forming on the semiconductor substrate at least two oxide films having a thickness corresponding to the thickness of the oxide film; A step of forming masks having different film thicknesses as described above, and a step of forming the oxide film by oxidizing the semiconductor substrate through the mask, and depending on the film thickness of the mask, A method for manufacturing a semiconductor device, in which the thickness of the oxide film to be formed changes.
(2)前記マスクを形成する工程は、 前記半導体基板上に前記マスクとなる層を形成する工程
と、 前記層上にパターニングされた第1のレジストを形成す
る工程と、 前記第1のレジストをマスクとして、露出した前記層を
所望の厚さ除去する工程と、 所望の厚さを除去された前記層上に、さらにパターニン
グされた第2のレジストを形成する工程と、 前記第2のレジストをマスクとして、露出した前記層を
除去する工程とからなる、特許請求の範囲第1項記載の
半導体装置の製造方法。
(2) The step of forming the mask includes: forming a layer to serve as the mask on the semiconductor substrate; forming a patterned first resist on the layer; and forming the first resist on the semiconductor substrate. removing the exposed layer to a desired thickness as a mask; forming a further patterned second resist on the layer from which the desired thickness has been removed; and using the second resist as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing the exposed layer as a mask.
(3)前記マスクは、写真製版法およびエッチング法に
よつて形成される、特許請求の範囲第1項または第2項
記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the mask is formed by a photolithography method and an etching method.
(4)前記マスクは、窒化膜である、特許請求の範囲第
1項、第2項または第3項記載の半導体装置の製造方法
(4) The method for manufacturing a semiconductor device according to claim 1, 2, or 3, wherein the mask is a nitride film.
(5)前記半導体基板は、シリコン基板である、特許請
求の範囲第1項ないし第4項のいずれかに記載の半導体
装置の製造方法。
(5) The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the semiconductor substrate is a silicon substrate.
JP62079105A 1987-03-30 1987-03-30 Method for manufacturing semiconductor device Expired - Lifetime JPH084108B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62079105A JPH084108B2 (en) 1987-03-30 1987-03-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62079105A JPH084108B2 (en) 1987-03-30 1987-03-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63244627A true JPS63244627A (en) 1988-10-12
JPH084108B2 JPH084108B2 (en) 1996-01-17

Family

ID=13680612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62079105A Expired - Lifetime JPH084108B2 (en) 1987-03-30 1987-03-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH084108B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5369052A (en) * 1993-12-06 1994-11-29 Motorola, Inc. Method of forming dual field oxide isolation
US5374586A (en) * 1993-09-27 1994-12-20 United Microelectronics Corporation Multi-LOCOS (local oxidation of silicon) isolation process

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994884A (en) * 1982-11-24 1984-05-31 Semiconductor Energy Lab Co Ltd Manufacture of photoelectric conversion device
JPS5994844A (en) * 1982-11-24 1984-05-31 Nec Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994884A (en) * 1982-11-24 1984-05-31 Semiconductor Energy Lab Co Ltd Manufacture of photoelectric conversion device
JPS5994844A (en) * 1982-11-24 1984-05-31 Nec Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5374586A (en) * 1993-09-27 1994-12-20 United Microelectronics Corporation Multi-LOCOS (local oxidation of silicon) isolation process
US5369052A (en) * 1993-12-06 1994-11-29 Motorola, Inc. Method of forming dual field oxide isolation

Also Published As

Publication number Publication date
JPH084108B2 (en) 1996-01-17

Similar Documents

Publication Publication Date Title
JPH04234108A (en) Mask positioning mark formation method
JPS63244627A (en) Manufacture of semiconductor device
JPH0458167B2 (en)
JP2691175B2 (en) Patterned oxide superconducting film formation method
JPH02172215A (en) Manufacture of semiconductor device
JPS62234333A (en) Formation of mask for processing fine groove
JP2570729B2 (en) Method for manufacturing semiconductor device
JPS61288426A (en) Taper etching method for aluminum film
JPS6232609A (en) Manufacture of semiconductor device
JP2811724B2 (en) Etching method
JPS63111619A (en) Manufacture of semiconductor device
JPH0235448B2 (en)
JP2961860B2 (en) Method for manufacturing semiconductor device
JPH0473608B2 (en)
JPH04364726A (en) Pattern formation
JPS6024009A (en) Formation of impurity region on semiconductor
JPS62177922A (en) Manufacture of semiconductor device
JPH0756319A (en) Production of phase shift reticule
JPH0322686B2 (en)
JPS63155619A (en) Formation of multilayer resist
JPH02117126A (en) Manufacture of semiconductor device
JPH03159112A (en) Manufacture of semiconductor device
JPS6027144A (en) Manufacture of semiconductor device
JPH0442925A (en) Manufacture of semiconductor
JPS63110654A (en) Etching method