JPH0442925A - Manufacture of semiconductor - Google Patents

Abstract

PURPOSE:To suppress scattering of etching dimensions and even up element characteristics in and between IC chips by patterning etched layers by two dry etchings for etching exactly opposite patterns respectively. CONSTITUTION:A polycrystalline silicon layer 2 is deposited on a silicon oxide film 1 and phosphorus is thermally diffused in the polycrystalline silicon layer 2. Another polycrystalline layer 2 is deposited, and exposed and developed with a reticle having the opposite pattern to the normal one. The upper polycrystalline silicon layer 2 is dry-etched with fluorine gas in plasma. After etching in hydrofluoric acid water solution, positive resist 3 is peeled in sulfuric acid solution. Positive resist is applied thick and its surface is securely flattened. The whole surface of the positive resist 3 is dry-etched with gas containing fluorine and oxygen in plasma. The upper polycrystalline silicon layer 2, a silicon oxide film 4, and the lower polycrystalline silicon layer 2 are dry-etched at a time with fluorine gas in plasma. The positive resist 3 is peeled to complete patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a patterning method using dry etching during a semiconductor manufacturing process.

[Prior art 1] Silicon oxide film (Sin), silicon nitride 11i (S
iMN, ), polycrystalline silicon (PolySi), aluminum (A11, etc.), and such materials are dry etched using the method shown in Figure 2.6 Figure 2 shows the main points in the IC die. It is a partial sectional view,
The symbol l indicates a silicon oxide film, 2 indicates polycrystalline silicon, and 3 indicates a positive resist.

A positive resist 3 is patterned on the polycrystalline silicon IIN2 (FIG. 2(a)), and the polycrystalline silicon 1!2 is patterned.
(Fig. 2 (b)) and peel off the positive resist 3 (Fig. 2 (C)). At this time, the loading effect of dry etching (coarse pattern areas are more pronounced than dense pattern areas). IC is etched.)
The etching dimension is wider in a dense pattern part than in a coarse pattern part in the chip (corresponding to 1.>1. in FIG. 2(c)), causing dimensional variation in the chip.

[Problem to be Solved by the Invention 1] However, the above-mentioned dimensional variations cause variations in element capabilities and characteristics within the IC chip, and if the variations are severe, the IC chip itself may become a defective chip.

This problem becomes more serious as the miniaturization progresses.

Now, as a way to suppress this dimensional variation within a chip, it is possible to use a mask or reticle that takes dimensional variation within a chip into account, but it is difficult to linearly change the dimensions within a mask or reticle, and Even if something similar to that is achieved, there are factors that change the loading effect, such as the need to prepare masks and reticles for each layer if the material and thickness of the layer to be etched are different, or placing a dummy pattern adjacent to a rough pattern area. A method to make it appear dense is possible, but there are areas where dummies cannot be made, and it is difficult to form a pattern with uniform density inside the chip.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate variations in etching dimensions within a chip even when dry etching with a loading effect is performed while maintaining the dimensions within a mask or reticle as before.

[Means for Solving the Problems] Therefore, in the present invention, in a patterning step using dry etching during a semiconductor process, a film of a different type from the layer to be etched is formed extremely thinly on a layer to be etched, and then a film of a type different from that of the layer to be etched is formed on the layer to be etched, and then a film of a type different from that of the layer to be etched is further coated on the thin film. A film of the same type as the etching layer is formed,
A resist is patterned on a film of the same type as the layer to be etched in the opposite manner to the usual method, and the film of the same type as the layer to be etched and the thin film are dry-etched to form an etching groove, and after the resist is removed, a resist is applied again and the resist is removed. The method is characterized in that the entire surface is etched so that the resist remains only in the etching grooves, and the layer to be etched is dry-etched in a predetermined pattern.

[For production]

According to the above-mentioned method of the present invention, the patterning of the layer to be etched is formed by dry etching twice, and the etched patterns are completely opposite in the first and second times, resulting in loading. The effects are canceled out and variations in etching dimensions within the chip can be suppressed.

[Example] Fig. 1 shows an example of the present invention, and shows the flow of the process with a sectional view of the main parts inside an IC chip. Symbol 1 is silicon oxide film,
2 is polycrystalline silicon, 3 is a positive resist, and 4 is a silicon oxide film containing phosphorus.

In the embodiment shown in Fig. 1, the first etching (Fig. 1 (d)
)) is not etched at all (L-1+ or L-
1 □) is finished finely due to the loading effect in the rough part of the pattern (L-1, as shown), but this part is etched for the second time (Fig. 1 (h)).
Since this changes to the part that is etched (corresponding to 1), the loading effect works to make it thicker, canceling out the first loading effect.

Here, since the loading effect of dry etching is canceled out as a result, variations in etching size within the chip can be suppressed. In addition, since dry etching is basically anisotropic, it is more effective with fine patterns.

In addition, since a very thin film of different nature is formed between the same layers to be etched, it is easy to control the end point of the first dry etching, and the thickness of the layer to be etched can be easily controlled in the patterning of the layer to be etched to be finally formed. can be adjusted to standard values with high accuracy.

In FIG. 1(a), a polycrystalline silicon layer 2 of 5100 μm is deposited on a silicon oxide film 1 by thermal decomposition of monosilane (SiH) at 600° C. or higher, and phosphorous oxychloride (POC) is deposited on the silicon oxide film 1.
1), phosphorus is thermally diffused into the polycrystalline silicon layer 2 at about 900° C., and the resistance of the polycrystalline silicon layer 2 is set to about 10Ω/min. At this time, the thickness of the polycrystalline silicon layer 2 is 5000 Å, and there is silicon oxide 114 containing phosphorus formed during phosphorus diffusion on the surface.

Next, 5,000 layers of polycrystalline layer 2 were deposited again on the silicon oxide film containing phosphorus by thermal decomposition of monosilane (S i H4) at 60°C or higher, and after coating the positive type cyst 3, A patterned reticle is used to expose and image (FIG. 1(b)).

The upper polycrystalline silicon 2 is dry etched using fluorine (F) based gas in plasma (FIG. 1(C)).

The end point of etching at this time is accurate and simple, as it is the time when the gas species in the etching device rapidly changes, ie, when the silicon oxide film containing phosphorus begins to be etched.

FIG. 1(d) shows the silicon oxide film 4 containing carbon dioxide etched in a Fluoride II (HF) based aqueous solution and the positive resist 3 removed in a sulfuric acid based solution.

Apply a positive resist to a thickness of about 20,000A to ensure that the surface of the resist is open-hearth (Figure 1 (e)).The resist at this time may be a negative resist as it is not exposed to light.Fluorine (F) in plasma and dry etching the entire surface of DiS 1-3 using a positive type in a gas containing oxygen (0),
The resist 1- is left only in the groove of the upper polycrystalline silicon layer (FIG. 1(f)).

In plasma, the polycrystalline silicon 2 on the upper layer side, the silicon oxide film 4 containing 200A of phosphorus in the middle, and the polycrystalline silicon 2 on the lower layer side are dry-etched all at once using a F-based gas (see Fig. 1(g)). )).

After forming a positive mold, the film 1-3 is peeled off, and the pattern shown in FIG. 1(h) is completed, and the patterning is completed.

The present invention can be applied not only to offset the loading effect caused by the spacing of patterns, but also to suppress etching variations within the wafer surface of the dry etching equipment itself.Furthermore, since it does not depend on the type of film, it can be widely used. It can be applied to various dry etched films.

[Advantageous Effects of the Invention 1] As described above, the present invention has the effect of suppressing variations in etching dimensions and making element characteristics uniform within an IC chip and between chips, in order to offset the loading effect of dry etching.

[Brief explanation of drawings]

FIGS. 1(a) to (h) show embodiments of the present invention.
Cross-sectional view of the main parts inside the chip. FIGS. 2(a) to 2(c) are sectional views of main parts inside an IC chip, showing a conventional method. l... Silicon oxide film 2...Polycrystalline silicon 3...Positive resist 4...Silicon oxide film containing phosphorus Once (α) Constant til(,!J-Slightly once() c) Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) Proverb f diagram (d
) Magazine 1@Ce) Iku 1 item (+) Senior 1 drawing (Riwabandai) included (0-2 12 units (1>

Claims (1)

[Claims] A very thin film of a type different from the layer to be etched is formed on the layer to be etched, a film of the same type as the layer to be etched is formed on the thin film, and a resist is applied on the same type of layer as the layer to be etched, contrary to the usual method. After patterning, dry etching the same type of film as the layer to be etched and the thin film to form an etching groove, and after removing the resist, apply a resist again and etch the entire surface of the resist so that the resist remains only in the etching groove. A semiconductor manufacturing method characterized by dry etching layers according to a predetermined pattern.