JPS5994844A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5994844A
JPS5994844A JP20571682A JP20571682A JPS5994844A JP S5994844 A JPS5994844 A JP S5994844A JP 20571682 A JP20571682 A JP 20571682A JP 20571682 A JP20571682 A JP 20571682A JP S5994844 A JPS5994844 A JP S5994844A
Authority
JP
Japan
Prior art keywords
oxide film
film
oxidation
nitride silicon
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20571682A
Other languages
Japanese (ja)
Inventor
Toru Suganuma
菅沼 徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP20571682A priority Critical patent/JPS5994844A/en
Publication of JPS5994844A publication Critical patent/JPS5994844A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To make the element finer and higher integrated by a method wherein an oxide film separating process preventing or restricting a projecting or a inroading of a field oxide film into an element region from occuring is performed. CONSTITUTION:An oxide film 2 and a nitride silicon film 3 are formed on a silicon substrate 1 to be etched leaving the nitride silicon film 3 only in the element forming region. Then the oxide film 2 is selectively removed exposing the silicon substrate 1 to enter slightly into the part right below the end of the nitride silicon film 3. Another nitride silicon film is formed on the surface of a field region to be selectively removed forming the other nitride silicon film 5'. Then a field oxide film 4 is formed by thermal oxidation. In such a constitution, any bird beak and bird head may be prevented or restricted from occuring since the nitride silicon films 5' restrict any oxidation at the ends.

Description

【発明の詳細な説明】 本発明は、半導体装置の製造方法に関し、特に酸化膜を
用いて素子を分離する酸化膜分離法の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in an oxide film isolation method for isolating elements using an oxide film.

近年、IC−?LSI等の製造においては各素子間を電
、気的に分離する方法として酸化膜分離法が多く用いら
れている。これは窒化珪素(SiaN4)膜をマスクと
して半導体基板の表面を選択的に酸化するものである。
In recent years, IC-? In the manufacture of LSIs and the like, an oxide film isolation method is often used as a method of electrically and gaseously isolating each element. This is to selectively oxidize the surface of a semiconductor substrate using a silicon nitride (SiaN4) film as a mask.

第1図(a)〜(C)は従来の酸化膜分離法を説明する
ための工程断面図である。
FIGS. 1A to 1C are process cross-sectional views for explaining a conventional oxide film separation method.

まず、第1図(a) K示すように、シリコン基板1の
表面に酸化膜2を設け、その上にCVD法により窒化珪
素膜3を堆積する。
First, as shown in FIG. 1(a) K, an oxide film 2 is provided on the surface of a silicon substrate 1, and a silicon nitride film 3 is deposited thereon by the CVD method.

次に、第1図(b)に示すようI/c%窒化珪素83゜
酸化膜2を素子形成領域にのみ残すようにパターニング
する。
Next, as shown in FIG. 1(b), the I/c% silicon nitride 83° oxide film 2 is patterned so as to remain only in the element formation region.

次に、第1図(C)に示すように、熱酸化を行ってフィ
ールド酸化膜4を形成する。
Next, as shown in FIG. 1C, field oxide film 4 is formed by thermal oxidation.

しかしながらこの従来方法では、第1図(C)に示すよ
うにフィールド酸化膜4の端部にバーズヘッドと称され
る隆起Aとバーズビークと称される素子領域への食い込
みBを生じる。この隆起Aは配線の段切れの原因となり
、又食い込みBは素子領域の寸法を設計値からずらせ、
素子の微細化・高集積化の妨げになるという欠点があっ
た。
However, in this conventional method, as shown in FIG. 1C, a protuberance A called a bird's head and a bite B into the device region called a bird's beak occur at the end of the field oxide film 4. This protrusion A causes a break in the wiring, and the bite B causes the dimensions of the element area to deviate from the design value.
This has the disadvantage that it hinders the miniaturization and high integration of elements.

本発明は上記欠点を除去し、フィールド酸化膜の隆起や
素子領域への食い込みを防止ないし抑制できる゛酸化膜
分離法を開発し、素子の微細化、高集積化をはかった半
導体装置の製造方法を提供するものである。
The present invention eliminates the above-mentioned drawbacks and develops an oxide film separation method that can prevent or suppress the protrusion of the field oxide film and its encroachment into the device area, and a method for manufacturing semiconductor devices that achieves miniaturization and high integration of devices. It provides:

本発明の半導体装置の製造方法は、半導体基板上に酸化
膜を形成し、該酸化膜上に第1の耐酸化性膜を形成する
工程と、前記耐酸化性膜ならびに酸化膜全選択的に除去
する工程と、露出している半導体基板のフィールド領域
端部に選択的に薄い第2の窒化膜を形成する工程と、熱
酸化を行って前記露出している半導体基板にフィールド
酸化膜を形成する工程と、前記第1及び第2の耐酸化性
膜を除去して素子を形成する工程とを含んで構成される
The method for manufacturing a semiconductor device of the present invention includes the steps of forming an oxide film on a semiconductor substrate, forming a first oxidation-resistant film on the oxide film, and selectively controlling all of the oxidation-resistant film and the oxide film. selectively forming a thin second nitride film on the exposed edge of the field region of the semiconductor substrate; and forming a field oxide film on the exposed semiconductor substrate by performing thermal oxidation. and a step of removing the first and second oxidation-resistant films to form an element.

次に、本発明の実施列について図面を用いて説明する。Next, embodiments of the present invention will be explained using the drawings.

第2図(a)〜(e)は本発明の第1の実施例を説明す
るための主な製造工程における断面図である。
FIGS. 2(a) to 2(e) are cross-sectional views showing main manufacturing steps for explaining the first embodiment of the present invention.

まず、第2図(a)VC示すように、シリコン基板1の
上に熱酸化により酸化膜2を50OAの厚さに形成し、
その上に耐酸化性膜として窒化珪素膜3をCVD法によ
り100OAの厚さに形成する。
First, as shown in FIG. 2(a) VC, an oxide film 2 with a thickness of 50 OA is formed on a silicon substrate 1 by thermal oxidation.
Thereon, a silicon nitride film 3 is formed as an oxidation-resistant film to a thickness of 100 OA by CVD.

次に、第2図(b)に示すように、通常のフォトレジス
トv用いる写真食刻法により、素子形成領域にのみ窒化
珪素膜3を残すようにドライエツチングする。次に、窒
化ケイ素膜3をマスクとして弗et用いるウェットエツ
チング法で酸化膜2を選択除去する。このとき、多少オ
ーバーエッチさせて窒化珪素膜3の端部直下の内側に少
し入シ込むようにシリコン基板表面を露出させることが
重要である。
Next, as shown in FIG. 2(b), dry etching is performed by photolithography using a normal photoresist V so that the silicon nitride film 3 is left only in the element formation region. Next, the oxide film 2 is selectively removed by wet etching using a film using the silicon nitride film 3 as a mask. At this time, it is important to expose the surface of the silicon substrate by slightly over-etching so as to penetrate slightly inside the silicon nitride film 3 just below the edge.

次に、第2図(C)に示すように、露出したシリコン基
板のフィールド領域表面に、第2の耐酸化性膜として窒
化珪素膜5を形成する。第2の耐酸化性膜としての窒化
珪素膜5の厚さは、後に形成するフィールド酸化膜の厚
さによって異なる。通常は数十へ〜数百への値である。
Next, as shown in FIG. 2C, a silicon nitride film 5 is formed as a second oxidation-resistant film on the exposed surface of the field region of the silicon substrate. The thickness of silicon nitride film 5 as the second oxidation-resistant film varies depending on the thickness of the field oxide film to be formed later. Usually values are in the tens to hundreds.

窒化珪素膜5は、超高純度をアンモニアガスを用い、1
000°0でシリコン基板を窒化することにより形成す
る。
The silicon nitride film 5 is made using ultra-high purity ammonia gas.
It is formed by nitriding a silicon substrate at 000°0.

次に、第2図fd)に示すように、異方性エツチング法
により窒化珪素膜5を選択除去し、窒化珪素膜3の直下
にのみ窒化珪素膜5′ヲ形成する。
Next, as shown in FIG. 2fd), the silicon nitride film 5 is selectively removed by an anisotropic etching method, and a silicon nitride film 5' is formed only directly under the silicon nitride film 3.

次に、第2図(e)に示すように、熱酸化を行い、厚さ
1μmのフィールド酸化膜4を形成する。このときフィ
ールド領域端部で残された窒化珪素膜5′が端部での酸
化の進行を抑える結果、図示するよウニ、バーズビーク
及びバーズヘッドが防止ナイしは抑制される。
Next, as shown in FIG. 2(e), thermal oxidation is performed to form a field oxide film 4 with a thickness of 1 μm. At this time, the silicon nitride film 5' left at the end of the field region suppresses the progress of oxidation at the end, thereby suppressing the formation of sea urchins, bird's beaks, and bird's heads as shown in the figure.

第3図(a)、 (b)は本発明の第2の実施例を説明
するための主な製造工程における断面図である。
FIGS. 3(a) and 3(b) are cross-sectional views showing the main manufacturing steps for explaining the second embodiment of the present invention.

第1の実施例と同じ方法を用いて第2図(d)に示す構
造のものを形成する。
The structure shown in FIG. 2(d) is formed using the same method as in the first embodiment.

次に、第3図fa)に示すように、シリコン基板1を異
方性エツチング法によりエツチングする。
Next, as shown in FIG. 3fa), the silicon substrate 1 is etched by an anisotropic etching method.

次に、第3図(b)に示すように、熱酸化してフィール
ド酸化膜4を形成する。このようにすると、フィールド
酸化膜4の段差を極めて小さくすることができ、エツチ
ング深さと酸化条件をうまく調整すると段差をなくすこ
ともできる。
Next, as shown in FIG. 3(b), a field oxide film 4 is formed by thermal oxidation. In this way, the step difference in the field oxide film 4 can be made extremely small, and by properly adjusting the etching depth and oxidation conditions, the step difference can be eliminated.

以上詳細に説明したように、本発明によれば、バーズビ
ークやバーズヘッドの発生を抑制し、素子領域への酸化
物の食い込みを抑制する酸化膜分離ができ、素子の微細
化、高準積化をはかった半導体装置の製造方法が得られ
るのでその効果は大きい。
As explained in detail above, according to the present invention, it is possible to perform oxide film separation that suppresses the occurrence of bird's beaks and bird's heads, and suppresses the penetration of oxide into the element region, and allows for miniaturization and high quasi-integration of elements. This method has a great effect because it provides a method for manufacturing a semiconductor device that achieves this.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(C)は従来の酸化膜分離法を説明する
ための工程断面図、第21’g(a1〜(e)は本発明
の第1の実施例全説明するための工程断面図、第3図(
a)。 (b)は本発明の第2の実施例を説明するための工程断
面図である。 1・・・・・シリコン基板、2・・川・熱酸化膜、3・
川・・窒化珪素膜、4・・・・・・フィールド酸化膜、
 5.5’・・・・・・窒化珪素膜。 グ ー/ (e) 牛2 図 (σ2 第3 図
1(a) to (C) are process cross-sectional views for explaining the conventional oxide film separation method, and FIGS. 21'g(a1 to (e) are cross-sectional views for explaining the entire first embodiment of the present invention. Process cross-sectional diagram, Figure 3 (
a). (b) is a process sectional view for explaining the second embodiment of the present invention. 1...Silicon substrate, 2...River/thermal oxide film, 3...
River: silicon nitride film, 4: field oxide film,
5.5'...Silicon nitride film. Goo / (e) Cow 2 Figure (σ2 Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に酸化膜を形成し、該酸化膜上に第
1の耐酸化性膜を形成する工程と、前記耐酸化性膜なら
びに酸化膜全選択的に除去する工゛程と、露出している
半導体基板のフィールド領域端部に選択的に薄い第2の
窒化膜を形成する工程と、熱酸化を行って前記露出して
いる半導体基板にフィールド酸化膜を形成する工程と、
前記第1及び第2の耐酸化性膜全除去して素子を形成す
る工程とを含むことを特徴とする半導体装置の製造方法
(1) forming an oxide film on a semiconductor substrate, forming a first oxidation-resistant film on the oxide film; and selectively removing all of the oxidation-resistant film and the oxide film; selectively forming a thin second nitride film on the exposed edge of the field region of the semiconductor substrate; performing thermal oxidation to form a field oxide film on the exposed semiconductor substrate;
A method for manufacturing a semiconductor device, comprising the step of completely removing the first and second oxidation-resistant films to form an element.
(2)前記第2の耐酸化性膜がアンモニアガスを用いて
窒化することにより形成される特許請求の範囲第(1)
項記載の半導体装置の製造方法。
(2) Claim No. 1, wherein the second oxidation-resistant film is formed by nitriding using ammonia gas.
A method for manufacturing a semiconductor device according to section 1.
(3)前記第2の耐酸化性膜が異方性ドライエッチソゲ
法によシ前記第1の耐酸化性膜の直下にのみ残るように
選択除去して形成される特許Iff求の範囲第(1)項
記載の半導体装置の製造方法。
(3) The second oxidation-resistant film is selectively removed by an anisotropic dry etching method so that it remains only directly under the first oxidation-resistant film. A method for manufacturing a semiconductor device according to item (1).
JP20571682A 1982-11-24 1982-11-24 Manufacture of semiconductor device Pending JPS5994844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20571682A JPS5994844A (en) 1982-11-24 1982-11-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20571682A JPS5994844A (en) 1982-11-24 1982-11-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5994844A true JPS5994844A (en) 1984-05-31

Family

ID=16511504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20571682A Pending JPS5994844A (en) 1982-11-24 1982-11-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5994844A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213047A (en) * 1985-07-10 1987-01-21 Matsushita Electronics Corp Manufacture of semiconductor device
JPS63244627A (en) * 1987-03-30 1988-10-12 Mitsubishi Electric Corp Manufacture of semiconductor device
US5504034A (en) * 1992-09-23 1996-04-02 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Local oxidation method with bird's beak suppression

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213047A (en) * 1985-07-10 1987-01-21 Matsushita Electronics Corp Manufacture of semiconductor device
JPS63244627A (en) * 1987-03-30 1988-10-12 Mitsubishi Electric Corp Manufacture of semiconductor device
US5504034A (en) * 1992-09-23 1996-04-02 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Local oxidation method with bird's beak suppression

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