JPS63240648A - Data compressing/storing system - Google Patents

Abstract

PURPOSE:To decrease the quantity of stored data by performing simultaneously the comparison of data of the same pattern with plural word width and then compressing the data with plural word widths. CONSTITUTION:A data latch circuit stores temporarily the (nX2)-word data and a (1-n)-word comparator compares the patterns of the (1-n)-word data and its following (1-n)-word data with each other. A priority deciding circuit 10 counts the repeating frequency of the same pattern every (m) words or counts the word number of the discontinuous data trains according to a fact whether the priority should be given to an m-word comparator based on the result of said comparison. Then a control circuit 11 decides whether the compressed word width data and the compressed code data or the compressed word width data and the discontinuous word number are added at the head of the data train and stored. In such a way, the same patterns are compared with each other with plural word widths and the quantity of stored data can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data compression storage system, and more particularly to a data compression storage system for compressing and storing data in a storage device or the like in an information processing apparatus.

(Prior Art) Conventionally, this type of data compression storage method uses data of a certain word width, for example, data of one word width, as one data, and determines whether the same pattern of data is repeated. For a data string in which n (positive integer) data of a pattern continues consecutively, it is expressed by a focus indicating that the data of the same pattern is repeated, the number of repetitions n, and the repeated data, and the data of the same pattern is not consecutive. Regarding data strings (hereinafter referred to as discontinuous data strings), by representing the number of data in which data of the same pattern is not consecutive and the discontinuous data strings,
The method was to reduce the amount of data compared to normal and store it in a storage device or the like.

[Problem that the invention seeks to solve]

The conventional data compression storage method described above determines whether or not the same pattern is repeated only for data with a fixed word width. It was possible to compress data, but it was not possible to compress a data string that repeated the same pattern with a word width multiple times the word width, and a word with a data string that could be compressed with other word widths. The disadvantage is that it cannot be compressed by width.

In view of the above-mentioned points, an object of the present invention is to provide a data compression storage in which data can be compressed in a plurality of word widths by making it possible to simultaneously compare the same pattern in a plurality of word widths. The goal is to provide a method.

[Means for solving problems]

The data compression storage method of the present invention includes a data launch circuit that temporarily holds data of n (positive integer) x 2 words, and 1 x 2 words of data held in this data launch circuit, counting from the first word of the A 1-word comparator to an n-word comparator that compares data of a word to n words with data of the following <1 word to n words to see if they have the same pattern; Based on the comparison result of the word comparator, m (1≦m
≦ positive integer of n) A priority determination circuit that gives priority to a word comparator or does not give priority to any comparator, and a case where priority is given to m word comparators by this priority determination circuit. is a counter that counts the number of times the same pattern is repeated every m words, and if priority is not given to any comparator, counts the number of words in a discontinuous data string, and the priority determination circuit calculates the number of repetitions of the same pattern. When priority is given to a comparator, compressed word width data corresponding to the m-word comparator and compressed code data consisting of the number of repetitions of the same pattern, which is the count value of the counter, are added to the beginning of the m-word data. If the priority determination circuit does not give priority to any of the comparators, compressed word width data indicating no compression and the number of discontinuous words which is the count value of the counter are stored. and a control circuit that stores a discontinuous data string by adding the following to the beginning.

[Effect]

In the data compression storage method of the present invention, the data latch circuit temporarily holds data of n (positive integer) x 2 words, and
A word comparator or an n-word comparator outputs l to n words of data, counting from the first word of the n×2 words of data held in the data launch circuit, and the following 1.
The data of the word to n word are compared to see if they have the same pattern, and the priority determination circuit determines whether the data has the same pattern as m(
(Positive integer of 1≦m≦n) Give priority to the word comparator or give priority to no comparator, and if the counter gives priority to the m word comparator by the priority determination circuit. counts the number of repetitions of the same pattern every m words, and if priority is not given to any comparator, counts the number of words in the discontinuous data string, and the control circuit compares the m words using the priority determination circuit. When priority is given to the m-word comparator, compressed word width data corresponding to the m-word comparator and compressed code data consisting of the number of repetitions of the same pattern, which is the count value of the counter, are added to the beginning of the m-word same pattern. If the data is written tα and the priority determination circuit does not give priority to any comparator, compressed word width data indicating no compression and the number of discontinuous words, which is the count value of the counter, are added to the beginning. to store a discontinuous data string.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The data compression storage method of this embodiment shows an example in which one word is one byte (8 bits) and the maximum word width n that allows comparison of matching of the same pattern is three. This data compression storage system consists of 5 (=n
, a control circuit 11 , a counter 12 , and a switching circuit 13
and a memory circuit 14.

Data launch circuits 1 to 6 are launch circuits each holding 1 byte of data, and are sequentially connected in series from data latch circuit 1 at the first stage to data latch circuit 6 at the final stage. A data bus 21 carrying input data to be stored is connected to the input of the data latch circuit l in the first stage, and data launch circuits 1 to 6 sequentially send input data from the data bus 21 to the data latch circuit in the subsequent stage. However, a total of 6 bytes of input data is temporarily held. The outputs of each data launch circuit 1-6 are connected to data latch buses 22-27 carrying latch data, respectively.

The 1-byte comparator 7 has inputs connected to the data latch bus 26 and the data latch bus 27, respectively, and compares the 1-byte data on the data launch bus 26 with the 1-byte data on the data latch bus 27 to determine whether they match. In some cases, a 1-byte comparison match signal indicating this fact is output as the 1-byte comparison match signal vA31.

The 2-byte comparator 8 has inputs connected to data latch buses 24 and 25 and data latch buses 26 and 27, respectively, and has inputs connected to two of the data latch buses 24 and 25.
Compares the byte data with the 2-byte data on the data latch buses 26 and 27 and indicates when they match.
A byte comparison match signal is output to the 2-byte comparison match signal line 32.

The input of the 3-byte comparator 9 is the data latch bus 22, 2.
3 and 24 and data latch bus 25.26 and 27
are connected to the data latch buses 22 .
23 and 24 3-byte data and data latch bus 2
5. Compare the 3-byte data of 26 and 27 and when they match, output a 3-byte comparison match signal indicating that fact to the 3-byte comparison match signal line 33.

The priority determination circuit 10 has inputs connected to a 1-byte comparison match signal line 31, a 2-byte comparison-defeat signal line 32, and a 3-byte comparison-defeat signal line 33, and connects the 1-byte comparison match signal lines 31, 2 A comparator that determines the priority of the 1-byte comparison match signal, 2-byte comparison-defeat signal, and 3-byte comparison-defeat signal on the byte comparison match signal line 32 and the 3-byte comparison-defeat signal line 33 and gives priority. number 2
Coincidence comparator number data expressed in bits is output to a 2-bit coincidence comparator number data bus 29. That is, when giving priority to the 1-byte comparator 7, the priority determination circuit IO assigns "Ol" (a number enclosed in " indicates a binary number, the same applies hereinafter) to the 2-byte comparator 7. When giving priority to 8, "10" is output to the coincidence comparator number data bus 29, and when giving priority to 3-byte comparator 9, "11" is output to the coincidence comparator number data bus 29. If neither the 2-byte comparison match signal nor the 3-byte comparison match signal is output and priority is not given to any comparator, the priority determination circuit IO outputs "OO" to indicate that. is output to the coincidence comparator number data bus 29 as coincidence comparator number data.

The control circuit 11 inputs the match comparator number data hash 29.
It holds the match comparator number data on the -defeat comparator number data bus 29 and instructs to write a counter count instruction signal to the counter count instruction line 34 and a switching instruction signal to the switching instruction line 35. A write instruction signal is output to line 36, write address data is output to write address data bus 37, and compressed word width data is output to compressed word width data bus 38.

The counter 12 is connected manually to a counter count instruction line 34, and counts the number of repetitions of the same pattern of m words or the number of words of a discontinuous data string based on a counter count instruction signal from the counter count instruction line 34. The count value is output to the 6-bit compressed word count data bus 30.

The switching circuit 13 receives compressed code data of 1 byte (8 bits) width, which is a combination of the 2-bit compressed word width data bus 38 and the 6-bit compressed word number data bus 30, at one input, and the other input. data latch bus 27
is connected. In addition, the command line 35 is switched to the control input.
is connected. The switching circuit 13 connects the switching instruction line 3
The compressed code data and the data from the data latch bus 27 are selectively switched based on the switching instruction signal from the data latch bus 27 and output to the write data bus 28.

The storage circuit I4 writes and stores the data on the write data bus 28 at the address specified by the write address data bus 37 based on the write instruction signal from the write instruction line 36.

Referring to FIG. 2, the compressed code data in the data compression storage method of this embodiment is composed of 1 byte (8 bits), and bits 0 and 1 indicate the compressed word width.
Bits 2 to 7 indicate the number of repetitions of the same pattern of compressed word width data indicated by bits O and l.

Next, the operation of the data compression storage system of this embodiment configured as described above will be explained.

(1) When data of the same pattern is not consecutive The first data sent is held in the data latch circuit 6, the next data sent is held in the data latch circuit 5, and the following 3 to 6 bytes are held in sequence. The second data is held in data latch circuits 4 to 1, respectively, and a total of 6 bytes of data is held in data latch circuits 1 to 6.

In this state, the 1-byte comparator 7 compares the 1-byte data of the data launch circuit 6 with the 1-byte data of the data latch circuit 5, and the 2-byte comparator 8 compares the 2-byte data of the data latch circuits 6 and 5. and the 2-byte data of data launch circuits 4 and 3 are compared with each other, and the 3-byte comparator 9 compares the 3-byte data of data latch circuits 6.5 and 4 with the 3-byte data of data latch circuits 3.2 and I. Bytes of data are compared with each other.

Now, since the data of the same pattern is not consecutive, 1-byte comparators 7, 2-byte comparators 8 and 3
All of the byte comparators 9 detect data mismatches. Therefore, the 1-byte comparison match signal, the 2-byte comparison match signal, and the 3-byte comparison match signal output to the 1-byte comparison match signal line 31, the 2-byte comparison-defeat signal line 32, and the 3-byte comparison-defeat signal line 33, respectively. 0'', and the priority determination circuit 10 outputs "00'" to the coincidence comparator number data bus 29 as coincidence comparator number data.

The control circuit 11 inputting the coincidence comparator number data “00” on the coincidence comparator number data path 29 holds this coincidence comparator number data “OO” and outputs a switching instruction signal to the switching instruction line 35. The switching circuit 13 is instructed to select the data latch bus 27. Upon receiving the switching instruction signal, the switching circuit 13 switches to output the data on the data launch bus 27 to the write data bus 28.

The control circuit 11 also controls the write address data bus 37.
The write address data is outputted to instruct the storage circuit 14 of the write address. Note that the control circuit 11 is
The address for storing compressed code data is held as a write address, and addressing is performed sequentially starting from the next address.

Further, the control circuit 11 outputs a write instruction signal to the write instruction line 36 to send the write data bus 28 to the memory circuit 14.
It instructs the counter 12 to write the above data, and outputs a counter count instruction signal to the counter count instruction line 34 to instruct the counter 12 to perform counting. Therefore, only one byte of data of the discontinuous data string is written into the memory circuit 14, and the counter 12 counts by one.

The value of the counter 12 is cleared to zero via the control circuit 12 when the value of the match comparator number data on the -defeat comparator number data bus 29 changes.

When the 1-byte data latched by the data latch circuit 6 is written into the memory circuit 14, each data launched in the previous stage data latch circuit is transferred to the next stage data launch circuit, and the data is transferred to the first stage data latch circuit. New 1-byte data supplied from the data bus 21 is held in the circuit l.

Processes similar to those described above are performed sequentially, and the data of the discontinuous data string is written into the storage circuit 14 one after another in I-hyde units.

In this state, when any one of the 1-byte comparator 7, 2-byte comparator 8, and 3-byte comparator 9 detects a data match, the priority determination circuit 1O sends the match comparator number data bus 29 Change the match comparator number data output from "oo" to another value.

When the control circuit 11 detects that the coincidence comparator number data from the coincidence comparator number data bus 29 has changed, the control circuit 11 writes an address for storing the held compressed code data δ onto the address data bus 37. The held match comparator number data "00" is output as compressed word width data on the compressed word width data bus on the third day. Further, the control circuit 11 outputs a switching instruction signal to the switching instruction line 35 to output the 2-bit compressed word width data on the compressed word width data bus 38 and the compressed word number data bus 3.
The switching circuit 13 is instructed to select the compressed code data obtained by combining the compressed word number data above 0. Further, the control circuit 11 instructs the tα circuit 14 to perform recessing via the write instruction line 36.

As a result, the compressed code data is written to the first address position in the storage circuit 14 where the discontinuous data string has been written.

(21m (rn is a positive integer of l≦m≦n) When data with the same pattern of hide width is consecutive When the m-byte comparator detects that m-byte-wide data match, it sends an m-byte comparison-defeat signal. Compare m bytes - Output to the failure signal line.

The priority order determination circuit 1O determines the priority order when a plurality of comparison-defeat ε numbers are input, and transmits the match comparator number data corresponding to the comparator to which priority is given to the match comparator number data bus 29. Output to. Here, the coincidence comparator number data output to the coincidence comparator number data bus 29 is assumed to be m.

The control circuit 11 that receives the coincidence comparator number data m from the coincidence comparator number data bus 29 holds the coincidence comparator number data m and writes the data without issuing a write instruction to the memory circuit 14 via the write instruction line 36. m of latch circuits 1 to 6
The data for bytes is sent to the data launch circuit of the next stage and subsequent stages, and the input data for m hides is received from the data bus 21. Also, 1llll? The 11 circuit 11 outputs a counter count instruction signal to the counter count instruction line 34 every m bytes, so that the counter 12 counts by 1 every m bytes.

Processing similar to that described above is performed continuously until the coincidence comparator number data on the coincidence comparator number data path 29 changes from m to another value.

Here, when the match comparator number data on the match comparator number data bus 29 changes to a value other than m, the control circuit 11 transfers the held match comparator number data m to the compressed word width data bus 3. output as data and output a switching instruction signal to the switching instruction line 35 to instruct the switching circuit 13 to select compressed code data that is a combination of the compressed word width data bus 38 and the compressed word number data bus 30. .

The switching circuit 13 instructed to select the compressed code data by the switching instruction line 35 outputs the compressed code data to the write data bus 28 . In addition, the control circuit 11
Instructs the memory circuit 14 to write using the write 1 indication line 36. As a result, compressed code data is written into the storage circuit 14.

Next, the control circuit 11 outputs a switching instruction signal to the switching instruction line 35 to send the data latch bus 27 to the switching circuit 13.
The memory circuit 14 instructs the selection of m-hide data from the data launch circuit on the subsequent stage successively from the address following the address where the compressed yaw 1 data of the memory circuit 14 is written.
I will write it in. That is, m bytes of data of the same pattern are written into the storage circuit 14.

In the data compression storage system of the present embodiment, manual data can be compressed and stored in the storage circuit 14 by appropriately repeating the processes (1) and (2) above.

FIG. 3 is a diagram showing an example of the relationship between input data and compressed data. In this example, bytes O to 3 of the input data
is compressed code data “04” as a discontinuous data string,
(The numbers enclosed in squares are hexadecimal numbers.

) is added to the beginning and stored in bytes θ to 4 of the compressed data. Bytes 4 to 9 of the input data are "FFDF" with compression code data "83" added to the beginning indicating that 2-byte wide data is consecutive three times.
"+1" is compressed and stored in bytes 5 to 7 of the compressed data. Bytes 10 to 7 of the input data
15 is "A" with compressed code data "C2" added to the beginning indicating that 3-byte wide data is consecutive twice.
A55DB" and is stored in bytes 8 to 11 of the compressed data. Bytes 16 to 19 of the input data are compressed data indicating that 1-byte wide data is consecutive four times. Code data "44" □ is compressed into data "00" 8 added to the beginning and stored in hides 12 and 13 of the compressed data.In this way, in this example, the number of input data is 20. In contrast, the number of data after compression is 14, reducing the number of stored data.

By the way, when reading data compressed and stored by the data compression storage method of this embodiment from the storage circuit 14,
Check the compressed word width data of bits O and l in the compressed code data, and if it is "00", output the number of bytes indicated by the number of repetitions of the same pattern in bits 2 to 7, and output "01".
”, then output the next 1 byte data for the number of times the same pattern is repeated, 1O”, output the next 2 bytes of data for the same pattern repeat times, and “11”, output the next 3 bytes of data for the same pattern. Output for the number of repetitions.

In addition, in the above embodiment, one word is one byte (8 bits), and the maximum word width n that allows comparison of one defeat of the same pattern is
An example has been described in which the number is 3, but it goes without saying that 1 word does not necessarily have to be 1 byte, and the maximum word width n that allows comparison of matches of the same pattern does not need to be 3.

Furthermore, although the compressed word width data is shown in 2 bits, if the maximum word width n that allows matching of the same pattern to be compared is increased, a correspondingly larger number of bits will be required. -Finally, if the maximum word width that allows matching of the same pattern to be compared is n, then the number of bits of compressed word width data is (1+[iogzn]) bits.

〔Effect of the invention〕

As explained above, the present invention includes a number of data latch circuits twice the maximum word width that can compare matches of the same pattern, an l-word comparator or an n-word comparator that compares one failure of the same pattern, By providing a priority determination circuit for these comparators, a counter that counts the number of repetitions of the same pattern and the number of discontinuous words, and a control circuit that controls the write operation, the same pattern can be compared simultaneously across multiple word widths. This has the effect of further reducing the amount of stored data compared to the case where data compression is determined based on a fixed word width.

[Brief explanation of drawings]

FIG. 1 is a program diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of the structure of compressed code data in the data compression storage method of this embodiment, and FIG. 3 is a diagram showing data of this embodiment. FIG. 2 is a code configuration diagram showing an example of the relationship between input data and compressed data using a compression storage method. In the figure, 1 to 6: data launch circuit, 7: 1-byte comparator, 8: 2-byte comparator, 9: 3-byte comparator, io: priority determination circuit, 11... -Control circuit, 12...Counter, 13...Switching circuit, 14...Storage circuit, 21...Data bus, 22-27-Data launch bus, 28...Write data bus, 29... - Match comparator number data path, 30... Compressed word number data bus, 31... 1 byte comparison match signal line, 32... 2 byte comparison - failure signal line, 33... 3 byte comparison match signal 34...Counter count instruction line, 35...Switching instruction line, 36...Write instruction line, 37...Write address data bus, 38...Compressed word width data bus.

Claims (1)

[Claims] A data latch circuit that temporarily holds n (positive integer) x 2 words of data, and 1 word counted from the first word of the n x 2 words of data held in the data latch circuit. A 1-word comparator to an n-word comparator that compares 1 to n words of data with the following 1 to n words of data to see if they have the same pattern; and 1-word to n-word comparisons. a priority determination circuit that gives priority to m (a positive integer of 1≦m≦n) word comparators or does not give priority to any of the comparators based on the comparison results of the comparators; If priority is given to m-word comparators, count the number of repetitions of the same pattern every m words; if priority is not given to any comparator, count the number of words in a discontinuous data string. and a counter consisting of compressed word width data corresponding to the m-word comparator when priority is given to the m-word comparator by the priority determination circuit, and the number of times the same pattern is repeated, which is the count value of the counter. Compressed word width data that adds compressed code data to the beginning and stores the same pattern data of the m words, and indicates that no compression is performed when the priority determining circuit does not give priority to any of the comparators. and a control circuit that stores a discontinuous data string by adding the number of discontinuous words, which is the count value of the counter, to the beginning.