JPS61256440A - Comparison processing system with mask - Google Patents

Abstract

PURPOSE:To perform a comparison processing with mask at high speed by having comparison partially or totally between the i-th byte of the 1st data distributed uncontinuously and the i-th and (i-1...0)-th bytes of the 2nd data distributed continuously. CONSTITUTION:Both output lines E10 and E11 of a decoder 5 are not set at '1' at a time and both byte comparators 10 and 11 are not activated simultaneously. Therefore both lines C10 and C11 are not equal to non-zero at a time. In the same way, >=2 among lines C20, C21 and C22 and >=2 among C30, C31 and C32 are not equal to non-zero at a time. While no AND circuit is obtained when a line C00 is equal to non-zero. Then the line C00 is delivered to a line CC. If non-zero exists on a line Cij, the line Cij having smaller (i) is delivered as the line CC. Thus the comparison is possible between the uncontinuous data 1 with a mask and the continuous data 2 according to the mask information 3 just through a single process without having the rearrangement of these data.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to comparison processing of masked data, and performs the comparison processing without performing rearrangement processing to replace masked discontinuously arranged data with continuous arranged data. The present invention relates to a masked comparison processing method suitable for.

[Background of the invention]

Conventionally, when comparing discontinuously arranged data with a mask and continuously arranged data, the method is to cut out the desired data one byte at a time, or replace the discontinuously arranged data with a mask with continuous arranged data and then compare. A method has been adopted. The latter method is often adopted because it is superior to the former in terms of processing speed.The latter method will be explained with reference to FIG.

Figure 1 is an example where the data width is 4 bytes.
This figure shows a processing device that compares the sizes of masked discontinuous arrangement data 1 rABcDJ and second continuous arrangement data 21EFG old. Now, the second data exists in the storage 101, and a normal aligner 102 positions the first byte of the desired data at the left end, outputs data equal to the number of effective bits (11') of mask information 3, and outputs the remaining data. In the example shown in the figure, the mass information is '0101' (the number of 1's is 2 = the number of bytes to be compared is 2 bytes), so the comparison should start from the left end of rEFGHJ. Number of bytes 2 bytes of data are selected, and 10' is embedded in the right 2 bytes ( rEFOO
(denoted by J).

The first data 1 is rearranged by the rearrangement circuit 100 according to the mask information 3. In the example of FIG.
Data rf3) and r(:)4 of the 1' portion of the mask information '0101' are extracted from ABCD J and arranged sequentially from the left end, and 0' is embedded in the remaining byte positions. Data after rearrangement obtained in this way 4 rBD
A size comparison is performed between OOJ and the second data 2r EFOOJ using a normal 4-byte comparator 103, and the rearranged data 4rBDOOJ and the second (7) data II
2 rEFOO" matches, set line CC to 0', data 4 (if data 2, set line CC to 11', data 4)
In the case of data 2, the line C (1'2') can be obtained. In this way, the desired comparison result can be obtained.

As an example of the relocation circuit 100, Japanese Patent Application Laid-Open No. 55-15150
Figure 2 shows the masked discontinuous arrangement data 1 of the circuit shown in Japanese Patent Application No. 54-20562.

A shifter 202 is used that allows digit movement in any direction.

According to the mask information 3, the first data 1 and the shifter 20
The data is rearranged by selecting one of the two outputs for each byte position.

The details of the control circuit 201 are explained in the same publication, so the explanation will be omitted here.

As described above, in the comparison process of masked non-continuous placement data, there are two steps: a step of once converting to continuous placement data using the relocation circuit 100, and a step of comparing continuous placement data. It was done. In the examples shown in FIGS. 1 and 2, a general-purpose 4-byte comparator 103 (a 4-byte adder/subtractor is also possible) and a general-purpose shifter 202 can be used, so it is necessary to add the Although this method has the advantage of requiring less hardware, it also has the disadvantage of requiring a processing step for once relocating the device, resulting in a long processing time.

[Purpose of the invention]

An object of the present invention is to provide a masked comparison processing method.

[Summary of the invention]

The present invention provides the i-th byte (i
=0,1. . . , N-4) and the i, 1-1e, . . . , O-th bytes of the consecutively arranged second data.

Based on the comparison results and mask information of each byte comparator,
This method is characterized by comparing the first and second data in terms of magnitude.

[Embodiments of the invention]

The first embodiment of the present invention is shown in FIGS. 3 and 4 below.

This will be explained with reference to FIGS. 5 and 6.

FIG. 3 is a block diagram showing the first embodiment of the present invention.
An example of a configuration when comparing byte-structured data is shown. First data 1 rABcDJ and second data 2
Mask information 3 (in this example, '010
1'), and if they match, line C
If the first data is smaller than the second data, the line CC is set to 1'; if the first data is larger than the second data, the line @CC is set to 2'.

The i-th byte of the first data 1 (i=o, 1, 2°3) and the j-th byte of the second data 2 Cj=Ov...

i), byte comparator 1j (ij=00, 10°11
．． 20, 21, 22, 30, 31, 32゜33) are provided, and the activation of these byte comparators is determined by the output EtJ (ij=oo, 1
0,11* 20,21°22.30,31,32.3
3). Byte comparator ij output CIJ
is sent to the magnitude relationship determination circuit 6, where CC is determined.

FIG. 4 is a diagram explaining the operation of the byte comparator ij in FIG. 3, where x and Y are 1-byte data, and E is an activation control line, which is inactive at 0' and activated at 1'. do, 2 is 10'
or 11' or (21 and E= 'O' or x=
When Y, z='o'.

When E= '1' and x<y, Z= '1', E=
When '1' and x>y, Z='2' operates.

FIG. 5 is a diagram explaining the operation of the decoder 5 of FIG.
Line El according to the 4-bit mask information.

is set to 10' or 11'.

FIG. 6 shows an example of the configuration of the magnitude relationship determination circuit 6 shown in FIG. As is clear from the decoder example of FIG. 5, the output lines E ifl and E1□ of the decoder 5 do not become Il+ at the same time, and the byte comparators lo and 11 are not activated at the same time. Therefore, the lines c1° and C11 will never both take a value of ≠'0'.Similarly, two or more of the lines C2I, C21, and C1 will not become ≠1 Or at the same time, and similarly, mc, , 031803m, and 033, two or more of them cannot be ≠l Ol at the same time. On the other hand, the line C0゜≠'0'
In this case, the AND circuits 81, 62, and 63 are not established, so the line C0° is output as is to #cc. Line C
,, = 'O' and which of the lines C1° and 081 is ≠
In the case of 'o', only the AND circuit 61 is established and the line cc
As a result, a value of ≠'0' for the line C1° or C11 is obtained.

Similarly, if lines c and J have ≠'o', the line cIJ with smaller i is drawn as the line cc,
If line C4J is all 0', 0' is output to line CC.

For example, if the mask information is '01 (H'), lines E□. and E31 become 1' and the others become 0' according to the decoding example in FIG. A comparison is made between the second data rBJ and the 0th byte data rEJ of the second data, and the byte comparator 31 compares the third byte rDJ of the first data with the first byte rFJ of the second data. A comparison is made and the respective results are reflected on the lines C1°, C1.Since all other byte comparators are inactivated, the lines C,.=C11=C2
o=cat=CB=can=cz,=c
sz = 'O'.

When rBJ ≠ "E", the line C1゜≠'0', so the magnitude relationship determination circuit in Fig. 6 outputs the line C8゜ as the line cc, and when rBJ = rEJ rpJ≠ "F", Line C4゜"'O' l cat≠g Oy, so line C31 is output as line CC, and rB4 = rE"
and "D) = [If FJ, line (:, , = #Q
#.

Since C, □='0', 10' is output as the line cc. In other words, it is the same as comparing the 2-byte data rBDJ and rEFJ, and the desired size comparison result is obtained on the line CC. Mask information 3 with data 2
The size comparison process according to the above can be executed in one step without rearrangement. Further, according to this embodiment, there is an effect that it is not necessary to embed "O" into unnecessary bytes of continuous arrangement data (the right two bytes in the example of mask information '0101').

The second embodiment will be explained with reference to FIGS. 7.8 and 9.10.

FIG. 7 is a block diagram showing a second embodiment of the present invention, also shown in a 4-byte structure.

The difference from the first embodiment lies in the alignment of the second continuous arrangement data 2. In the first example.

The first byte of the second data (indicated by rEJ in the figure) was positioned at the left end, so-called left-justification, but in the second embodiment, the first byte of the mask information 3 is left-aligned only when the first bit is 11'. If the first bit is l01, the data is shifted an extra 1 to 3 bytes to the right and becomes the second data 2'.
For example, as shown in FIG. 8, the mask information 3 is shifted to the right by the number of consecutive tOx from the beginning (however.

'oooo' is the same as '0001' for convenience) is set as the second data 2'. This operation is performed by decoder 5
By partially correcting the number of shifts of the normal aligner 102 from ' to line 50, it can be realized with less hardware addition.

By performing such alignment, the first byte of the second data is used only when the first byte of the first data is valid (the first bit of mask information is "11"), so the first byte of the second data is Byte comparators 10, 20 in FIG.
30 becomes unnecessary, resulting in the configuration shown in FIG. When the second data 2' is aligned as shown in FIG. 8, the decoder 5' in FIG. 7 becomes like 9v1. Output line EJJ' of decoder 5'(ij''=OO',11',21'
, 22'.

31', 32', 33'), the byte comparator ij' is activated and the output line C of the byte comparator x jI is activated.
,,' are sent to the magnitude relationship determination circuit 6', and the final comparison result CC is generated. An example of the configuration of the magnitude relationship determination circuit 6' is shown in FIG.

For example, in the case where the mask information is '0101', the second data 2' is shifted to the right by one byte more than the normal shift according to FIG. 8, and the second data 2' is aligned as rXEFGJ. The decoder 5' is connected to lines E, ,' according to FIG.
=E,,' Wl, line E,,'=E,1'=4:,
,' =E, 1' ==E, ,' ==O are output.

In the byte comparator 11', the first byte r1 of the first data
3J and the first byte rEJ of the second data are compared in magnitude, and in byte comparison $32', the third byte "D" of the first data and the second byte "F" of the second data are compared in magnitude. are carried out, and the results of each comparison are shown on the line C1□e' v
reflected in cat'. Since all other byte comparison amounts are inactivated, the line C0゜'=C,,'=C,,'=
C,,'=C,3'='O'. Accordingly, the magnitude relation determining circuit 6' outputs the line C11' as the line CC when the line C1□'≠0, and outputs the line C2,' as the line CC when the line c, .

Now, the comparison result of the 2-byte data rBDJ and rEFJ is obtained on the line CC.

In this way, when the first bit of mask information 3 is 10', by changing the alignment of continuous arrangement data,
The number of byte comparators can be reduced (10 byte comparators were required in the first embodiment, but 7 byte comparators are required in the second embodiment).
It goes without saying that, as in the first embodiment, there is no need to embed '01 into unnecessary bytes of the second data.

〔Effect of the invention〕

According to the present invention, it is possible to omit the relocation processing step of replacing masked discontinuous arrangement data with continuous arrangement data, so there is an effect that masked comparison processing can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of conventional masked comparison processing, FIG. 2 is a block diagram of an example of the relocation circuit 100 of FIG. 1, and FIG. 3 is a block diagram of a first embodiment of the present invention. 4 is an explanatory diagram of the operation of the byte comparator of FIG. 3, FIG. 5 is an explanatory diagram of the operation of the decoder 5 of FIG. 3, and FIG. 6 is an example of the magnitude relationship determining circuit 6 of FIG. 3. 7 is a block diagram showing a second embodiment of the present invention, and FIG. 8 is a block diagram showing a second embodiment of the present invention.
9 is a diagram illustrating the operation of the decoder 5' in FIG. 7, and FIG. 10 is a circuit diagram of an example of the magnitude relationship determining circuit 6' in FIG. 7. 00.10, 11, 20, 21.22, 30, 31.3
2, 33... Byte comparator, 00', 11'. 11', 22', 31', 32', 33'・
... Byte comparator, 5.5' ... Mask information decoder, 6° 5th z

Claims (1)

[Claims] 1. First data of up to N bytes in non-contiguous arrangement whose arrangement is controlled by N-bit mask information, and second data of up to N bytes in continuous arrangement, the arrangement of which is controlled by N-bit mask information. In the masked comparison processing method that compares the magnitude between
, N-1) and the second data i, i-1, ..., 0
a plurality of comparators that compare all or part of each byte with the byte-th data, and a magnitude comparison between the first data and the second data using the results of the plurality of comparators and the mask information. A comparison processing method with a mask, characterized in that it has a means for performing comparison processing.