JPS58140858A - Transfer system for arithmetic data - Google Patents

Abstract

PURPOSE:To speed up arithmetic processing by adding an information processor which has one-word, n-byte constitution and performs word-by-word data transfer and hardware dedicated to data positioning and code extension. CONSTITUTION:Data read out of a main storage device, word by word, is stored in a data register 1 and the low-order (l) bits of a readout address are stored in a register 2. For arithmetic processing, the data is sent from the register 1 to a function circuit 3. The circuit 3 is given the position of necessary data in one read word by the register 2 and also supplied with the length of data to be processed and an instruction for arithmetic format through a line 15. The circuit 3 when commanded to perform k-byte arithmetic shifts the data in the register 1 to right by n-(m+k) bytes according to the address (m) set in the register 2 to set a sign in the left-hand side (n-k) bytes, and the resulting data is supplied to a logical operation circuit 4 to perform the prescribed arithmetic. Thus, program steps are decreased to realize high-speed processing.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a calculation data transfer method.

[Technical background of the invention and its problems]

In general, when handling m pie) (m) m) data in an information processing device where one word consists of n bytes and data transfer between the main memory and the arithmetic processing unit is performed word by word, the data is transferred from the main memory. After reading , it is necessary to sign-extend and move the byte position & before operation. The time required for this processing can be ignored and is a factor in reducing the calculation speed.

For example, if one word consists of 4 bytes, 1
As shown in the 1g1 diagram, 2-byte data is stored in “09” in the main memory.
"When stored at address 08, main memory readout is 08.
``Starting from the address, 4 bytes of data are read out to the arithmetic processing unit.When performing arithmetic operations, the necessary data in this readout data must be right-justified and the sign must be extended on the left. , as shown in FIG. 2, required processing to convert the data.

[Purpose of the invention]

The present invention has been made based on the above-mentioned drawbacks, and is a method for transferring calculated data that speeds up calculation processing by adding dedicated hardware for data alignment and sign extension. [Summary of the Invention] In an information processing apparatus in which the Fi1 word of the present invention is composed of n bytes and data transfer is performed word by word, normal operation 1
1J 11 circuit includes a register in which the necessary data position of the word data issued from the main memory is set, and a register to align and sign extend the data according to the value set in this register and the type of operation instruction. A circuit is added to perform the calculation, and the output obtained by this circuit is supplied to the logical operation circuit as data that can be processed. This allows the arithmetic processing to be linked.

[@Suzuki's example]

The details of the embodiments of the present invention using pipes are explained below from Figure 3.
Figure 3 shows an embodiment of an arithmetic processing circuit in which the present invention is implemented! In FIG. 0, which is a lock diagram, 1 is a data register in which word-by-word data read out from a main memory (not shown) is stored. The data obtained through this register 1 is supplied via line 12 to an alignment and sign extension circuit (hereinafter simply referred to as function circuit 3). In addition, the lower t bits of the read address of the main memory are sent to the O function circuit 3 on line 13. Register 2.2 in 14
Supplied via. In register 2, the necessary data position of one word read from the primary storage device is set.

The functional circuit 3 aligns the data by shifting by a predetermined byte based on the value set in the register 2, and also performs sign extension based on the type signal of the operation instruction given via the line 15.

Details such as logic will be clarified through the operation. 4 is a logic operation circuit, which connects line 16 from the functional circuit 3.
A logical operation is performed on the data given through the input terminal and the data given to the other input terminal.

@Figure 4 shows the format of data stored in the main memory, Figure 5 shows the data stored in the data register, and Figure 5 shows the data processed by the circuit added according to the present invention and sent to the arithmetic logic circuit. In the diagram showing the contents of each piece of data that can be supplied, arrows indicate word boundaries.

Hereinafter, the operation of the embodiment of the present invention shown in FIG. 3 will be explained in detail with reference to FIGS. 4 to 6.

First, when data is read from the main memory, the data is stored in the data register 1 via line 11. Further, when performing arithmetic processing on the 0th order in which the lower t bits of the read address are stored in the register 2 via the line 13, the data is sent to the functional circuit 3 via the line 12.

In the functional group wIs, the data is aligned and sign extended, and the data for operation thus created is supplied to the logic operation circuit 4 via the line 16.

When processing data in the functional circuit 3, the register 2 indicates the position of necessary data within one word that has been read out from the main memory. The data length and operation format of the data to be operated on are determined by the instruction, and this information is sent to the function group jI! via line 11Yt. Can supply to 3.

In the functional circuit S, processing is performed according to the procedure described below. Assuming that the first block consists of n bytes, the rr required for the operation is k bytes of data in the main memory! i! :F is stored at x+m address (n)m+k) as shown in FIG. When this data is read out, data as shown in FIG. 5 is stored in the data register l. Further, the value "m" is set in the register IK. Here, Q'c=B. Next, when instructed by an instruction to perform a k-byte operation, the functional circuit S shifts the data in register 1, which is supplied via line 11, to the right by n (m+k) bytes; n
A sign is set in -k bytes. In setting the sign, if the instruction is an arithmetic operation, an expanded sign of the data is set in the shaded position in FIG. 5, and if the instruction is a logical operation, "0" is set. The arithmetic data (FIG. 6) produced in this manner is supplied to the logic arithmetic circuit 4 via the line 16t. Desired calculations are performed here.

〔Effect of the invention〕

As described above, according to the present invention, data alignment and sign extension can be performed simultaneously with arithmetic operations, so that the program step necessary for the ninth step can be omitted. Therefore, processing speed can be increased.

[Brief explanation of the drawing]

1 and 4 are diagrams showing the format of data stored in the main memory, and FIGS. 2 and 6 are diagrams showing the format of data to be supplied to the logic operation circuit. , FIG. 3 is a block diagram showing an embodiment of a small arithmetic processing circuit in which the present invention is realized, and FIG. 6 is a diagram showing a formatter of data set in a data register. 1...Data register, 2...Register, 3...
Functional circuit (alignment and sign extension circuit), 4...Logic operation circuit. Takehiko Suzue, agent, patent attorney, figure 1, figure 2, figure 3, figure 114

Claims (1)

[Claims] In an information processing device in which one word consists of n bytes and data transfer is performed word by word, when supplying byte operation data (m:)k) stored in the main memory to the logic operation circuit, from the main memory a first register that is read and held word by word; a second register that sets a necessary data position within one word read from the main memory;
circuit means for performing data alignment by shifting a predetermined number of bytes by 1 based on the value set in the second register, and for performing sign extension according to the type of instruction; A calculation data transfer method characterized in that the output obtained from the calculation data is supplied to the logical calculation circuit as data that can be processed.