JPS60250435A - Information processor - Google Patents

Abstract

PURPOSE:To omit an interface between hardware and instruction software by enabling the instruction firmware to refer to the instruction word editing information while a microprogram corresponding to the instruction read out of a control store is executed. CONSTITUTION:An instruction control arithmetic device 3 processes the instruction word supplied from a main memory 1 via a memory controller 2. Then the device 3 uses an instruction code 301a of an instruction register 301 storing an instruction word as an address and stores the start address information 302a of a control store 305 and the editing type information 302b of the instruction word to a control memory 302 in response to the instruction code. Furthermore/the output of the register 301 and the information 302b are supplied to an editing circuit 303 and edited into a prescribed format to be outputted. The output of an editing register 307 which sets the editing output is stored to a shunt register 308 synchronously with the 1st step of a microprogram of the store 305 and can be referred to through the instruction firmware.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information processing device that performs command control using command words, and more particularly to editing the contents of the command word referred to by the command far 1% 'share.

BACKGROUND ART Conventionally, in this type of information processing device, when instruction firmware refers to an instruction word to judge a condition, it is necessary to read the entire instruction word and then edit it into a predetermined format that allows condition judgment. It was necessary to prepare a microinstruction step. This is because although the number of bits j7y@ is smaller than the number of bits of the entire instruction word, the bit position of the referenced bit differs depending on the instruction format.

On the other hand, in hardware, it is necessary to construct a circuit that judges conditions based on the instruction word editing information recorded in - so that it is not influenced by the instruction format.
However, it is necessary to prepare a data bus for transporting the entire instruction word to a location where it can be referenced and edited by the instruction firmware. Therefore, the above-mentioned conventional device has drawbacks such as a decrease in P1 performance due to an increase in the number of microinstruction steps, and an increase in the number of data buses.

OBJECTS OF THE INVENTION 1-1 of the present invention is to provide an information processing bag that solves the above-mentioned conventional drawbacks, reduces the interface between hardware and instruction firmware, and reduces the number of microinstruction steps of instruction firmware. The purpose is to provide P, +.

Composition of the Invention The information processing device of the present invention includes a control store storing a plurality of microprograms, and startup address information and instruction words of the microprograms specified by an instruction code and stored in the control store corresponding to the instruction code. A control memory that stores editing format information, an editing circuit that outputs instruction word editing information in which the contents of the instruction word are edited into a predetermined format according to the editing format information output from the control memory, and an output of the editing circuit. and an edit register for storing and holding instruction word editing information, so that the instruction file L and ware can refer to the instruction word editing information while the microprogram corresponding to the instruction read from the control store is being executed. It is characterized by the following.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, 5. The instruction control arithmetic unit (IU/EU) 3 includes an instruction register 301 that stores instructions input manually from the main memory 1 via the storage control device 2;
Input the command code 301a output by 01 as an address signal 12. In the instruction code pair IL, start address information 302a of the control store 305 and instruction word editing format information N
(Edit code') 302b inputs the output of the control memory 302 and the instruction register 301, and edit format information 3 is output from the control memory 302 or b111.
an editing circuit 303 that edits and outputs bits necessary for reference by the instruction firmware in a predetermined format according to 02b; and an r train I/register 30 that sets startup address information 302a output from the control memory 302.
4, a control store 305 that stores a plurality of microprograms and in which a microprogram designated by the output of the address register 304 is activated; and a control store 30.
a read register 306 that stores read data of No. 5;
An edit register 307 sets the instruction word edit information output from the edit circuit 303, and a save register 308 stores and holds the output of the edit register 307 in synchronization with the first step of the microprogram that outputs the control store 305.
It is equipped with The contents of the save register 308 can be referenced by the instruction firmware.

FIG. 2 shows the #4 collection format information 302b stored in the control memory 302, which has a 2-bit configuration of bit SO and bit SL, and can indicate four types of editing formats.

FIG. 3 is a diagram showing various instruction types and the editing format of instruction words corresponding to each instruction type. The same figure (A
), the instruction word of instruction type A consists of an 8-bit instruction code and a 20-bit instruction description, and the bit &or ``r required for reference is placed at the position shown in the instruction word. It has been repeated, see 1. Pitu F ao + a
On the right side of Figure 1, if< is used to edit the 8-hit command word editing information in the format of if<. (Δ(B) indicates the relationship between the instruction word of instruction type B and the instruction word editing information format, and (C) of the same figure).

εD) indicate similar formats for instruction types C and D, respectively.

The two bits of the editing format information 302b can be made to correspond to the four instruction types described in JZ as follows.

Instruction type A...S'0=0, S1=
0 instruction type B... SO= O, S1=
1 instruction type C... SO= 1, S1=
0 instruction type D... SO= 1, S1
= 1 Returning to FIG. 1, the editing circuit 303 is the instruction register 3
01 is input, and the reference bits are edited and output in the la format corresponding to each instruction type according to the editing format information 302b supplied from the control memory 302, and set in the editing register 307. Edit register 3
Since 07 is not under the control of the instruction firmware, the above contents are held until the next microprogram starts. The output of the edit register 307 is stored and held in the save register 308 in synchronization with the first step of one microprogram output from the control store 305. ! ! Since the instruction word editing information is stored in the save register 308 in a format corresponding to the instruction type, the instruction firmware can refer to the instruction word editing information at any time during execution of the microprogram.

Next, the operation of this embodiment will be explained. The command word is)
° It is read out from the storage device vl via the storage control device 2 to the instruction control arithmetic unit 3 and stored in the instruction register 301. The instruction code 301a output from the instruction register 301 is output as an address signal of the control memory 302, and the starting address information 3θ2a and editing format information 302b are output from the corresponding address of the control memory 302.
It is supplied to address register 304 and editing circuit 303.

On the other hand, the editing circuit 303 is composed of a selector, inputs the output of the instruction register 301, and additionally outputs the reference history I for referring to the instruction firmware and the editing format information 302b supplied from the control memory 302 as a selection signal. By doing this, the instruction word editing information is edited and output in the specified format.

When a microprogram compatible with the instruction code is started, the start address information 30 output from the control memory 302
2a is set in the address register 304 and output as a startup address signal of the control store 305, the microprogram corresponding to the instruction code stored in the control store 305 is started, and the microinstruction read from the control store 305 is read. It is stored in register 308.

During execution of the microprogram, address register 3
04 is set to an address specified by the instruction firmware.

When a microprogram corresponding to an instruction code is activated, instruction word editing information output from the editing circuit 303 is set in the editing register 307 in synchronization with the activation address information 302a being set in the 7-dress register 304. This instruction word editing information is in a predetermined format corresponding to the instruction type of the instruction. Note that since the 1 edit register 307 is not under the control of the instruction firmware, it holds the contents of 1- until the microprogram starts. The output of the edit register 307 is stored and held in the save register 308 in response to the first step of the microprogram. The output of the save register 308 can be referenced at any time by the instruction firmware.

In this embodiment, since the instruction word can be edited in a predetermined format corresponding to the instruction type and stored in the save register 308, the instruction firmware can refer to the reference hit in the save register 308 at any time during execution of the microprogram. This has the effect of making it possible. The above-mentioned editing does not require preparing a microinstruction step for editing in the microprogram as in the past.
This has the advantage that it can be carried out without reducing performance. Also, from a hardware perspective, as can be understood from FIG. 3, the number of bits referenced by the instruction firmware can be reduced, and the interface between the bird air and the instruction firmware can be reduced.

Effects of the Invention As described in 1-, in the present invention, editing format information is stored in the control memory corresponding to the instruction code, and the editing circuit edits the instruction word into a predetermined format based on the editing format information. Because of this structure, the microinstruction steps conventionally required for reference bit editing are unnecessary, thereby reducing the number of microinstruction steps, and the interface between hardware and instruction firmware can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of editing format information stored in the control memory of the -1-0 embodiment, and FIG. 3 is a diagram showing various command formats and instructions. FIG. 3 is a diagram showing the relationship between word editing formats. In the figure, l: main storage device, 2: storage control device, 3'
: Instruction control arithmetic unit, 301: Instruction register, 301a
: Instruction code, 301b: Instruction descriptor, 302: Control memory, 302a: Start/trace information, 302b/H nest format information, 303: Edit circuit, 304: '/' train driver, 305, Control store, 306: Read 2 Renonuta 307 Edit Rensk, 308: Exit 2 Jf register. Applicant: 11 Electric Co., Ltd. 1 Agent: BU C. 1, Resident 11. l Shunso〉Complete゛ 1 Diagram■

Claims (1)

[Claims] a control store that stores a plurality of microprograms; a control memory that stores startup address information and instruction word editing format information of microprograms that are specified by an instruction code and stored in the control store in correspondence with the instruction code; an editing circuit that outputs instruction word editing information in which the content of the instruction word is edited into a predetermined format according to the editing format information output from the control memory; and an editing circuit that stores and holds the instruction word editing information output from the editing circuit. An information processing device comprising: an edit register for the instruction word editing information, so that instruction firmware can refer to the instruction word editing information while a microprogram corresponding to the instruction read from the control store is being executed.