JPH11184858A - Two division search method/device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize a processing for reading a search object data from a storage device, to improve a processing speed of two division search and to shorten whole processing time required for two division search through the use of a single port memory whose read-out speed is the same as a former one. SOLUTION: Two division search is executed in order from the left of tree of search addresses. The search addresses are arranged so that a search address whose LSB (lowest bit) is zero is an even address and that whose LSB is '1' is an odd address and the two addresses being next search objects can simultaneously be read in the tree. Search object data are separated into data of an even address and those of an odd address in the successive addresses and they are allocated to the two storage devices. Then, reading of the two storage devices is performed simultaneously and the reading/comparison of data can be processed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary search method and apparatus for reading out search target data stored at consecutive addresses one by one in ascending or descending order according to the value thereof and collating it with comparison data of a search key. In particular, while optimizing the process of reading the search target data from the storage device and using a single-port memory with the same reading speed as the conventional one,
The present invention relates to a binary search method and apparatus capable of improving the processing speed of a binary search and reducing the overall processing time required for the binary search.

[0002]

2. Description of the Related Art For example, as shown in FIG. 1, a search address is represented by (N + 1) digits in binary notation, and a total of (2 ^{(N + 1)} -2) pieces of search target data are arranged in ascending order or according to the value. It is assumed that they are stored in descending order. As described above, consider a process in the binary search method in which search target data stored at consecutive search addresses is read out one by one and collated with search key comparison data.

In this case, in the binary search, usually, the first search address is “1000” shown in the figure by reference numeral A1 in the middle of the address space of the continuous addresses.
00 ... 0000 "In addition, according to the comparison result between the data at the search address and the comparison data of the search key, the next search address becomes" 010000 ... 000 ".
0 "or" 110000... 0000 ".

In the binary search, the search address space is divided into two with the middle address of the search address space as a boundary, and the address at the boundary, that is, the data at the search address is compared with the comparison data. Further, one of the two divided address spaces is adopted according to the comparison result, and the adopted address space is set as the next search address space. Thereafter, similarly, the process is repeated with an intermediate address in the current search address space as a boundary. In the binary search, target data is found while sequentially dividing the search address space into two.

[0005] The binary search method is a method often used as a search method for a large amount of data because the search time for n data is proportional to log (n). When a binary search device having a configuration as shown in FIG. 2 is considered, one process includes, as shown in FIG. 3, one process for reading data from the search target data storage device 30, and a process for reading the read data and the comparison data. Is composed of two processes, such as one process for comparison with. As illustrated, in the binary search, the reading process and the comparing process are repeated. Here, the time for reading and comparing is defined as Ct. Then, the total processing time T is as follows.

T = (2 × Ct × log (n)) (1)

In FIG. 2, an address setting device 1
0A and the search target data storage device 30 are connected by the address bus 5. The search data register 22A of the data comparison device 20A and the search target data storage device 30 are connected by the data bus 7. The address setting device 10A sequentially outputs the search addresses during the binary search. The search target data storage device 30 outputs the search target data corresponding to the search address to the search data register 22A of the data comparison device 20A. The data comparison device 20A compares the data in the search data register 22A with
The data is compared with data to be searched which is set in the comparison data register 24A in advance.

[0008]

Here, as shown in FIG. 3, the reading process and the comparison process repeated in the binary search are performed alternately. Therefore, as shown in FIG. 4, when viewed from the search target data storage device 30 side,
Half of the total processing time is free. FIG. 4 shows the reading process and the comparing process separately.

In FIG. 4, first, the data comparison device 20
In A, during the process of comparing the data in the search data register 22A with the data in the comparison data register 24A, the read process is not performed as shown by the broken line in the figure. On the other hand, during the period of the read process from the search target data storage device 30 to the search data register 22A according to the search address from the address setting device 10A, the comparison process is not performed as shown by the broken line in the figure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. The present invention aims at optimizing a process of reading data to be searched from a storage device and using a single-port memory having the same read speed as the conventional one. An object of the present invention is to provide a binary search method and apparatus capable of improving the processing speed of the binary search and reducing the overall processing time required for the binary search.

Here, a single-port memory refers to each memory cell of a built-in memory cell matrix.
It is a common memory with a set of word lines and bit lines. For the single-port memory, on the other hand, the two-port memory or the multi-port memory includes two or more sets of word lines and bit lines for each memory cell. make use of,
This is a special memory that can simultaneously access different built-in memory cells. In the first invention and the second invention, such a two-port memory or a multi-port memory may be used, but the effect can be obtained even with a single-port memory.

[0012]

First, a binary search method according to the first invention of the present application reads out search target data stored at consecutive addresses one by one in ascending or descending order according to the value thereof, and searches for search key comparison data. In the binary search method, the search target data is distinguished between odd-address data and even-address data among consecutive addresses, allocated to two storage devices and stored, and the search target data is stored. When reading one by one, the data of the odd address and the data of the even address are read simultaneously, so that the two storage devices are read simultaneously, and the free time of access to the storage devices is eliminated, thereby solving the above problem. It is a solution.

Next, the binary search device of the second invention of the present application
In a binary search device that reads out the search target data stored at successive addresses one by one according to the value in ascending or descending order and compares the search target data with search key comparison data, When reading one by one, when the address of the reading is expressed in a binary number, L
As the value of SB (least significant bit) is different,
An address setting device for setting two addresses, and distinguishing the search target data by odd-numbered address data and even-numbered address data among the continuous addresses, and storing odd-numbered address data among the search target data. First
A second storage device for storing data of an even address out of the search target data, wherein data of an odd address and data of an even address are simultaneously read, so that reading from the two storage devices is performed. Are at the same time, and the problem is solved.

Hereinafter, the operation of the first and second aspects of the present invention will be briefly described.

For example, if the search address is "3 (00000)
0... 0011) "is given as a search key and is stored in the comparison data register 24A of FIG. 2 when the search data is stored in the comparison data register 24A of FIG. In, the search target data is read out one by one at the following search address,
A comparison for collating with the comparison data of the search key is performed.

First stage: “100000... 0000 (even address)” indicated by reference sign A1 Second stage: “010000... 0000 (even address)” indicated by reference sign A2 Third step: “001000... 0000 (even address) ”Fourth stage:“ 000100... 0000 (even address) ”...

In the conventional binary search, the search address is generally an even address until the last search target data is read. Then, only the last search target data is read at an odd address. For example, all of the first to fourth stages are even addresses.

Referring to FIG. 1, the search addresses A3 and A4 adjacent to the search address of the even address of the code A1 in the first stage are odd addresses. The search addresses A5 and A6 adjacent to the search address of the even address of the code A2 in the second stage are odd addresses.

Thus, an address adjacent to an even address is an odd address, and an address adjacent to an odd address is an even address. That is, by shifting the search address and changing the operation of the search address, the address can be changed to an odd address or an even address. Therefore, by changing the operation of the search address in this way, it is possible to simultaneously read the data of the odd address and the data of the even address when reading the search target data one by one in the binary search.

There are at most two addresses to be searched next time, and these two addresses may be an odd address and an even address.

When the search address is changed as described above, it is necessary to take care not to omit any data to be compared in the binary search. For this reason, in FIG. 8 and FIG. 9 of the embodiment described later, there are addresses that appear redundantly in the search tree, such as underline search addresses.

Further, the search target data is distinguished by odd-numbered address data and even-numbered address data among the continuous addresses, and is allocated and stored in two storage devices. Then, as described above, when the data of the odd address and the data of the even address to be searched next time are simultaneously read, the reading to the two storage devices is performed simultaneously.

When reading from two storage devices is performed simultaneously, comparison processing can be performed continuously (FIG. 6). For this reason, the processing speed of the binary search can be improved, and the overall processing time required for the binary search can be reduced while using the same single-port memory as that for reading the search target data from the storage device.

Note that neither the first invention nor the second invention of the present application specifically limits the above-described search address operation changing method. For example, as in an embodiment described later,
The search address may be logically generated by an operation.
Alternatively, the operation of the search address may be changed using some kind of conversion table. The first and second inventions do not specifically limit the order of search addresses generated by such an operation change as indicated by the search tree.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 5 is a block diagram showing the configuration of a binary search device according to an embodiment to which the binary search method of the first invention and the binary search device of the second invention are applied.

In FIG. 5, an address setting device 10 includes:
The search target data storage device 31 is connected by an address bus 5A. The search data register 22 of the data comparison device 20 and the search target data storage device 31 are connected by the data bus 7A. An address setting device 10,
The search target data storage device 32 is connected by the address bus 5B. The search data register 22 of the data comparison device 20 and the search target data storage device 32 are connected by a data bus 7B. Further, a signal line indicating a comparison result is connected from the data comparison device 20 to the address setting device 10.

The address setting device 10 sequentially outputs search addresses in a binary search. For the two search addresses, the search target data storage device 31 outputs search target data corresponding to the search odd address to the search data register 22 of the data comparison device 20. At the same time, the search target data storage device 32 outputs search target data corresponding to the search even address to the search data register 22 of the data comparison device 20.

Hereafter, the search target data storage device 3
1 is referred to as an odd bank. Further, the search target data storage device 32 is referred to as an even bank.

The data comparison device 20 compares the data read into the search data register 22 with the comparison data register 2
4 is compared with comparison data that is to be searched and is set in advance as search keys. During the comparison, at least a part of the process of reading the next search target data is performed in parallel as shown in FIGS.

When the data to be searched for the m-th time is determined, the candidates for the data to be searched for the (m + 1) -th time are narrowed down to two candidates. As shown in FIGS. 8 and 9, by modifying the address search method of the binary search, one of the two search target data is an odd address and the other is an even address. If the reading of these two search target data is performed simultaneously with the m-th comparison, the (m + 1) -th comparison can be executed subsequent to the m-th comparison.

Here, it is assumed that the reading process is performed continuously in the parallel process and the comparison process is performed continuously as shown in FIG. Further, assuming that the time of the read processing and the time of the comparison processing are almost equal, the total processing time T in this case is as follows. Also, in this case, the binary search can be executed in approximately half the processing time as compared with the related art.

T = (Ct × (log (n) +1)) (2)

Here, in the present embodiment, when the number of data is up to 32, that is, when the address width of the entire search space is (N + 1), an example in which (N + 1) is 5 bits is shown.

FIG. 7 shows a search tree in the order of address search in a conventional general binary search when the search address (N + 1) is 5 bits. In the search tree, addresses to be searched are shown in order from left to right. The vertical direction is the same search order. The number of addresses in the same search order is, of course, two as a binary search.

For example, if the search address is "3 (0001
1) When comparison data that matches the search target data stored at the address of “” is given as a search key and stored in the comparison data register 24, 10000 → 0
The comparison is performed in the order of search addresses 1000 → 00100 → 00010 → 00011.

Since two cycles (reading and comparing) are required for one comparison, a total of ten cycles are required. Here, looking at the search tree in FIG. 7, for example, when the search address 00100 is selected as a comparison target, only two search addresses 00010 and 00110 can be the next comparison targets. That is, if the reading of the data at the two search addresses is performed simultaneously with the comparison of the search target data at the search address 00100,
The overall processing time can be reduced.

When two single port memories are prepared (one bank is set to an odd address and the other bank is set to an even address), the address of the search tree is set so that two data to be read simultaneously cannot be in the same bank. The configuration needs to be modified. For example, it is effective to form a search tree such that the LSBs of two addresses read simultaneously become 0 and 1. With this configuration, L
The bank is distinguished by the SB, and the bank having the search target data to be read can be changed only by the operation change of shifting the search address by one.

Hereinafter, a method of constructing a search tree of a binary search to which the present invention is applied, in a case where the search address (hereinafter referred to as a head address) of search target data to be read and compared first is an even number. (Hereinafter referred to as a first embodiment) and an example of an odd number (hereinafter referred to as a second embodiment) will be described in this order.

In the first and second embodiments, the search address is (N + 1) digits in binary notation, and
That is, consider the case of processing a total of (2 ^{(N + 1)} -2) search target data with (N + 1) bits.

First, the first embodiment, that is, the case where the start address is an even number will be described.

The case where the start address is an even number means that the start address is "100000... 0000".

Then, the search address for the second read of the search target data is “10000” for the even-numbered bank.
0... 0000 ”and“ 1100
00... 0001 ”.

Hereafter, in addition to "0" and "1", each bit of the (N + 1) digit search address is added to "x",
Represented by "R", "A", "B", and "C".
Also, “x”, “R”, “A”, “B”, and “C”
, Each character represents one bit whose value is “0” or “1”.

Then, in each of the third to (N + 1) times (each time is m-th), the search address for reading the search target data for the even-numbered bank is as follows.

“Xxx... XxxRA1000... 0000” (3)

The data for the odd-numbered bank is as follows.

“Xxx... XxxRB1000... 0001” (4)

Here, in the bit strings of the above (3) and (4), the "R ..."
A ”or“ RB ”on the left side, that is, MSB (most sig
The length of the bit string on the (nificant bit) side is (m−3) bits. The bit string has the same value as the (m-3) bits from the MSB of the previous (m-1) th search address.

The value of “R” at the (m−2) th bit from the MSB depends on the (m−2) th, that is, the result of the previous comparison. If the comparison result is {(comparison data) <(search target data)}, then (R = 0). {(comparison data)
If> (search target data)}, then (R = 1).

The value of "A" at the (m-1) th bit from the MSB depends on the (m-1) th, that is, the result of the previous comparison. When the even bank is selected based on the comparison result, (A = 0) and (B = 1). When an odd-numbered bank is selected based on the comparison result, (A = 1), (B =
0).

The value of the m-th bit from the MSB of the search address is "1". N from the (m + 1) th bit from the MSB
All bits of the bit string having a total (N−m) bit length up to the bit number are “0”. LSB is "0" for even banks and "1" for odd banks.

The search address for the final (N + 2) -th read operation for the even-numbered bank is as follows.

“CCCCC... CCCCC0” (5)

The data for the odd-numbered bank is as follows.

“00000... 000001” (6)

Here, in the bit string of the above (5),
The bit string of bit length N from the MSB, indicated by “CCCCC... CCCCC”, is converted into the value of the bit string of bit length N from the MSB of the previous (N + 1) th search address.
This is a bit string of a value obtained by adding “1”. In the bit string of the above (6), all the bits of the bit string indicated by “00000... 000000” from the MSB to the bit length N are “0”. The last (N + 2) -th read is the previous (N + 1) -th read, and if all the bits of the search address are “0”, the bank becomes an odd-numbered bank. Others are even banks.

For example, when the start address is an even number, the search address is represented by five digits in binary notation, that is, (N =
In the case of 4), the processing for a total of 32 search target data is as shown in FIG. In FIG. 8, a search address with an underline is an address that appears repeatedly. Further, the search addresses marked with “*” in the figure are for the case where an odd-numbered bank is selected in the final comparison.

Next, a second embodiment, that is, a case where the start address is an odd number will be described.

The case where the start address is an odd number, that is, the start address is "011111... 1111".

Then, the search address for the second read of the search target data is “00111” for the even-numbered bank.
1... 1110 ”and“ 1011 ”for odd-numbered banks.
11 ... 1111 ".

Then, in each of the third to (N + 1) times (each time is m-th), the search address for reading the search target data for the even-numbered bank is as follows.

“Xxx... XxxRA0111... 1110” (7)

The data for the odd-numbered bank is as follows.

“Xxx... XxxRB0111... 1111” (8)

Here, in the bit strings of the above (7) and (8), "R ..."
The length of the bit string on the left side of “A” or “RB”, that is, the bit string on the MSB side is (m−3) bits.
It has the same value as SB to (m−3) bits.

The value of “R” at the (m−2) th bit from the MSB depends on the (m−2) th, that is, the result of the preceding comparison. If the comparison result is {(comparison data) <(search target data)}, then (R = 0). {(comparison data)
If> (search target data)}, then (R = 1).

The value of “A” at the (m−1) th bit from the MSB depends on the (m−1) -th, that is, the result of the previous comparison. When the even-numbered bank is selected based on the comparison result, (A = 1) and (B = 0). When an even-numbered bank is selected based on the comparison result, (A = 0), (B =
1).

The value of the m-th bit from the MSB of the search address is "0". N from the (m + 1) th bit from the MSB
Up to the bit, all bits of the bit string having a total (N−m) bit length are “1”. LSB is "0" for even banks and "1" for odd banks.

The search address for the final (N + 2) -th read operation for the even-numbered bank is as follows.

“11111... 111110” (9)

The data for the odd-numbered bank is as follows.

“CCCCC... CCCCC1” (10)

Here, in the bit string of the above (9),
The bits of the bit string indicated by "11111 ... 11111" from the MSB to the bit length N are all "1". In the bit string of the above (10), "CCCCC ...
.., "CCCCC", the bit string from the MSB to the bit length N is obtained from the value of the bit string from the MSB to the bit length N of the previous (N + 1) -th search address.
This is a bit string of a value obtained by subtracting “1”. The last (N + 2) -th read is the previous (N + 1) -th read, and if all bits of the search address are “1”, the bank becomes an even-numbered bank. Others are odd banks.

For example, when the start address is an odd number, the search address is represented by five digits in binary notation, that is, (N =
In the case of 4), the processing for a total of 32 pieces of search target data is as shown in FIG. In FIG. 9, a search address with an underline is an address that appears repeatedly. In this case, only the search addresses marked with “*” in the figure select the even-numbered bank in the final comparison.

As described above, in the first embodiment and the second invention, when the first and second search addresses are given as the initial values, the subsequent search addresses can be logically obtained by calculation. Note that the last search address needs to be adjusted differently from the method of obtaining the search address before that. When changing the operation of the search address, it is necessary to take care not to omit the search target data to be compared in the binary search.

As described above, according to the present embodiment,
The first invention and the second invention of the present application can be effectively applied. Therefore, the process of reading the search target data from the storage device is optimized, and the read speed is increased using the same single-port memory as before, but the processing speed of the binary search is improved and the overall processing time required for the binary search is reduced. can do.

In the binary search method according to this embodiment, the number of search tree stages is increased by one, and the number of times of reading and comparing the search target data is increased by one, as compared with the ordinary binary search method. This is because, when reading out the search target data sequentially, the data of the odd address and the data of the even address are read simultaneously, so that the search tree is modified to apply the present invention. Is increased by one. As described above, although the number of times of reading and comparing the search target data increases, at least a part of the reading and the comparison is performed in parallel,
As a whole, the processing time of the binary search is reduced.

For example, as shown in FIG. 6, it is assumed that read processing is continuously performed in parallel processing and comparison processing is continuously performed. Further, assuming that the time of the reading process and the time of the comparing process are substantially equal to each other, the time required for the increasing one reading or comparing process takes a total of (log (n) +2) cycles. Therefore, the total processing time is as follows.

T = (Ct × (log (n) +2)) (11)

[0081]

According to the present invention, the processing for reading the search target data from the storage device is optimized, and the processing speed of the binary search is improved while using the same single-port memory as the conventional one, and the binary search is performed. The entire processing time required for the search can be reduced.

For example, conventional (2 × Ct × log (n))
When the present invention is applied, the required processing time is reduced by (Ct ×
(Log (n) +2)), and an extremely excellent effect that the processing time can be reduced by almost half compared to the related art can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram relating to a search address showing a process of a binary search.

FIG. 2 is a block diagram showing a configuration of a conventional binary search device.

FIG. 3 is a diagram showing readout and comparison of search target data in the binary search device.

FIG. 4 is a diagram showing the discontinuity of the reading and comparison / comparison.

FIG. 5 is a block diagram showing a configuration of an embodiment of a binary search device to which the first invention and the second invention of the present application are applied;

FIG. 6 is a diagram showing reading of search target data and comparison and comparison in the binary search device of the embodiment.

FIG. 7 is a diagram showing a conventional search tree.

FIG. 8 is a diagram showing a search tree when the start address is an even number in the embodiment.

FIG. 9 is a diagram showing a search tree when the start address is odd in the embodiment.

[Explanation of symbols]

 10, 10A ... address setting device 20, 20A ... data comparing device 22, 22A ... search data register 24, 24A ... comparison data register 30, 31, 32 ... search target data storage device

Claims (2)

[Claims] 1. A binary search method in which search target data stored at consecutive addresses is read one by one in ascending order or descending order according to the value thereof, and is compared with comparison data of a search key. The data of the odd address and the data of the even address are distinguished from each other, are allocated and stored in two storage devices, and when the search target data is read one by one, the data of the odd address and the data of the even address are simultaneously read. The binary search method as described above, wherein reading from the two storage devices is performed at the same time, and reading and comparison are performed in parallel to reduce a search time. 2. A binary search device that reads out search target data stored at consecutive addresses one by one in ascending order or descending order according to the value and compares the data with search key comparison data. When reading out the search target data one by one, when the read address is expressed in a binary number, LSB (least significant bit)
An address setting device that sets two addresses, the values of which are different from each other, and the search target data is distinguished by odd-numbered address data and even-numbered address data in the continuous addresses,
A first storage device that stores data of an odd address in the search target data; and a second storage device that stores data of an even address in the search target data. The data of the odd address and the even address Wherein the data is read out at the same time so that the two storage devices are read out simultaneously, thereby shortening the search time.