JP4785492B2 - Memory system and search method - Google Patents

Description

  The present invention searches for data having a specific value (search key data) in a data string (data to be searched) stored in a plurality of memories arranged in ascending or descending order. The present invention relates to a memory system and a data search method.

  Conventionally, according to the value, a plurality of data are arranged in ascending or descending order in one memory and stored, and the stored data string includes data of a value that matches the data of a specific value. The bisection method is known as a method for searching whether or not the image is detected. Hereinafter, as an example, as shown in FIG. 7, 15 data from N0 to N14 are stored in ascending order (N0 ≦ N1 ≦... ≦ N14) in memory addresses 1000 to 1014 according to the values. The bisection method will be described by taking a case as an example.

  In the bisection method, when searching whether or not the data V is included in the 15 data strings, first, the data N7 at the address 1007 at the center of the data string is read, and V and N7 are compared. As a result, if V = N7, the search ends at that time. If V <N7, the data V is not included in the data N8 to N14, so the data N0 to N6 at the addresses 1000 to 1006 are searched next. Data N8 to N14 of 1008 to 1014 are searched.

  For example, when data N0 to N6 at addresses 1000 to 1006 are searched next, N3 and V at the center address 1003 are similarly compared. As in this bisection method, in order to search predetermined data from 2 N -1 data strings by a search method with the search range narrowed down to about ½ each time, read comparison from the memory is required. A maximum of N-1 times is required. For this reason, as the number of data included in the data string is increased, the number of times of reading data from the memory is increased, and the processing time is increased.

  Here, as a prior art document related to the present invention, there is a binary search method and apparatus disclosed in Patent Document 1.

  Patent Document 1 reads out the search target data stored in consecutive addresses one by one in ascending or descending order according to the value and collates with the comparison data of the search key. Distinguish between address data and even address data, allocate to two storage devices, store them, and when reading the search target data one by one, read the odd address data and even address data simultaneously, Reading to the two storage devices is performed simultaneously, and reading and comparison are processed in parallel.

Japanese Patent Laid-Open No. 11-184858

  An object of the present invention is to solve the problems based on the prior art, and according to the value, whether data of a specific value is included in the data string stored in ascending or descending order in the memory. It is an object of the present invention to provide a memory system and a search method capable of searching whether or not at high speed.

In order to achieve the above object, the present invention provides a memory system composed of N memories (N is a power of 2 of 4 or more) obtained by dividing the address space by the value of the lower bits of the address, in ascending or descending order. A method for searching for data having a specific value from the arranged data columns,
Read data of N addresses separated from each other by (N + 1) ^M (M is an integer of 2 or more) from the N memories, and compare the value of the read data with the specific value ;
If none of the read data has a value that matches the specific value, then:
From the magnitude relationship between the value of the read data and the specific value, an address range in which data having a value matching the specific value exists is specified, and within the specified address range, (N + 1) ^{M− The} present invention provides a search method characterized by simultaneously reading data at N addresses apart by one and comparing the value of the read data with the specific value .

Further, the present invention is composed of N memories (N is a power of 2 of 4 or more) with identification codes from 0 to N-1 divided into the address space according to the value of the lower bits of the address, A memory system for retrieving data of a specific value from a data sequence arranged in ascending or descending order in the N memories,
Each of the N memories is provided in correspondence with each other and receives a common global address and a numerical value K indicating an integer search order from the Mth order (M is an integer of 2 or more) to the 0th order, and (N + 1) each other ^There is provided a memory system having an address generator for generating local addresses corresponding to N addresses separated by ^K.

Here, the address generator, to the global address ^{(N + 1) K × L} -1 (L is an integer from 1 to N) preferably generates a local address corresponding to the address obtained by adding, respectively.

Further, when the remainder obtained by dividing the global address by N is R, a memory with an identification code of R + L-1 (if R + L-1 is N or more, R + L-1-N) is attached. It is preferable that the address generator provided corresponding to generate a local address corresponding to an address obtained by adding (N + 1) ^K × L−1 to the global address.

  According to the present invention, since data is read and compared simultaneously from four or more power-of-two memories, a search can be performed faster than the conventional bisection method. In addition, as the number of memory divisions is increased, the number of search orders can be reduced and the number of comparisons of reading from the memory can be reduced, so that the next search area is narrowed down to a narrower range than before by one read comparison. It is possible to search a data string including a large number of data at higher speed.

  Hereinafter, a memory system and a search method of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a schematic diagram of an embodiment showing the configuration of a memory system of the present invention. The memory system 10 shown in FIG. 1 arranges the values in ascending or descending order in four memories with identification codes 0 to 3 divided into four address spaces by the value of the lower 2 bits of the address. The data of a specific value is retrieved from the obtained data string. The memory system 10 includes a memory controller 12 and four comparison circuits 14a, 14b, 14c, and 14d.

  The memory controller 12 performs control when data is written to and read from the four memories, and operation when searching for data of a specific value from the data string. A global address is output from the memory controller 12 via the global address bus 26, and various control signals are output via the signal line 30. The memory controller 12 and the four comparison circuits 14a, 14b, 14c, and 14d are connected to each other via a global data bus 28.

  Subsequently, the comparison circuits 14a, 14b, 14c, and 14d are the values of the data (comparison data) arranged for each predetermined number of data among the data strings stored in the respective addresses of the four memories. And the value of specific data (search key data) designated by the memory controller 12, and the comparison result is output. All the comparison results output from the comparison circuits 14a, 14b, 14c, and 14d are input to the memory controller 12 through the signal line 36.

  Hereinafter, the comparison circuit 14a will be described as a representative example.

  The comparison circuit 14a includes an address generator 16a (address generator 0), a memory 18a (memory 0), a gate circuit 20a (G0), a register 22a (R0), and a comparator 24a (comparator 0). It is configured. Here, for example, the numbers 0, 1, 2, and 3 in the address generators 0, 1, 2, and 3 represent the identification codes (ID) of the address generators 16a, 16b, 16c, and 16d, respectively. For example, the identification code of the address generator 0 is 0. The same applies to the other components.

  The address generator 16 a receives a global address from the memory controller 12 via the global address bus 26 and various control signals via the signal line 30. The address generator 16a outputs a local address via the local address bus 32a. The address generator 16a receives a global address and a control signal from the memory controller 12, and outputs a local address to the memory 18a.

  A local address is input to the memory 18a from the address generator 16a via the local address bus 32a. The memory 18a is connected to the gate circuit 20a and the comparator 24a via the local data bus 34a.

  The memories 18a, 18b, 18c, and 18d are the four memories described above. The local addresses input to the four memories 18a, 18b, 18c, and 18d correspond to addresses in which the address space is divided into four by the value of the lower two bits (four values) of the global address. In this embodiment, the memory 18a is selected when the value of the lower 2 bits of the global address is 00, and the memories 18b, 18c, and 18d are selected when the values are 01, 10, and 11, respectively.

  In other words, the memory 18a, 18b, 18c, 18d is allocated with memory spaces corresponding to addresses whose addresses are 0, 1, 2, 3 by dividing the global address by 4 of the number of memories. For example, local addresses 0, 1, 2,... Of the memory 18a correspond to global addresses 0, 4, 8,. Further, local addresses 0, 1, 2,... Of the memories 18b, 18c, 18d are global addresses 1, 5, 9,..., Global addresses 2, 6, 10,. Corresponding to

  Subsequently, the gate circuit 20 a is connected to the memory controller 12 via the global data bus 28. The gate circuit 20a is connected to the memory 18a and the comparator 24a via the local data bus 34a as described above. The gate circuit 20a is a bidirectional buffer circuit, for example, and controls connection and disconnection between the global data bus 28 and the local data bus 34a when writing and reading data between the memory controller 12 and the memory 18a. To do.

  For example, when the memory 18a is selected by the global address, the gate circuit 20a becomes active. When data is written to the memory 18a, control is performed so that data is input from the global data bus 28 toward the local data bus 34a. On the other hand, when data is read from the memory 18a, control is performed so that data is output from the local data bus 34a toward the global data bus 28.

  Subsequently, the register 22 a is connected to the memory controller 12 via the global data bus 28. Further, the specific value data (search key data) described above is output from the register 22a. The register 22a receives data of a specific value to be searched from the data string stored in the memory 18a from the memory controller 12 and holds it.

  A predetermined value data (comparison data) is input from the memory 18a to one input of the comparator 24a, and a specific value data (search key data) is input from the register 22a to the other input. . The comparator 24a compares the value of the comparison data input from the memory 14a with the value of the search key data input from the register 22a, and outputs the comparison result. The comparison result output from the comparator 24 a is input to the memory controller 12 via the signal line 36.

  The configuration of the comparison circuits 14b, 14c, and 14d is the same as that of the comparison circuit 14a. For this reason, in FIG. 1, the codes of the corresponding address generators, memories, gate circuits, registers, and comparators of the comparison circuits 14b, 14c, and 14d are changed to “b”, “c”, and “d”, respectively. The reference numerals are changed to 1, 2, and 3, respectively, and description thereof is omitted. For example, the address generator is an address generator 16b, 16c, 16d (address generator 1, 2, 3).

  Next, the operation of the memory system 10 will be described.

  First, normal memory access, that is, data write and read operations to the memories 18a, 18b, 18c, and 18d will be described.

  In this case, a global address for writing or reading data is output from the memory controller 12. Each address generator 16a, 16b, 16c, 16d outputs a quotient obtained by dividing the global address by 4 as a local address. Since the address is generally expressed in binary, in this case, all the bits on the upper side excluding 2 bits from the least significant bit side of the global address are output as the local address.

  At the same time, from the address generators 16a, 16b, 16c, and 16d, an active state write or write to only one corresponding memory among the memories 18a, 18b, 18c, and 18d by the remainder obtained by dividing the global address by 4 or A read control signal (not shown in FIG. 1) is input. In the case of this embodiment, when the remainder is 0, 1, 2, 3, the active state write or read control signals are input only to the memories 18a, 18b, 18c, 18d, respectively.

  Then, the gate circuit corresponding to the memory to which the control signal for writing or reading in the active state is input is set in the active state, and the local data buses 34a and 34b corresponding to the gate circuit are set in the active state through the gate circuit. , 34c, 34d and the global data bus 28 are connected. As a result, data is written or read between the memory controller 12 and the memory storing the data corresponding to the global address.

  Next, the search operation, that is, the comparison operation between the value of the comparison data and the value of the search key data will be described.

  First, the zero-order search will be described with reference to FIG. The zero-order search is a search in the case where the data included in the data string is only comparison data, and the number of data is four (4 words), which is the same as the number of memory divisions.

  FIG. 2A shows an example in which the starting address of the search area is 1000, which is a multiple of 4. In the figure, 1000, 1004, 1008,... On the left side represent global addresses, and 250, 251, 252,. Further, +0, +1, +2, +3 on the upper side in the figure represent offset values for the global address on the left side in the figure. The vertical columns +0, +1, +2, and +3 represent data stored in the memories 18a, 18b, 18c, and 18d, respectively. The same applies to the following description.

  In the case of the data string shown in FIG. 2A, in the zero-order search, the memory controller 12 outputs a global address 1000 indicating the start address of the search area and a control signal indicating the zero-order search.

  In each address generator 16a, 16b, 16c, 16d, the head address 1000 is divided by 4 which is the same as the number of memories, and the quotient 250 and the remainder 0 are calculated. In the zero-order search, as shown in the table of FIG. 5, when the remainder is 0, all of the address generators 16a, 16b, 16c, and 16d having the identification codes 0, 1, 2, and 3 are related to the quotient 250. The numerical value 0 is added and a local address 250 is generated.

  Here, the table of FIG. 5 shows the remainder obtained by dividing the start address of the search area by 4 that is the number of memory divisions, and the address generators 16a, 16b, 16c, and 16d of the identification codes 0, 1, 2, and 3, respectively. Represents the relationship with the coefficient value added to the value of the quotient. That is, the address generators 16a, 16b, 16c, and 16d of the identification codes 0, 1, 2, and 3 are shown in the table of FIG. 5 as a quotient obtained by dividing the head address represented by the global address by the number of memories. The coefficient value is added to generate a local address.

  Also, control signals for reading comparison data are input from the address generators 16a, 16b, 16c, and 16d to the corresponding memories 18a, 18b, 18c, and 18d, respectively.

  Search key data is output from the memory controller 12. This search key data is held in all the registers 22a, 22b, 22c, and 22d. The comparison data C0 to C3 read from each of the memories 18a, 18b, 18c, and 18d and the search key data held in each of the registers 22a, 22b, 22c, and 22d are respectively compared with the corresponding comparison circuits 24a, 24a, 24b, 24c, and 24d are input, and the magnitude comparison between the two is performed.

  The comparison results by the comparators 24a, 24b, 24c, and 24d are input to the memory controller 12 via the signal line 36. The memory controller 12 determines which of the comparison data C0, C1, C2, and C3 stored in the memories 18a, 18b, 18c, and 18d is a search key based on the comparison results by the comparators 24a, 24b, 24c, and 24d. It is determined whether the data matches or does not match, and the search operation is terminated.

  Next, FIG. 2B is an example in the case where the start address of the search area is 1001 which is not a multiple of 4.

  The difference between FIG. 2 (a) and FIG. 2 (b) is that, in the zero-order search of FIG. 2 (b), the global address 1001 representing the start address of the search area is output from the memory controller 12 and the address The generator 16a outputs 251 instead of 250 as the local address.

  The address generator 16a similarly divides the start address 1001 of the search area by 4, and calculates that the quotient is 250 and the remainder is 1. As shown in the table of FIG. 5, when the remainder is 1, the address generator 16 a having an identification code (ID) of 0 adds a coefficient value of 1 to the quotient 250, so that the local address 251 is changed. Generated. The operations in the address generators 16b, 16c, and 16d and the subsequent search operation are the same as those in FIG.

  In the above two embodiments, the start address of the search area is a multiple of 4 that is the number of memory divisions and a multiple of 4 + 1, but as shown in the table of FIG. 5, a multiple of 4 + 2 In this case, the remainder is 2, and 0 and 1 whose identification code (ID) is smaller than the remainder 2, that is, 1 is added to the quotient 250 in the address generators 16a and 16b. In the case of a multiple of 4 + 3, the remainder is 3, and the identification code (ID) is 0, 1, 2, that is, 1 is added to the quotient 250 in the address generators 16a, 16b, 16c.

  Next, the primary search will be described with reference to FIG. In the primary search, as the data included in the data string, four (4 words) data, which is the same as the number of data included in the data string of the zero-order search (that is, the number of memory divisions), is stored in one unit (block). This is a search in the case where five blocks B0 to B4 that are (size) are included, and one comparison data C0 to C3 is inserted between each of the blocks B0 to B5.

  FIG. 3A shows an example in which the start address of the search area is 1000, which is also a multiple of 4.

  Similarly, in the case of the primary search shown in FIG. 3A, the memory controller 12 outputs a global address 1000 indicating the start address of the search area and a control signal indicating the primary search.

  In each address generator 16a, 16b, 16c, 16d, the head address 1000 is divided by 4, and the quotient 250 and the remainder 0 are calculated. In the primary search, as shown in the table of FIG. 5, when the remainder is 0, the address generators 16a, 16b, 16c, and 16d having the identification codes 0, 1, 2, and 3 are related to the quotient 250. The number 0 is added. Further, local addresses 251, 252, 253, and 254 are generated by adding values obtained by multiplying the coefficient values shown in the table of FIG. 6 by the block size (4 in this example) ÷ 4 = 1, respectively.

  Here, the table of FIG. 6 shows the remainder obtained by dividing the head address by 4 which is the number of memory divisions, and the local addresses at the address generators 16a, 16b, 16c, and 16d of the identification codes 0, 1, 2, and 3, respectively. In generation, it represents the relationship with the coefficient value multiplied by block size ÷ 4. That is, the address generators 16a, 16b, 16c, and 17d of the identification codes 0, 1, 2, and 3 are shown in the table of FIG. 5 as a quotient obtained by dividing the head address represented by the global address by the number of memories. The coefficient value is added, and further, a value obtained by multiplying the coefficient value shown in the table of FIG. 6 by the block size ÷ 4 is added to generate a local address.

  The subsequent operation is the same as in the case of FIG. All the comparison results are input to the memory controller 12, and as a result, if the value of the search key data matches any of the comparison data C0 to C3, the search operation ends.

  On the other hand, if none of them matches, the block to be searched next is determined from the blocks B0 to B4 according to the magnitude relationship between the value of the search key data and the comparison data C0 to C3. The above-described zero-order search is performed on the block. For example, when the value of the search key data is larger than the comparison data C0 and smaller than the comparison data C1, the block B1 becomes the next search target, and the four comparison data C0 to C3 included in the block B1 A zero-order search is performed.

  Next, FIG. 3B is an example in the case where the start address of the search area is 1001 which is not a multiple of 4.

  The difference between FIG. 3A and FIG. 3B is that, in the primary search of FIG. 3B, the memory controller 12 outputs a global address 1001 representing the start address of the search area, and the address The generators 16a, 16b, 16c, and 16d output 255, 251, 252, and 253 calculated as in the case of FIG. 3A, instead of 251, 252, 253, and 254 as local addresses, respectively. Is a point.

  The subsequent search operation is exactly the same as in the case of FIG. The same applies when the remainder is 2 or 3.

  Next, the secondary search will be described with reference to FIG. In the secondary search, as data included in the data string, 24 pieces of data (24 words) which are the same as the number of data included in the data string of the primary search (that is, 4 × 5 + 4) are stored in one unit (block size). ), And the comparison data C0 to C3 is inserted between the blocks B0 to B5.

  FIG. 4A shows an example in which the start address of the search area is 1000, which is also a multiple of 4.

  Similarly, in the case of the secondary search shown in FIG. 4A, the memory controller 12 outputs a global address 1000 indicating the start address of the search area and a control signal indicating the secondary search.

  In each address generator 16a, 16b, 16c, 16d, the head address 1000 is divided by 4, and the quotient 250 and the remainder 0 are calculated. In the secondary search, as shown in the table of FIG. 5, when the remainder is 0, the address generators 16a, 16b, 16c, and 16d having the identification codes 0, 1, 2, and 3 are related to the quotient 250. The number 0 is added. Further, local addresses 256, 262, 268, and 274 are generated by adding the values obtained by multiplying the coefficient values shown in the table of FIG. 6 by the block size (24 in this example) ÷ 4 = 6, respectively. .

  The subsequent operation is the same as in the case of the primary search. That is, if the value of the search key data matches any one of the comparison data C0 to C3, the search operation ends. On the other hand, if none of them matches, the next block to be searched is determined from among the blocks B0 to B4 according to the magnitude relationship between the value of the search key data and the comparison data C0 to C3. The above-described primary search is performed on the block.

  Next, FIG. 4B is an example in the case where the start address of the search area is 1001 which is not a multiple of 4.

  The difference between FIG. 4A and FIG. 4B is that, in the secondary search of FIG. 4B, the global address 1001 representing the start address of the search area is output from the memory controller 12, and the address The generators 16a, 16b, 16c, and 16d output 275, 256, 262, and 268 calculated in the same manner as in FIG. 4A, instead of 256, 262, 268, and 274 as local addresses, respectively. Is a point.

  The subsequent search operation is exactly the same as in the case of FIG. The same applies when the remainder is 2 or 3.

  The search is performed from the search of the highest order according to the number of data included in the data string to be searched. For example, if the data string is 3124 (3124 words), the fourth search is started. If a match is detected according to the comparison result of the quaternary search, the search operation ends at that point. If no match is detected, one block is determined according to the comparison result, and then the tertiary search is performed. Is called. Similarly, if no match is detected, the lower order is sequentially searched. In the longest case, the search is performed up to the zeroth search, and the search operation ends.

  Note that the number of data included in the data string to be searched can be arbitrarily set. In that case, an address where the last data of the data string is stored is set in the memory controller 12, and if the read data exceeds the last address in the read comparison, the comparison result is adopted. What is necessary is just to comprise so that it may not.

  For example, if C3 exceeds the last address among the comparison data C0 to C3, only the comparison result of C0 to C2 is adopted. At the time of primary or higher search, a block to be searched next may be selected from blocks B0 to B3 excluding B4. In this case, if C2 is equal to the last address and the value of the search key data is larger than C2, no matching data is set (when data is arranged in ascending order).

  In addition, the number of memory divisions is not limited to 4, and the search performance can be easily improved by dividing the memory into larger numbers such as 4 or more powers of 2 such as 8, 16, 32,. Can be made. That is, as the number of memory divisions is increased, the number of search orders can be reduced and the number of read comparisons from the memory can be reduced, so that the next search area can be narrowed down to a narrower range by one read comparison. Thus, it becomes possible to search a data string including a large number of data at higher speed.

  For example, when the number of memory divisions is increased to 16, the searchable data size from the 0th order to the 3rd order is 16,288, 4912, 83520 in order, and is composed of 83520 data in four or less read comparisons. It is possible to search from the data string. On the other hand, in the conventional bisection method, the memory system of the present invention can significantly increase the speed as compared with the case where a data string composed of 65535 data can be searched by a maximum of 17 read comparisons. It is clear that it is intended.

Here, N (N is a power of 2 of 4 or more) is the number of memory divisions, and M (M is an integer of 1 or more) is the order of search. In this case, according to the present invention, comparison data stored at N addresses separated from each other by (N + 1) ^M are simultaneously read from N memories, and the values of the read N comparison data are searched. Compared with key data at the same time. When L (L is an integer from 1 to N) is a coefficient and the remainder obtained by dividing the global address (start address) by N is R (R is an integer from 0 to N−1), each address generator Generates a local address corresponding to an address obtained by adding (N + 1) ^M × L−1 to the global address. In the M-th search, it is possible to search a data string composed of at most (N + 1) ^{M + 1} −1 data.

Each identification code of the N memories is represented by an integer from 0 to N-1. Here, the identification code of each memory is expressed as R + L-1 when R + L-1 is smaller than N, and R + L-1-N when N +. Then, the address generator provided corresponding to the memory with the identification code expressed as R + L-1 or R + L-1-N is an address obtained by adding (N + 1) ^M × L-1 to the global address. A local address corresponding to is generated.

The present invention is basically as described above.
The memory system and search method of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the spirit of the present invention. Of course.

It is the schematic of one Embodiment showing the structure of the memory system of this invention. (A) And (b) is the schematic showing the arrangement | sequence of the data sequence at the time of the 0th search in this invention. (A) And (b) is the schematic showing the arrangement | sequence of the data sequence at the time of the primary search in this invention. (A) And (b) is the schematic showing the arrangement | sequence of the data sequence at the time of the secondary search in this invention. It is a table | surface for calculating the local address output from each memory in each next search of this invention. 6 is a table for calculating a local address output from each memory in a primary or higher-order search according to the present invention. It is a conceptual diagram for demonstrating the conventional bisection method.

Explanation of symbols

10 memory system 12 memory controller 14a, 14b, 14c, 14d comparison circuit 16a, 16b, 16c, 16d address generator 18a, 18b, 18c, 18d memory 20a, 20b, 20c, 20d gate circuit 22a, 22b, 22c, 22d register 24a, 24b, 24c, 24d Comparator 26 Global address bus 28 Global data bus 30, 36 Signal line

Claims (4)

Data of a specific value from a data string arranged in ascending or descending order in a memory system composed of N memories (N is a power of 2 greater than or equal to 4) that divides the address space according to the value of the lower bits of the address A search method,
Read data of N addresses separated from each other by (N + 1) ^M (M is an integer of 2 or more) from the N memories, and compare the value of the read data with the specific value ;
If none of the read data has a value that matches the specific value, then:
From the magnitude relationship between the value of the read data and the specific value, an address range in which data having a value matching the specific value exists is specified, and within the specified address range, (N + 1) ^M− read ¹ away N addresses of data at the same time, search method the value of the read-out data and comparing with the specific value. It is composed of N memories (N is a power of 2 of 4 or more) with identification codes from 0 to N-1 obtained by dividing the address space by the value of the lower bits of the address. A memory system for retrieving data of a specific value from a data sequence arranged in ascending or descending order,
Each of the N memories is provided in correspondence with each other and receives a common global address and a numerical value K indicating an integer search order from the Mth order (M is an integer of 2 or more) to the 0th order, and (N + 1) each other A memory system comprising an address generator for generating local addresses corresponding to N addresses separated by ^K. Said address generator, to the global address ^{(N + 1) K × L} -1 (L is an integer from 1 to N) according to claim 2, characterized in that respectively generate local address corresponding to the address obtained by adding Memory system. When the remainder obtained by dividing the global address by N is R, it corresponds to a memory with an identification code of R + L-1 (if R + L-1 is N or more, R + L-1-N) 4. The memory system according to claim 3 , wherein the address generator is configured to generate a local address corresponding to an address obtained by adding (N + 1) ^K × L−1 to the global address.

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