JP4784514B2 - List vector processing apparatus and method - Google Patents

Description

  The present invention relates to list vector processing.

  List vector processing is known as a technique for performing computation by a computer at high speed. When a load instruction is executed in the list vector processing, the data recorded at the address on the main storage device indicated by the vector element is read in ascending order of the vector element number and passed to the vector processing device.

  In order to speed up the load instruction in the list vector processing, the following techniques are known. A plurality of vector elements are distributed to different vector processing devices and processed in parallel. In this case, the plurality of vector processing devices compare the vector elements output in the same clock cycle by the coincidence determination circuit. As a result of the comparison, if a plurality of vector elements match, access to the main memory is executed based on only one of the vector elements, and data obtained as a result of the access is obtained for the other vector elements. Is returned. By such processing, the number of accesses to the main memory is reduced, and the speed of the load instruction for the list vector is realized.

Regarding the list vector processing, Patent Document 1 is disclosed.
Japanese Patent Laid-Open No. 10-49520

  An object of the present invention is to provide a list vector processing apparatus and method that enable faster calculation.

  In the following, means for solving the problem will be described using the numbers used in [Best Mode for Carrying Out the Invention] in parentheses. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  The list vector processing apparatus according to the present invention includes the following parts: a first vector data including a plurality of vector elements indicating addresses on a memory is input in a first clock cycle, and a plurality of vectors indicating addresses on the memory Vector data input unit (100, 101, 102, 103) for inputting second vector data including elements in a second clock cycle subsequent to the first clock cycle; the order of element numbers in the first vector data is the last A collation unit (230) for collating the address of the vector element with the address of the first vector element in the order of the element numbers in the second vector data; when the collation results match, Contains the last vector element, the element number is continuous with the last vector element, and indicates the same address An address common vector element group including a vector element including the first vector element in the second vector data, an element number continuous with the first vector element, and a vector element indicating the same address is set. When a command for reading memory information in accordance with the address indicated by the vector element is input to the address common vector element group for the vector element belonging to the address common vector element group. A reply unit (6000) that returns information read out by accessing the memory based on the address indicated by any representative vector element to which it belongs.

  In the list vector processing apparatus according to the present invention, the representative vector element is the last vector element having an element number in the address common vector element group.

  In the list vector processing apparatus according to the present invention, the same address continuous area combining unit (1000) includes the following parts: Control information corresponding to a plurality of vector elements included in the first vector data and having the last flag set And the element number is set in the control information corresponding to the last vector element in the first common vector element group in the first clock cycle that consists of consecutive vector elements indicating the same address in the first vector data. Address common vector recognition unit (110) in the first clock cycle that sets the last flag; and control information corresponding to each of a plurality of vector elements included in the second vector data is generated, and the element number in the first vector data Is the last flag of the last vector element and is the first of the second vector data When the address indicated by the vector element is the same as the address indicated by the last vector element, the last flag is turned off, the same address is indicated in the second vector data, and the addresses in the second clock cycle consisting of consecutive vector elements are common. A control information correction unit (240) that sets a last flag included in the control information corresponding to the last vector element in the vector element group. The last element number of the vector element region belonging to the common address vector element group is designated by the last flag.

  According to the present invention, there is provided a list vector processing apparatus and method that enable faster calculation.

  ADVANTAGE OF THE INVENTION According to this invention, the list vector processing apparatus and method which reduce the frequency | count of access to the main memory in list vector processing, and enable faster calculation are provided.

  FIG. 1 is a conceptual diagram for explaining a list vector processing method according to the present invention. Clock cycle 1 and clock cycle 2 indicate two consecutive clock cycles.

  Process 1: The vector elements of the first vector data output from a plurality of vector processing devices in clock cycle 1 are compared by the address match determination circuit, and vector elements that access the same address in the vector elements of clock cycle 1 are detected. The As a result of the detection, a continuous region including the vector element having the highest element number (the last vector element among the vector elements input in clock cycle 1) and continuing vector elements having the same address is detected. . Among the vector elements included in the continuous region, the smallest element number “2” is found.

  Process 2: The vector element having the smallest element number among the vector elements of the second vector data inputted in clock cycle 2 which is the next clock cycle and the address of the last vector element in clock cycle 1 (in clock cycle 2) The address of the first vector element among the input vector elements) is compared. If the comparison result is the same, the addresses from the vector element having the smallest element number in the continuous area obtained in process 1 to the first vector element of the vector element input in clock cycle 2 must match. I understand. In this case, the smallest element number in the continuous area obtained in process 1 is recorded.

  Process 3: The vector elements input in clock cycle 2 are compared by the address match determination circuit, and a vector element that accesses the same address in the vector elements in clock cycle 2 is detected. As a result of the detection, a continuous area including the vector element at the head and continuous vector elements having the same address is detected. Among the vector elements included in the continuous area, the maximum element number “5” is found.

  By the above processing 1 to processing 3, a region composed of a plurality of vector elements having the same address and having consecutive element numbers is detected, and the first element number and the last element number of the region are determined. For this area, the main memory is accessed based only on the vector element having the largest vector element number. As a result, the number of accesses to the main memory is reduced.

  FIG. 2 shows the configuration of the list vector processing apparatus in the present embodiment. The vector processing devices 3001 to 3004 output vector elements every clock cycle. In this embodiment, the number of vector processing devices 3001 to 3004 is four, and therefore four vector elements are output every clock cycle.

  When receiving a vector element from the vector processing devices 3001 to 3004, the list vector processing device (same address continuous area combining unit) 1000 that performs compression processing detects a vector element having the same address. The vector element having the largest element number among the vector elements having the same address is detected, and the main memory is accessed based only on the detected vector element.

  The main memory control device (request issue) 4000 receives control information and addresses of vector elements from the list vector processing device (compression processing) 1000, and receives data from the vector processing devices 3001 to 3004, and sends a memory request to the main memory. Generate.

  The main memory 5000 receives a memory request from the main memory controller (request issue) 4000, writes data to or reads data from the address indicated by the memory request, and sends the result to the memory reply. Output as.

  When the main memory control device (reply unit) 6000 receives a memory reply from the main memory device 5000, it generates control information and data for vector elements. When the list vector processing device (expansion processing) 2000 receives the control information and data of the vector elements from the main memory control device (reply receiving) 6000, the list vector processing device (expansion processing) 2000 accesses the main memory among the vector elements having the same address from the control information. Restore the element numbers of vector elements that have not been performed. From this process, the vector elements reduced by the list vector processing apparatus (compression process) 1000 are restored.

  Referring to FIG. 3, a detailed configuration of a list vector processing apparatus (compression process) 1000 is shown.

  One vector instruction can process multiple vector elements. When the number of vector elements processed by one instruction is compared with the number of vector processing devices 3001 to 3004, the number of vector elements processed by one instruction is larger. Therefore, when one vector instruction is processed, the vector processing devices 3001 to 3004 repeat the output of up to four vector elements every clock cycle until the number of vector elements processed by the instruction is reached.

  Input REGs 100 to 103 (vector data input unit) take in vector elements output by the vector processing devices 3001 to 3004.

  Control information is generated corresponding to the vector element. The control information is composed of 4-bit information, an element number, and a head element number. In the diagram of this embodiment, the control information is expressed in the order of 4-bit information, element number, and head element number, and is expressed in the format “bbbb [x] [x]”. In the following description, the leftmost bit of the 4-bit information is described as the first bit, and the rightmost bit is described as the fourth bit.

  The first bit of the control information indicates whether or not access to the main memory is performed. When the first bit is 1, the corresponding vector element is controlled to access the main memory. When the first bit is 0, the corresponding vector element is controlled not to access the main memory. When a group of vector elements having the same address in four vector elements of the same clock cycle is named a common vector element group within the same clock, the vector element having the largest element number among the common vector elements within the same clock The first bit of the control information is set to 1, and the first bits of the control information of the other vector elements are set to 0.

  The second bit of the control information indicates that it is a compressible vector element. The control information generation circuit 110 (control information generation circuit in the first clock cycle) compares the addresses of four vector elements in the same clock cycle. When vector elements having the same address exist continuously, the second bit of the control information of the vector element is set to 1. Otherwise, the second bit of the control information of the vector element is set to 0.

  The third bit of the control information indicates that when vector elements having the same address are consecutive, the vector element has the smallest element number among the vector elements. The fourth bit of the control information indicates that when vector elements having the same address are continuous, the vector element has the largest element number among the vector elements.

  The element number of the control information indicates to which vector element the control information is the control information. When vector elements having the same address are consecutive, the largest element number among the vector elements is stored as the element number of the control information.

  The head element number of the control information is set to the same value as the element number of the control information when there is no vector element having the same address. On the other hand, when vector elements having the same address are continuous, the smallest (first) element number of the vector elements is set as the first element number of the control information.

  The address comparison circuit 230 (collation unit) compares the address of the vector element output from the input REG 100 with the address of the vector element output from the carry-around REG 203. If they match, 1 is output, and if they do not match, 0 is output.

  A vector element carried by the address comparison circuit and inputted from the REG 203 is a vector element having the largest element number included in the vector data inputted in the first clock cycle. The vector element input from the input REG 100 by the address comparison circuit is the vector element having the smallest element number included in the vector data input in the second clock cycle subsequent to the first clock cycle.

  The address continuation information REG 260 holds the comparison result output from the address comparison circuit 230. When the output of the address continuation information REG260 is 1, it is indicated that vector elements having the same address are consecutive from the previous clock cycle.

  The control information generation circuit 110 compares the addresses of the four vector elements output from the inputs REG100 to 103 in the same clock cycle, and detects a vector element that accesses the same address in the vector elements.

  As a result of detection, a continuous region in which vector elements having the same address including the largest vector element (the last vector element) among the four vector elements is continuous is detected. Of the vector elements in the continuous area, the control information of the vector element having the smallest element number “S” is output as “0110 [S] [S]”, and the control information of the vector element having the largest element number “L” is output. Is output as “1101 [L] [S]”, and control information of other vector elements is output as “0100 [x] [x]”.

  However, when the control information of the vector element output from the input REG 100 is “0110 [x] [x]” and the output of the address comparison circuit 230 is 1, “0110 [x] [x]” is used as the control information. Instead, “0100 [x] [x]” is generated. The third bit of the control information is information indicating that, when vector elements having the same address are consecutive, the vector element having the smallest element number among the vector elements, and the previous clock cycle. When vector elements having the same address are consecutive, different control information is generated because the condition is not met.

  As a result of the detection, a continuous region in which vector elements having the same address including the smallest vector element (first vector element) among the four vector elements is continuous is detected. When vector elements having the same address exist, the control information of the vector element having the smallest element number “S” among the vector elements in the continuous area is output as “0110 [S] [S]”. The control information of the vector element having the largest element number “L” is output as “1101 [L] [S]”. The control information of other vector elements is output as “0100 [x] [x]”.

  The control information REG210 to 213 holds the control information output from the control information generation circuit 110. The head element number selection circuit 120 is a vector in which the output value of the address comparison circuit 230 is 1 and the control information is “0110 [x] [x]” among the control information output from the control information REG210 to 213. If the element exists, the element number of the vector element is output. When there are a plurality of vector elements whose control information is “0110 [x] [x]”, the element number of the vector element having the largest element number among the vector elements is output. When there is no vector element whose control information is “0110 [x] [x]”, the output of the head element number REG220 is selected.

  The leading element number REG 220 captures the output of the leading element number selection circuit 120. The carrying REGs 200 to 203 take in the vector elements output from the input REGs 100 to 103.

  The control information correction circuit 240 (control information correction unit) has a vector element whose control information output from the control information REG 213 is “1101 [x] [x]”, and the output of the address comparison circuit 230 is 1. In this case, “0100 [x] [x]” is generated instead of “1101 [x] [x]” as the control information. The fourth bit of the control information is information indicating that the vector element having the largest element number among the vector elements when vector elements having the same address are continuous, is one clock cycle after If there is a vector element having the same address, “0100 [x] [x]” is generated as control information because the condition is not met.

  The head element number replacement circuit 250 rewrites information indicating the head element number of the control information of the vector element having the output value of the address continuation information REG260 of 1 and having “1101 [x] [x]” as the control information. Do. The head element number of the control information indicates the head element number of the vector element having the same address continuously in the same clock cycle, and when the output of the address continuation information REG260 is 1, from the previous clock cycle Since vector elements having the same address are continuous, rewriting is performed. When there are a plurality of the vector elements, only the top element number of the control information of the smallest vector element among the vector elements is rewritten.

  Referring to FIG. 4, a detailed configuration of list vector processing device (development processing) 2000 is shown.

  The list vector processing device (development processing) 2000 holds four vector element restoration circuits 2001 to 2004. Since the configuration of the four vector element restoration circuits 2001 to 2004 is the same, only the vector element restoration circuit 2001 will be described in the present embodiment.

  The control information buffer 400 is a buffer that temporarily holds control information output from the main memory control device (reply reception) 6000. When the output of the comparison circuit 540 is 1, the control information buffer 400 outputs control information.

  The data buffer 410 is a buffer that temporarily holds data output from the main memory control device (reply reception) 6000. The data buffer 400 outputs data when the output of the comparison circuit 540 is 1.

  When receiving the control information, the control information decoder 420 outputs the element number and the head element number of the vector element from the control information. The element number is a value stored in the second field of the control information. The head element number is a value stored in the third field of the control information.

  The selection circuit 550 selects the head element number output from the control information decoder 420 when the output of the comparison circuit 540 is 1, and selects the head element number output from the adder 530 when the output of the comparison circuit 540 is 0. To do.

  The selection circuit 551 selects the element number output by the control information decoder 420 when the output of the comparison circuit 540 is 1, and selects the element number output by the element number REG 510 when the output of the comparison circuit 540 is 0.

  The selection circuit 552 selects the data output from the data buffer 410 when the output of the comparison circuit 540 is 1, and selects the element number output from the data REG 520 when the output of the comparison circuit 540 is 0.

  The generation element number REG500 is a register that holds a value output from the selection circuit 550. The element number REG510 is a register that holds a value output from the selection circuit 551. The data REG 520 is a register that holds data output from the selection circuit 552. The adder 530 is an adder that outputs a value obtained by adding +1 to the value output by the head element number REG500.

  The comparison circuit 540 compares the value of the generated element number REG500 and the value of the element number REG510, and outputs 1 if the values match, and outputs 0 if they do not match.

  The element number output REG 600 is a register that holds a value output from the generated element number REG 500. The data output REG 610 is a register that holds data output from the data REG 520. The arbitration circuit 2005 arbitrates the element number and data output from the vector element restoration circuits 2001 to 2004, and outputs the result to the vector processing devices 3001 to 3004.

  Next, the operation of the compression processing performed by the list vector processing apparatus (compression processing) 1000 shown in FIG. 3 will be described using the time chart shown in FIG.

  FIG. 7 is a diagram in which information movement and dependency relationships are supplemented with arrows based on FIG. In the present embodiment, description will be made assuming that the number of vector elements output by the vector processing devices 3001 to 3004 is 12 elements.

  In clock cycle T2, address inputs REG100 to 103 fetch the addresses of vector elements (element numbers 0 to 3) output from vector processing devices 3001 to 3004. Similarly, in the clock cycle T3, the address inputs REG100 to 103 fetch the addresses of the vector elements (element numbers 4 to 7) output from the vector processing devices 3001 to 3004. In clock cycle T4, address inputs REG100 to 103 fetch the addresses of vector elements (element numbers 8 to 11) output from the vector processing devices 3001 to 3004.

  In the clock cycle T3, the address rotation REGs 200 to 203 fetch the addresses of the vector elements (element numbers 0 to 3) output from the address inputs REG100 to 103. Similarly, in the clock cycle T4, the address rotation REGs 200 to 203 fetch the addresses of the vector elements (element numbers 4 to 7) output from the address inputs REG100 to 103. In the clock cycle T5, the address rotation REGs 200 to 203 fetch the addresses of the vector elements (element numbers 8 to 11) output from the address inputs REG100 to 103.

  In the clock cycle T4, the address outputs REG300 to 303 fetch the addresses of the vector elements (element numbers 0 to 3) output from the address carry-over REGs 200 to 203. Similarly, in the clock cycle T5, the address outputs REG300 to 303 fetch the addresses of the vector elements (element numbers 4 to 7) output from the address carry-over REGs 200 to 203. In the clock cycle T6, the address outputs REG300 to 303 fetch the addresses of the vector elements (element numbers 8 to 11) output from the address carry-over REGs 200 to 203.

  In the clock cycle T2, the control information generation circuit 110 receives an address from the address inputs REG100 to 103, and compares addresses between vector elements (element numbers 0 to 3) input in the same clock cycle. Then, the processing in the control information generation circuit 110 described with reference to FIG. 3 is executed. In the clock cycle T2, since the addresses of the vector elements (element numbers 0 to 3) are “YY”, “ZZ”, “AA”, and “AA”, respectively, as control information (element numbers 0 to 3), “1000 [0] [0]”, “1000 [1] [1]”, “0110 [2] [2]”, “1101 [3] [2]” are generated.

  In the clock cycle T3, the control information REG210 to 213 takes in the control information (element numbers 0 to 3) output from the control information generation circuit 110.

  In the clock cycle T3, the address (element number 4) output from the address input REG100 matches the address (element number 3) output from the address carry-over REG200. Therefore, the address comparison circuit 230 outputs 1 as the determination result.

  In the clock cycle T4, the address continuation information REG260 takes in the output value 1 of the address comparison circuit 230.

  In the clock cycle T3, the control information generation circuit 110 receives the address from the address inputs REG100 to 103, and compares the addresses between the vector elements (element numbers 4 to 7) input in the same clock cycle. Then, the processing in the control information generation circuit 110 described with reference to FIG. 3 is executed. In clock cycle T3, the addresses of the vector elements (element numbers 4 to 7) are “AA”, “AA”, “AA”, and “AA”, respectively, and the output of the address comparison circuit 230 is 1. As control information (element numbers 4 to 7), “0100 [4] [4]”, “0100 [5] [5]”, “0100 [6] [6]”, “0100 [7] [4], respectively” Is generated.

  In the clock cycle T4, the control information REG210 to 213 takes in the control information (element numbers 4 to 7) output from the control information generation circuit 110.

  In clock cycle T4, the address (element number 8) output from the address input REG100 matches the address (element number 7) output from the address carry-over REG200. Therefore, the address comparison circuit 230 outputs 1 as the determination result.

  In the clock cycle T5, the address continuation information REG260 takes in the output value 1 of the address comparison circuit 230.

  In the clock cycle T4, the control information generation circuit 110 receives an address from the address inputs REG100 to 103, and compares addresses between vector elements (element numbers 8 to 11) input in the same clock cycle. Then, the processing in the control information generation circuit 110 described with reference to FIG. 3 is executed. In the clock cycle T4, the addresses of the vector elements (element numbers 8 to 11) are “AA”, “AA”, “BB”, and “CC”, respectively, and the output of the address comparison circuit 230 is 1. Therefore, as control information (element numbers 8 to 11), “0100 [8] [8]”, “1101 [9] [8]”, “1000 [10] [10]”, “1000 [11] [ 11] "is generated.

  In the clock cycle T5, the control information REG210 to 213 takes in the control information (element numbers 8 to 11) output from the control information generation circuit 110.

  In clock cycle T5, since there is no vector element in address input REG100, address comparison circuit 230 outputs 0 as the determination result.

  In clock cycle T 6, address continuation information REG 260 captures 0, which is the output value of address comparison circuit 230.

  In the clock cycle T3, the output value of the address comparison circuit 230 is 1, and the control information (element number 2) output by the control information REG212 among the control information (element numbers 0 to 3) output by the control information REG210 to 213. ) Is “0110 [2] [2]”, the leading element number selection circuit 120 outputs 2 which is the element number of the vector element.

  In clock cycle T4, the leading element number REG220 takes in the output value 2 of the leading element number selection circuit 120.

  In the clock cycle T4, since the vector element whose control information is “0110 [x] [x]” does not exist in the control information (element numbers 4 to 7) output from the control information REG210 to 213, the head element number REG220. The output value 2 is output.

  In the clock cycle T5, the leading element number REG220 takes in the output value 2 of the leading element number selection circuit 120.

  Since the output value of the address comparison circuit 230 is 1 in the clock cycle T3, the control information correction circuit 240 changes the control information “1101 [3] [2]” output from the control information REG213 to “0100 [3] [2]. ] "And output.

  In the clock cycle T3, the head element number replacement circuit 250 receives the control information (element numbers 0 to 2) output from the control information REG210 to 212 and the control information (element number 3) output from the control information correction circuit 240. Since the received control information (element numbers 0 to 3) does not have control information of “1101 [x] [x]” (x is arbitrary), the control information (element numbers 0 to 3) is output as it is.

  Since the output value of the address comparison circuit 230 is 1 in the clock cycle T4, the control information correction circuit 240 changes the control information “1101 [7] [4]” output from the control information REG 213 to “0100 [7] [4]. ] "And output.

  In the clock cycle T4, the head element number replacement circuit 250 receives the control information (element numbers 4 to 6) output from the control information REG210 to 212 and the control information (element number 7) output from the control information correction circuit 240. Since the received control information (element numbers 4 to 7) does not have control information “1101 [x] [x]” (x is arbitrary), the control information (element numbers 4 to 7) is output as it is.

  Since the output value of the address comparison circuit 230 is 0 in the clock cycle T5, the control information correction circuit 240 outputs the control information “1000 [11] [11]” output from the control information REG213 as it is.

  In the clock cycle T5, the head element number replacement circuit 250 receives the control information (element numbers 8 to 10) output from the control information REG210 to 212 and the control information (element number 11) output from the control information correction circuit 240. Of the received control information (element numbers 8 to 11), the control information of element number 9 is “1101 [9] [8]”. Therefore, the head element number is replaced with 2 output from the head element number REG220, and “1101 [9] [2]” is output as control information. Other control information (element numbers 8, 10, and 11) is output as it is.

  In the clock cycle T4, the control information outputs REG310 to 313 take in the control information (element numbers 0 to 3) output from the head element number replacement circuit 250. Similarly, in the clock cycle T5, the control information outputs REG310 to 313 take in the control information (element numbers 4 to 7) output from the head element number replacement circuit 250. In the clock cycle T6, the control information outputs REG310 to 313 take in the control information (element numbers 8 to 11) output from the head element number replacement circuit 250.

  As a subsequent process, the main memory control device (request issuance) fetches an address from the address outputs REG300 to 303, fetches control information from the control information outputs REG310 to 313, and fetches data from the vector processing devices 3001 to 3004. Generate a memory request for. At this time, a request is generated only for the vector element corresponding to control information “1xxx [x] [x]” (x is arbitrary), and a request is not generated for a vector element not corresponding to the control information. This reduces the number of accesses to the main memory.

  Next, the operation of the compression process of FIG. 4 will be described using the time chart shown in FIG. Here, description will be made assuming that control information is stored in the control information buffer 400 in advance and data is stored in the data buffer 410.

  In the clock cycle T1, since the output value of the comparison circuit 540 is 1, the control information buffer 400 outputs the control information “1000 [1] [1]” stored in the buffer.

  In the clock cycle T1, since the output value of the comparison circuit 540 is 1, the data buffer 410 outputs the data “DATA1” stored in the buffer.

  When the control information decoder 420 receives the control information “1000 [1] [1]” from the control information buffer 400 in the clock cycle T1, it extracts the first element number “1” and the element number “1” from the control information. The extracted head element number is output to the selection circuit 550, and the extracted element number is output to the selection circuit 551.

  In the clock cycle T1, since the output value of the comparison circuit 540 is 1, the selection circuit 550 selects the head element number “1” from the control information decoder 420 and outputs the value.

  In the clock cycle T2, the generation element number REG500 takes in the head element number “1” output from the selection circuit 550.

  In the clock cycle T1, since the output value of the comparison circuit 540 is 1, the selection circuit 551 selects the element number “1” from the control information decoder 420 and outputs the value.

  In the clock cycle T2, the element number REG510 takes in the head element number “1” output from the selection circuit 551.

  In the clock cycle T1, since the output value of the comparison circuit 540 is 1, the selection circuit 552 selects the data “DATA1” output from the data buffer 410 and outputs the value.

  In the clock cycle T 2, the data REG 520 takes in the data “DATA 1” output from the selection circuit 552.

  In the clock cycle T2, the comparison circuit 540 compares the output value of the generated element number REG500 with the output value of the element number REG510, and outputs 1 as the determination result.

  In the clock cycle T3, the element number output REG600 takes in the element number “1” output from the generated element number REG500.

  In the clock cycle T3, the data output REG610 takes in the data “DATA1” output from the data REG520.

  In the clock cycle T2, since the output value of the comparison circuit 540 is 1, the control information buffer 400 outputs the control information “1101 [9] [7]” stored in the buffer.

  In the clock cycle T2, since the output value of the comparison circuit 540 is 1, the data buffer 410 outputs the data “DATA2” stored in the buffer.

  When receiving the control information “1101 [9] [7]” from the control information buffer 400 in the clock cycle T2, the control information decoder 420 extracts the first element number “7” and the element number “9” from the control information. The extracted head element number “7” is output to the selection circuit 550, and the extracted element number “9” is output to the selection circuit 551.

  In the clock cycle T2, since the output value of the comparison circuit 540 is 1, the selection circuit 550 selects the head element number “7” from the control information decoder 420 and outputs the value.

  In the clock cycle T 3, the generation element number REG 500 captures the head element number “7” output from the selection circuit 550.

  In the clock cycle T2, since the output value of the comparison circuit 540 is 1, the selection circuit 551 selects the element number “9” from the control information decoder 420 and outputs the value.

  In the clock cycle T3, the element number REG510 takes in the head element number “9” output from the selection circuit 551.

  In the clock cycle T2, since the output value of the comparison circuit 540 is 1, the selection circuit 552 selects the data “DATA2” output from the data buffer 410 and outputs the value.

  In the clock cycle T3, the data REG520 takes in the data “DATA2” output from the selection circuit 552.

  In clock cycle T3, adder 530 calculates “output value of generated element number REG500 + 1 (7 + 1)” and outputs 8 which is the calculation result.

  In the clock cycle T3, the comparison circuit 540 compares the output value of the generated element number REG500 and the output value of the element number REG510, and outputs 0 as the determination result because they do not match.

  In clock cycle T4, the element number output REG600 takes in the element number “7” output from the generated element number REG500.

  In the clock cycle T4, the data output REG610 takes in the data “DATA2” output from the data REG520.

  Since the output value of the comparison circuit 540 is 0 in the clock cycle T3, the selection circuit 550 selects the value “8” output from the adder 530 and outputs the value.

  In the clock cycle T4, the generation element number REG500 takes in the value “8” output from the selection circuit 550.

  Since the output value of the comparison circuit 540 is 0 in the clock cycle T3, the selection circuit 551 selects the element number “9” from the element number REG510 and outputs the value.

  In the clock cycle T4, the element number REG510 takes in the head element number “9” output from the selection circuit 551.

  In the clock cycle T3, since the output value of the comparison circuit 540 is 0, the selection circuit 552 selects the data “DATA2” output from the data REG520 and outputs the value.

  In the clock cycle T4, the data REG520 takes in the data “DATA2” output from the selection circuit 552.

  In clock cycle T4, adder 530 calculates “output value of generated element number REG500 + 1 (8 + 1)” and outputs 9 as the calculation result.

  In the clock cycle T4, the comparison circuit 540 compares the output value of the generated element number REG500 and the output value of the element number REG510, and outputs 0 as the determination result because they do not match.

  In clock cycle T5, the element number output REG600 takes in the element number “8” output from the generated element number REG500.

  In the clock cycle T5, the data output REG610 takes in the data “DATA2” output from the data REG520.

  In the clock cycle T4, since the output value of the comparison circuit 540 is 0, the selection circuit 550 selects the value “9” output from the adder 530 and outputs the value.

In the clock cycle T5, the generation element number REG500 takes in the value “9” output from the selection circuit 550.

  In the clock cycle T4, since the output value of the comparison circuit 540 is 0, the selection circuit 551 selects the element number “9” from the element number REG510 and outputs the value.

In the clock cycle T5, the element number REG510 takes in the head element number “9” output from the selection circuit 551.

  In the clock cycle T4, since the output value of the comparison circuit 540 is 0, the selection circuit 552 selects the data “DATA2” output from the data REG520 and outputs the value.

  In the clock cycle T5, the data REG520 takes in the data “DATA2” output from the selection circuit 552.

  In the clock cycle T5, the comparison circuit 540 compares the output value of the generation element number REG500 and the output value of the element number REG510, and outputs 1 as the determination result because they match.

  In clock cycle T6, the element number output REG600 takes in the element number “9” output from the generated element number REG500.

  In the clock cycle T6, the data output REG610 takes in the data “DATA2” output from the data REG520.

  Thereafter, by repeating the same processing, the list vector processing device (decompression processing) 2000 can restore the requests reduced by the list vector processing device (compression processing) 1000.

  The element number fetched by the element number output REG 600 and the data fetched by the data output REG 610 are output to the arbitration circuit 2005 thereafter. The arbitration circuit 2005 performs competitive arbitration on the captured data, and then outputs the data to the vector processing devices 3001 to 3004.

FIG. 1 is a conceptual diagram for explaining a list vector processing apparatus according to the present invention. FIG. 2 shows the configuration of the list vector processing apparatus. FIG. 3 shows the configuration of the list vector processing device (compression processing). FIG. 4 shows the configuration of the list vector processing device (development processing). FIG. 5 is a time chart showing the operation of the compression processing performed by the list vector processing device (compression processing). FIG. 6 is a time chart showing the operation of the compression process. FIG. 7 is a time chart illustrating information movement and dependency in the operation of compression processing performed by the list vector processing device (compression processing).

Explanation of symbols

420 ... Control information decoder 530 ... Adder 540 ... Comparison circuit 550-552 ... Selection circuit 1000 ... List vector processing device (compression processing)
2000 ... List vector processing device (development processing)
2001-2004 ... Vector element restoration circuit

Claims (4)

First vector data including a plurality of vector elements indicating addresses on the memory is input in a first clock cycle, and second vector data including a plurality of vector elements indicating addresses on the memory is input to the first clock cycle. A vector data input section for input in a subsequent second clock cycle;
A matching unit that performs matching between the address of the last vector element in the order of element numbers in the first vector data and the address of the first vector element in the order of element numbers in the second vector data;
When the result of the collation matches, the first vector data includes the last vector element, the element number is continuous with the last vector element, and indicates the same address; The same address continuous area for setting an address common vector element group including the first vector element in two vector data, the element number being continuous with the first vector element, and the vector element indicating the same address A coupling part;
When a command for reading the memory information is input according to the address indicated in the vector element, the vector element belonging to the address common vector element group is indicated in any representative vector element belonging to the address common vector element group. A reply unit that returns information read by accessing the memory based on the address to be read ,
The list vector processing device, wherein the representative vector element is the last vector element in the common address vector element group. A list vector processing apparatus according to claim 1,
The same address continuous area combination part is:
A first clock composed of successive vector elements indicating the same address in the first vector data, each corresponding to a plurality of vector elements included in the first vector data, generating control information in which a last flag is set. An address common vector recognizing unit in the first clock cycle that sets the last flag set in the control information corresponding to the last vector element in the cycle common address vector element group;
Control information corresponding to each of a plurality of vector elements included in the second vector data is generated, the last flag of the last vector element having an element number in the first vector data is set, and the second vector When the address indicated by the first vector element in the data is the same as the address indicated by the last vector element, the last flag is defeated and the same vector address indicating the same address is indicated in the second vector data. A control information correction unit for setting the last flag included in the control information corresponding to the last vector element having an element number in the second clock cycle address common vector element group consisting of
And
A list vector processing apparatus in which a last element number of a vector element region belonging to the address common vector element group is designated by the last flag .   First vector data including a plurality of vector elements indicating addresses on the memory is input in a first clock cycle, and second vector data including a plurality of vector elements indicating addresses on the memory is input to the first clock cycle. A vector data input step for inputting in a subsequent second clock cycle;
  A collation step of performing collation between an address of a vector element whose element number is last in the first vector data and an address of a vector element whose element number is first in the second vector data;
  When the result of the collation matches, the first vector data includes the last vector element, the element number is continuous with the last vector element, and indicates the same address; The same address continuous region combining step for setting an address common vector element group including the first vector in two vector data, the element number being continuous with the first vector, and the vector element indicating the same address;
  When a command for reading the memory information is input according to the address indicated in the vector element, the vector element belonging to the address common vector element group is indicated in any representative vector element belonging to the address common vector element group. A reply step for returning information read by accessing the memory based on the address to be read,
  The representative vector element is an address element having the last element number in the address common vector element group.
  List vector processing method.   The list vector processing method according to claim 3, wherein
  The same address continuous region combining step includes:
  A first clock composed of successive vector elements indicating the same address in the first vector data, each corresponding to a plurality of vector elements included in the first vector data, generating control information in which a last flag is set. A first clock cycle address common vector recognition step for setting the last flag set in the control information whose element number corresponds to the last vector element in the in-cycle address common vector element group;
  Control information corresponding to each of a plurality of vector elements included in the second vector data is generated, the last flag of the last vector element having an element number in the first vector data is set, and the second vector When the address indicated by the first vector element in the data is the same as the address indicated by the last vector element, the last flag is defeated and the same vector address indicating the same address is indicated in the second vector data. A control information correction step for setting the last flag included in the control information whose element number corresponds to the last vector element in the address common vector element group in the second clock cycle consisting of:
  The last element number of the vector element region belonging to the common address vector element group is specified by the last flag.
  List vector processing method.

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