JPH11232279A - Method and device for split search - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten processing time by optimizing a processing to read searching object data from a storage device and improving search processing speed. SOLUTION: The searching object data is stored in a first bank when a value of two bits at the side of an LSB of a searching address is '00', and is stored in a second bank when the value is '01', and is stored in a third bank when the value is '10' and is stored in a fourth bank when the value is '11'. The bank in which the data is stored is adjusted by shifting the address. When plural pieces of the searching object data are read, simultaneous reading of these data is enabled by setting the addresses of each piece of the searching object data so that the banks in which these data are stored are different from one another and time to be required for search is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a divided search method for reading out search target data stored at consecutive addresses one by one in ascending or descending order according to the value of search target data and comparing and comparing the search data with search key comparison data. Related to the device, especially
A divided search method and apparatus capable of improving the search processing speed and shortening the processing time while optimizing the processing of reading the search target data from the storage device and using the same single-port memory as the conventional one in the read speed. About.

[0002]

2. Description of the Related Art For example, as shown in FIG. 1, a search address is (n + 1) bits, and a total of 2 ^{(n + 1 )} search target data are stored in ascending or descending order according to the value. . As described above, consider the processing in the binary search method in which the search target data stored at successive search addresses is read out one by one and compared with the comparison data of the search key.

In this case, in the binary search, usually, the first search address is “1000” indicated by reference numeral A6 in the figure, which is intermediate in the address space of consecutive addresses.
00 ... 0000 "Also, according to the comparison result between the data at the search address and the comparison data of the search key, the next search address is" 010000 ... "of the code A3.
… 0000 ”or“ 110000… 0000 ”
Becomes

In the binary search, the search address space is divided into two with the middle address of the search address space as a boundary, and the address at the boundary, that is, the data at the search address is compared with the comparison data. Further, one of the two divided address spaces is adopted according to the comparison result, and the adopted address space is set as the next search address space. Thereafter, similarly, the process is repeated with an intermediate address in the current search address space as a boundary. In the binary search, target data is found while sequentially dividing the search address space into two.

The binary search method is often used as a search method for a large amount of data because the search time for N (N = 2 ⁿ ) data is proportional to log (N). In the case of a bisection search device having a configuration as shown in FIG. 2, one process includes one process of reading data from the search target data storage device 30 as shown in FIG. 1 for comparison with data
It consists of two processes. As illustrated, in the binary search, the reading process and the comparing process are repeated. Here, the time for reading and comparing is defined as Ct. Then, the total processing time T is as follows.

T = 2 × Ct × log (N) (1)

In FIG. 2, an address setting device 1
0A and the search target data storage device 30 are connected by the address bus 5. The search data register 22A of the data comparison device 20A and the search target data storage device 30 are connected by the data bus 7. The address setting device 10A sequentially outputs the search addresses during the binary search. The search target data storage device 30 outputs the search target data corresponding to the search address to the search data register 22A of the data comparison device 20A. The data comparison device 20A compares the data in the search data register 22A with
The data is compared with the data to be searched which is set in advance in the comparison data register 24A.

[0008]

Here, in the above-described binary search, a multi-division search method in which the search target area is divided into two or more is also conceivable. In the case where the data is divided into a large number in this way, the time required for the search cannot be reduced unless reading or comparison of a plurality of data during the search is performed simultaneously. Rather, it is extended.

For example, assume that the number of divisions is M = 2 ^m, and a total of M data read from each area are compared at once. Even if the simultaneous comparison is performed as described above, it takes (M + 1) cycles for one comparison when the reading of M data is sequentially performed one by one. The processing time Ta until the search is completed is as follows.

Ta = (M + 1) × Ct × log (N) / m = (M + 1) / m × Ct × log (N) (2)

If R in the following equation is 1 or less with respect to the processing time T of the binary search, it can be said that the processing time is shortened.

R = Ta / T = {(M + 1) / m × Ct × log (N)} / {2 × Ct × log (N)} = {(M + 1) / m} / 2 (3)

In the above equation (3), (M ≧ 4) and (m ≧ 2). Therefore, R is at least 1.25
Thus, the multi-division search requires more processing time than the binary search. In the multi-segment search, although the number of comparisons is reduced as compared with the binary search, the number of times data is read increases, and as a result, the processing time becomes longer as a whole.

Here, a single-port memory refers to each memory cell of a built-in memory cell matrix.
It is a common memory with a set of word lines and bit lines. For the single-port memory, on the other hand, the two-port memory or the multi-port memory includes two or more sets of word lines and bit lines for each memory cell. make use of,
This is a special memory that can simultaneously access different built-in memory cells.

If such a two-port memory or a multi-port memory is used, a plurality of data can be read at the same time, and even if the number of data reading in the multi-division search increases, the processing time is reduced by simultaneous reading. be able to. However, in general, the use of special memories, such as a two-port memory or a multi-port memory, is not desirable and may not be possible in some cases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. The present invention aims at optimizing a process of reading data to be searched from a storage device and using a single-port memory having the same read speed as the conventional one. An object of the present invention is to provide a binary search method and apparatus capable of improving a search processing speed and shortening a processing time.

[0017]

First, a divided search method according to the first invention of the present application reads out search target data stored at consecutive addresses one by one in ascending or descending order according to the value of search target data, and searches for the search key. In the divided search method of performing comparison and comparison with the comparison data, the search target data is sequentially allocated to and stored in four or more power-of-two different storage devices in the order of the consecutive addresses, and the plurality of the search data are stored. When reading the target data, the addresses of the respective search target data are set so that the storage devices storing these data are different from each other, so that these data can be read simultaneously, and the time required for the search is reduced. Thereby, the above-mentioned problem has been solved.

Next, the divided search device according to the second invention of the present application
In a divided search device that sequentially reads out search target data stored at consecutive addresses in order of increasing or descending according to the value of the search target data and compares and compares the search target data with search key comparison data, the search target data is Four or more 2 which are sequentially allocated and stored in different things sequentially
When reading out a number of storage devices and a plurality of the search target data, an address of each search target data is set so that the storage devices storing these data are different from each other, and reading of these data is performed. The present invention solves the above problem by providing an address setting device that enables simultaneous operation and a data comparison device that performs the comparison and collation, so that reading from a plurality of the storage devices can be performed at the same time, and the time required for searching is reduced. Things.

Hereinafter, the operation of the first and second aspects of the present invention will be briefly described.

The reason why the overall processing time in the multi-partition search is longer than that in the binary search is that the number of data readings increases. For this reason, in the present invention, a multi-division search is employed, and a plurality of data readings performed in one comparison are simultaneously performed.

Even if simultaneous reading of a plurality of data is enabled, special care is taken so that a special memory such as a two-port memory or a multi-port memory is not required. That is, for the simultaneous reading, in the present invention, the data to be read at the same time is stored in different storage devices.

More specifically, the search target data is sequentially allocated to and stored in four or more power-of-two different storage devices sequentially in the order of the consecutive addresses. When the data is sequentially stored in different storage devices, the adjacent address data of the search target data at a certain address is stored in a different storage device. Therefore, when reading out a plurality of search target data, by shifting the address, the storage device storing the data can be selected, and the storage devices of the plurality of data can be different from each other. Further, if the storage devices for a plurality of data are different from each other, the data can be read simultaneously, and the time required for the search can be reduced.

Therefore, according to the present invention, even if the number of data readings is increased by employing the multi-segment search, the reading time can be shortened or reduced by simultaneous reading. In addition, the number of comparisons is reduced by employing the multi-division search. As a result, in the present invention, the processing for reading the search target data from the storage device is optimized, and the search processing speed is improved and the processing time is reduced while using a single-port memory having the same read speed as the conventional one. Can be.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 4 is a block diagram showing a configuration of a divided search device to which the present invention is applied.

In FIG. 4, a search target data storage device M
1 to Mj are provided as four or more powers of two. Here, the number is j. An address setting device 10,
A total of j sets of search target data storage devices M1 to Mj are connected by a total of j sets of address buses AB1 to ABj. A search data register 22 of the data comparison device 20;
A total of j data buses DB1 to DBj are connected to a total of j search target data storage devices M1 to Mj.
Further, a signal line indicating a comparison result is connected from the data comparison device 20 to the address setting device 10.

The address setting device 10 performs a search
Different search addresses are simultaneously output to the search target data storage devices M1 to Mj. The search target data storage devices M1 to Mj simultaneously output the corresponding search target data to the search data register 22 of the data comparison device 20 at the same time. Further, the data comparison device 20 compares and compares the plurality of search target data in the search data register 22 with the comparison data of the search key stored in the comparison data register 24 at the same time, and determines whether or not they match.

In this embodiment, first, as a divided search device, search target data is stored at consecutive addresses in ascending or descending order according to the value. These search target data are sequentially allocated to different data in the search target data storage devices M1 to Mj in the order of the consecutive addresses and stored. That is, at the above-mentioned consecutive addresses, certain search target data is stored in the search target data storage device M1.
Is stored in the search target data storage device M2, the next data is stored in the search target data storage device M3, and so on. M1 to Mj.

Here, the present embodiment will be described on the premise of the conditions listed below.

B1. Assume that the search address is (n + 1) bits. That is, the number of search target data is 2
Suppose that there were ^{(n + 1)} pieces.

B2. Search target data storage devices M1 to Mj
Is four. That is, j = 4.

B3. LSB of search address (least sign
It is assumed that the search target data in which the value of the two bits on the significant bit side is “00” is stored in the search target data storage device M1 (hereinafter referred to as a first bank). It is assumed that the search target data whose 2-bit value is “01” is stored in the search target data storage device M2 (hereinafter, referred to as a second bank). It is assumed that the search target data whose 2-bit value is “10” is stored in the search target data storage device M3 (hereinafter, referred to as a third bank). It is assumed that the search target data whose 2-bit value is “11” is stored in the search target data storage device M4 (hereinafter, referred to as a fourth bank).

Based on the above conditions B1 to B3, the bank numbers in which the respective search target data are stored are, for example, as shown in the rightmost column of FIG.

Here, the search target data to be searched is 2
Suppose there are ^{(n + 1)} items. At this time, it is preferable that the four search target data read out for one comparison and collation exist at equal intervals at consecutive addresses. In addition, these search target data are arranged in ascending order of address, such as first search target data, second search target data, third search target data,
And the fourth search target data.

Under this condition, the following comparative example is considered.
That is, extremely simply, the first search target data, the second search target data, the third search target data, and the fourth search target data are at equal or substantially equal intervals in continuous addresses.
That is, the number of search target data is (2 ^(n-1) -1) intervals. For example, in FIG. 1, considering the first comparison / collation, the first search target data is the search target data of the first bank having the code A1 and the data number “1”. The second search target data is the search target data of the first bank, which has the code A3 and the data number of “2 ⁽ⁿ⁻¹⁾ +1”. The third search target data is the search target data of the first bank, which has the code A6 and the data number of “2 ⁿ +1”. The fourth search target data is not shown,
The data number is “2 ⁿ +2 ⁽ⁿ⁻¹⁾ +1”, which is also the search target data of the first bank.

In this comparative example, all the search target data is read from the first bank. Therefore, the first search target data, the second search target data, the third search target data, and the fourth search target data cannot be read out at the same time, and the process as shown in FIG. 5 has to be performed.

When the present invention is applied, on the other hand, at the time of reading the search target data, the addresses are shifted as necessary, so that the first search target data, the second search target data, the third search target data, The fourth search target data may be stored in different banks (storage devices). Therefore, these search target data can be read out simultaneously and processed as shown in FIG.

For example, if the search target data to be searched is 2
Suppose there are ^{(n + 1)} items. In this case, for example, the 2 ^{(n + 1)} start addresses in the continuous address,
That is, a total of 2 ⁽ⁿ⁻¹⁾ search target data exist between the address of the first search target data and the address of the second search target data. Between the address of the second search target data and the address of the third search target data, a total of 2 ^{(n -1)} search target data exist. Between the address of the third search target data and the address of the fourth search target data, a total of 2 ^{( n -1)} search target data exist. However,
Between the address of the fourth search target data and the final data, that is, the address of the first search target data, a total of (2 ⁽ⁿ⁻¹⁾ −4) search target data exist. Then, the first search target data and the second
The search target data, the third search target data, and the fourth search target data may be stored in different banks (storage devices).

Here, the numbers in these four sections, that is, 2 ^(n-1) , 2 ^(n-1) , 2
^{The sum of (n-1)} , (2 ^(n-1) -4) and each of the search target data is 2 ^{(n + 1)} , and all data are covered I understand.

Here, as an example, as a specific example, as the first comparison and collation in FIG. 1, the first search target data is the search target data of the first bank having the code A1 and the data number "1". Becomes The second search target data is a code A4
And the data number is "2 ^(n-1) +2", which is the search target data of the second bank. The third search target data is a code A
8, the data number becomes “2 ⁿ +3”, the search target data of the third bank. The fourth search target data is the search target data of the fourth bank having the code A11 and the data number “2 ⁿ +2 ⁽ⁿ⁻¹⁾ +4”.

Therefore, the first search target data, the second
The search target data, the third search target data, and the fourth search target data may be stored in different banks (storage devices). It should be noted that reference signs A2 to A3, reference signs A5 to A7, reference signs A9 to A1.
Up to 0, the search target data is 2 ^(n-1) . In addition, the codes A12 to A14 have (2 ^(n-1) -4) search target data.

Hereinafter, a description will be given of an example (hereinafter, referred to as an embodiment) of the division search method to which the present invention is applied, in which the start address is an even number.

In this embodiment, the conditions B1 to B
It is assumed that 3 holds.

First, at the time of the first comparison reference, four search target data are simultaneously read from each bank as described below. Here, the head address of the target continuous address is hereinafter referred to as a reference address. For example, in the first stage, the reference address is “000000...
000 ".

“000000... 0000”: First bank “010000... 0001”: Second bank “100000... 0010”: Third bank “110000... 0011”: Fourth bank

Of these four addresses, the largest one that satisfies (search key) <(data read from the corresponding address) is set as the next reference address. For example, if the following four inequalities hold, "0100
00 ... 0001 "is the reference address.

(Search key) <(search target data of “000000... 0000”) (4) (search key) <(search target data of “010000... 0001”) (5) (search key) )> (Search target data of “100000... 0010”) (6) (search key)> (search target data of “110000... 0011”) (7)

In the above equations (4) to (7), when the left side and the right side are equal, the data is the search target data, so that it is not necessary to proceed with the search further.

Hereafter, each bit of the (n + 1) digit search address is added to “x”,
“A” to “H”, “a” to “h”, and “w” to
Expressed by "z". In addition, these “x”, “A” to “H”,
1 for each of “a” to “h” and “w” to “z”
The character shall represent one bit whose value is "0" or "1".

Then, the search addresses for reading the search target data in each of the second to (n + 1) / 2 times (each time is m-th) are as follows.

Address of the first bank = “xxx ... xxxAB000 ... 0wab” (8) Address of the second bank = “xxx ... xxxCD000 ... 0xcd” (9) Address of the third bank = “Xxx …… xxxEF000 …… 0yef” (10) Address of the fourth bank = “xxx …… xxxGH000 ... 0zgh” (11)

Here, in the bit strings (5) to (4), the MSB indicated by “xxx... Xxx”
The length of the bit string from the (most significant bit) to the left side of “AB”, “CD” or “EF” is ｛(m−1)
× 2｝ bits. The bit string has the same value as {(m−1) × 2} bits from the MSB of the base address at that time.

The two-bit bit strings indicated by A to H are as shown in the following binary numbers.

AB = 00 (12) CD = 01 (13) EF = 10 (14) GH = 11 (15)

Further, "a" to "h" and "w" to
The bit strings of 1 to 3 bits represented by “z” are as shown in the following binary numbers.

W = 0 (16) ab = (lower 2 bits of reference address) +1 xcd = ab + 1 (17) yef = cd + 1 (18) zgh = ef + 1 (19)

For example, when the search address is 6 bits, that is, when (n = 5), and processing is performed on a total of 64 pieces of search target data, the one to which the present invention is applied is shown in FIG.
(First half of continuous address) and FIG. 8 (second half). FIG. 9 (first half of a continuous address) and FIG. 10 (second half) are comparative examples under similar conditions.

In FIGS. 7 to 10, the reading of the search target data and the comparison and reference are performed in the order of "first time", "second time", and "third time" shown in FIG. Proceed to the right. In the first half and the second half of the continuous address, and in each of the first and third examples of the application of the present invention and the comparative example, 6 bits surrounded by a frame are four in each of the first to third times. Are search addresses indicating search target data to be read from each bank (these four search addresses are hereinafter referred to as reference addresses).
Here, the second reference address is determined by comparing and matching the search target data of the four reference addresses in the first time, and the third reference address is similarly determined in the same manner.

In FIGS. 7 and 8, the second reference address may be close to each other. For this reason, there is an overlapping third reference address determined from a different second reference address. For this reason, in FIGS. 7 and 8, the third time is shown by (A) and (B).
One is shown.

For example, the second reference address “010”
000 ", four third reference addresses following" 010001 "," 010010 "," 01001 "
7 (third time (A) in FIG. 7), and a second reference address “01001”.
The four third reference addresses following "0"
There are “010011”, “010100”, “010101”, and “010110” (the third (B) in FIG. 7).
Among these different second reference addresses, “01001” is included in each of the four third reference addresses.
"1" and "010100" overlap.

Focusing on the LSB of the reference address and the two bits adjacent thereto, first, in FIGS. 7 and 8 to which the present invention is applied, in any of the first to third times, the four reference addresses in that time are: Because one is “00”,
This is the first bank. One is “01”, so the second
It is a bank. One is "10", which is the third bank. One is “11”, which is the fourth bank. For example, in the first round, four reference addresses are:
“000000”, “010001”, “10001”
0 "and" 110011 "In FIGS. 7 and 8 to which the present invention is applied, in each of the first to third rounds, four banks from the first to fourth banks, which are different from each other, Since two search target data are read, the reading can be performed at the same time.

On the other hand, when attention is paid to the same two bits, in FIGS. 9 and 10 of the comparative example, in the first and second rounds, all of the reference addresses in the round are “0”.
0 ", which is a common first bank. Therefore, simultaneous reading cannot be performed because the bank is a common bank.

[0063]

According to the present invention, the processing for reading the search target data from the storage device is optimized, and the search processing speed is improved while using the same single-port memory as the conventional one, and the processing time is improved. Can be shortened. In a conventional binary search, N searches are (2 × Ct × l
og (N)). On the other hand, in the present invention, assuming that the number of divisions is m, ｛(2 / log
(M)) × (Ct × log (N))}. For example, when the number of divisions is 4, the processing time is:
(Ct × log (N)), and the search can be performed in half the processing time of the related art.

[Brief description of the drawings]

FIG. 1 is a diagram relating to a search address showing a process of a binary search.

FIG. 2 is a block diagram showing a configuration of a conventional binary search device.

FIG. 3 is a diagram showing readout of search target data and comparison and collation in the above-described binary search device.

FIG. 4 is a block diagram showing a configuration of an embodiment of a multi-segment search device to which the present invention is applied.

FIG. 5 is a diagram showing reading of search target data and comparison and collation of a comparative example for the embodiment.

FIG. 6 is a diagram showing reading of search target data and comparison and collation in the embodiment.

FIG. 7 is a diagram of the first half of an address showing reading of search target data in a search according to an embodiment of the divided search method to which the present invention is applied;

FIG. 8 is a diagram of the latter half of the address showing the above-mentioned reading.

FIG. 9 is a diagram of the first half of an address showing reading of search target data in a search of a comparative example with respect to the embodiment.

FIG. 10 is a diagram of the latter half of the address showing the above-mentioned reading.

[Explanation of symbols]

 10, 10A address setting device 20, 20A data comparison device 22, 22A search data register 24, 24A comparison data register 30, M1 to Mj search target data storage device

Claims (2)

[Claims] 1. A divided search method for reading out search target data stored at consecutive addresses one by one in ascending or descending order according to the value of search target data, and comparing and comparing the search target data with search key comparison data. , 4 in the order of the consecutive addresses.
One or more powers of two are allocated and stored in mutually different storage devices, and when a plurality of the search target data are read out, each search target is stored such that the storage devices storing these data are different from each other. A divided search method characterized in that data addresses are set so that these data can be read at the same time and the time required for the search is reduced. 2. A divided search apparatus which reads out search target data stored at consecutive addresses one by one in ascending order or descending order according to the value of search target data and compares and compares the search target data with search key comparison data. , Four or more power-of-two storage devices that are sequentially allocated and stored in different ones in the order of the consecutive addresses, and the storage device that stores a plurality of the search target data when reading out the plurality of search target data. An address setting device that sets the address of each search target data so that the devices are different from each other so that these data can be read simultaneously; and a data comparison device that performs the comparison and collation. A divided search device wherein reading is performed simultaneously to reduce the time required for search.