JPS63240527A - Thin film transistor array - Google Patents

Thin film transistor array

Info

Publication number
JPS63240527A
JPS63240527A JP62074671A JP7467187A JPS63240527A JP S63240527 A JPS63240527 A JP S63240527A JP 62074671 A JP62074671 A JP 62074671A JP 7467187 A JP7467187 A JP 7467187A JP S63240527 A JPS63240527 A JP S63240527A
Authority
JP
Japan
Prior art keywords
thin film
scanning
film transistor
wire
transistor array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62074671A
Other languages
Japanese (ja)
Inventor
Yoshitake Hayashi
祥剛 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62074671A priority Critical patent/JPS63240527A/en
Publication of JPS63240527A publication Critical patent/JPS63240527A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306Details
    • G02F1/1309Repairing; Testing

Abstract

PURPOSE:To obtain thin film transistors having the structure in which the defective transistors and defective parts can be easily disconnected from scanning wire and signal wire by providing >=1 points of bridge parts to the scanning wires and signal wires with respect to one picture element of the thin film transistor array. CONSTITUTION:The bright part 9 of the signal wire is provided at the part intersecting with the scanning wire 1 to relay the signal wire 2 and the bridge parts 10 of the scanning wire are provided at two points on both sides of the juncture of the scanning wire 1 and gate electrodes 7. For example, the bridge parts 10a and 10b are cut by a laser beam 15 by which the defective part can be isolated when a short-circuiting 14 is generated by a counter electrode 12 and the scanning wire 1. The defectless display image is obtd. by impressing an input voltage to the scanning wire 1 from both sides thereof at this time. The short circuiting at the intersected part and the defect of the thin film transistors can be similarly corrected by selecting and cutting the cutting points of the scanning wire 1 and the signal wire 2 according to a defect mode. The defective image display by the defects of the thin film transistors are thereby decreased and the defects by cross-shortings and counter electrode-shortings are eliminated without increasing the line resistance.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はアクティブマトリクス方式液晶表示装置に用い
られる薄膜トランジスタアレイに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film transistor array used in an active matrix liquid crystal display device.

従来の技術 近年、従来のCRTに代わる新しい表示装置の開発が盛
んに行なわれるようになってきた。その中でも液晶表示
装置は薄型で低電力動作が可能であるため、自動車、時
計、家電と市場での期待は大きいものがある。
2. Description of the Related Art In recent years, new display devices to replace conventional CRTs have been actively developed. Among these, liquid crystal display devices are thin and can operate with low power, so they have high expectations in the markets of automobiles, watches, and home appliances.

従来、液晶表示装置は単純駆動方式で小型のものが多か
ったが、コントラストが悪く、高密度化。
Conventionally, liquid crystal display devices used a simple drive method and were often small, but the contrast was poor and the density was high.

大型化が難しいため、各絵素を独立で動作させるアクテ
ィブマトリクス方式の表示装置が有望となってきている
。中でも薄膜トランジスタによる駆動方式の液晶表示装
置として高密度な1〜5インチサイズの小型テレビなど
市場が拡大されてきている。さらに今後は10〜20イ
ンチサイズや小型サイズを拡大投映する液晶ライトパル
プを利用した投写型テレビなど将来的に有望な商品の研
究開発が進んでいる。
Since it is difficult to increase the size, active matrix display devices, in which each picture element operates independently, are becoming promising. Among them, the market for liquid crystal display devices driven by thin film transistors, such as high-density compact televisions of 1 to 5 inches in size, is expanding. Furthermore, research and development is progressing on promising products such as projection televisions using liquid crystal light pulp that can enlarge images of 10 to 20 inches or small sizes.

以下図面を参照しながら、上述した従来の薄膜トランジ
スタアレイの一例について説明する。
An example of the conventional thin film transistor array mentioned above will be described below with reference to the drawings.

第8図は従来の薄膜トランジスタアレイの平面構成図を
示すものである。第8図において、1は走査線でゲート
電極7に接続されている。2は信号線でソース電極6と
接続されており走査線との交差部は絶縁膜3で絶縁され
ている。5はドレイン電極で絵素電極4と接続されてい
る。8は半導体膜および絶縁膜で半導体膜とソース電極
、ドレイン電極が接続されておりゲート電極とは絶縁膜
8で絶縁されている。
FIG. 8 shows a planar configuration diagram of a conventional thin film transistor array. In FIG. 8, 1 is a scanning line connected to the gate electrode 7. A signal line 2 is connected to the source electrode 6, and the intersection with the scanning line is insulated by an insulating film 3. 5 is a drain electrode connected to the picture element electrode 4. Reference numeral 8 denotes a semiconductor film and an insulating film, and the semiconductor film is connected to a source electrode and a drain electrode, and is insulated from a gate electrode by the insulating film 8.

以上のように構成された薄膜トランジスタアレイに制御
信号と走査電圧が与えられた場合、個々の薄膜トランジ
スタのスイッチングが行なわれ絵素電極4に信号が入力
される。
When a control signal and a scanning voltage are applied to the thin film transistor array configured as described above, switching of each thin film transistor is performed and a signal is input to the picture element electrode 4.

発明が解決しようとする問題点 しかしながら上記のような構成では、薄膜トランジスタ
の欠陥やパネル化した時に生ずる対向電極との短絡(コ
モンショート)、あるいは走査線と信号線の交差部での
クロスショートなどにより表示画像に欠陥が生じた場合
にパネルとして不良となるが欠陥部のトランジスタある
いは欠陥部の走査線、信号線を切り離し走査線、信号線
を両側給電することにより修正が可能である。しかしな
がら走査線、信号線はパネルの大型化に伴ない低抵抗化
をはかる必要がありAntなどにより数千人の膜厚にな
っている。アレイ状態ではレーザ光線により数千人のA
lを切断することは可能であるが、パネル状態で切断可
能なレーザ出力を与えた場合、滞在する液晶、対向電極
等に悪影響を与え逆に対向電極とのシ曹−ト不良を起こ
すため修正は困難であるので歩留を低下させるという大
きな問題点を有していた。
Problems to be Solved by the Invention However, with the above configuration, problems may occur due to defects in the thin film transistors, short circuits with the opposing electrode (common short) that occur when the panel is assembled, or cross shorts at the intersections of scanning lines and signal lines. If a defect occurs in the displayed image, the panel will be defective, but it can be corrected by separating the transistor in the defective part or the scanning line or signal line in the defective part and supplying power to the scanning line or signal line on both sides. However, as the size of the panel increases, the scanning lines and signal lines need to be made lower in resistance, and the thickness of the scanning lines and signal lines has become several thousand people due to the use of Ant and the like. In an array state, thousands of A
It is possible to cut the l, but if a laser output that can cut the panel is applied, it will have a negative effect on the liquid crystal, counter electrode, etc. that stays, and will cause a sheet failure with the counter electrode, so it must be corrected. Since it is difficult, there is a major problem in that the yield is reduced.

本発明は上記問題点に鑑み、欠陥トランジスタおよび欠
陥部分を走査線および信号線から容易に切り離なせる構
造を有した薄膜トランジスタを提供するものである。
In view of the above problems, the present invention provides a thin film transistor having a structure in which a defective transistor and a defective portion can be easily separated from a scanning line and a signal line.

問題点を解決するための手段 上記問題点を解決するために本発明の薄膜トランジスタ
アレイは、1絵素に対して走査線と信号線に1箇所以上
のブリッジ部を設けたという構成を備えたものである。
Means for Solving the Problems In order to solve the above problems, the thin film transistor array of the present invention has a configuration in which a scanning line and a signal line are provided with one or more bridge portions for each pixel. It is.

作用 本発明は上記した構成によって薄膜トランジスタに欠陥
が生じた時や、パネル化後に対向電極との短絡不良など
が生じた場合に、レーザ光線により切断容品なブリッジ
部を切断して、走査線あるいは信号線より欠陥部分を分
離することにより、欠陥を無くするか軽減することがで
きることとなる。
Effects of the present invention With the above-described configuration, when a defect occurs in the thin film transistor, or when a short-circuit failure with the counter electrode occurs after forming a panel, the bridge portion that can be cut is cut with a laser beam, and the scanning line or By separating the defective portion from the signal line, defects can be eliminated or reduced.

実施例 以下本発明の一実施例の薄膜トランジスタアレイについ
て図面を参照しながら説明する。第1図は本発明の第1
の実施例における薄膜トランジスタアレイの平面構成図
を示すものである。第1図において9は信号線プリフジ
部で膜厚1000人のCrで構成されている。信号線ブ
リッジ部は走査線との交差部に設けられ信号線2を中継
している。10は走査線ブリッジ部で膜厚1000人の
Crで構成されており、走査wA1とゲート電極7の接
続部の両側2箇所に設けている。ゲート電極はCrで膜
厚1000人、走査線、信号線ドレイン電極5.ソース
電極6はAJで8000人の膜厚で構成されている。8
は半導体膜および絶縁膜、4は絵素電極。
EXAMPLE Hereinafter, a thin film transistor array according to an example of the present invention will be described with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
FIG. 3 shows a plan configuration diagram of a thin film transistor array in an example. In FIG. 1, reference numeral 9 denotes a signal line prefix portion, which is made of Cr having a thickness of 1000 mm. The signal line bridge section is provided at the intersection with the scanning line and relays the signal line 2. Reference numeral 10 denotes a scanning line bridge portion, which is made of Cr having a film thickness of 1,000 yen, and is provided at two locations on both sides of the connection portion between the scanning wA1 and the gate electrode 7. The gate electrode is made of Cr with a film thickness of 1000 mm, and the scanning line and signal line drain electrodes are 5. The source electrode 6 is made of AJ and has a thickness of 8000 mm. 8
4 is a semiconductor film and an insulating film, and 4 is a picture element electrode.

以上のように構成された薄膜トランジスタアレイについ
て、以下第1図〜第4図を用いてその欠陥修正方法につ
いて説明する。
A method for correcting defects in the thin film transistor array constructed as described above will be described below with reference to FIGS. 1 to 4.

まず第2図は第1図の斜視図、第3図はアレイをパネル
化したもので走査l1)1)の中央部から長手方向に切
断した断面図、第4図は薄膜トランジスタアレイの等価
回路図を示すものであって、第3図においてアレイをパ
ネル化した場合に対向電極とのギャップは10μm以下
と狭ギャップのため対向電極と各アレイの電極部との上
下ショートが生じた場合表示欠陥となる。又走査線と信
号線の交差部でのショートや、個々の薄膜トランジスタ
での電極間ショートが生じた場合も同様に表示欠陥とな
る。この欠陥を修正するには欠陥部分を走査線および信
号線から切り離すことにより実現できる。
First, Fig. 2 is a perspective view of Fig. 1, Fig. 3 is a cross-sectional view of the array as a panel, cut in the longitudinal direction from the center of scanning l1) 1), and Fig. 4 is an equivalent circuit diagram of the thin film transistor array. In Figure 3, when the array is made into a panel, the gap between the counter electrode and the counter electrode is as narrow as 10 μm or less, so if a vertical short occurs between the counter electrode and the electrode part of each array, it will be a display defect. Become. Furthermore, a short circuit at the intersection of the scanning line and the signal line or a short circuit between the electrodes of individual thin film transistors also results in a display defect. This defect can be corrected by separating the defective portion from the scanning line and signal line.

第3図および第4図は対向電極12と走査線1とで上下
ショート14が生じた欠陥例である。これを修正するに
はブリッジ部10aと10bをレーザ光線15によって
切断することによって欠陥部を独立させることができる
。この際、走査線の両側から入力電圧を印加することに
より欠陥のない表示画像が得られる。同様に交差部での
ショートや薄膜トランジスタの欠陥も、走査線と信号線
を欠陥モードに応じて切断箇所を選択して切断すること
により修正できる。なお、薄膜トランジスタ欠陥の修正
÷は、ライン欠陥あるいは絵素欠陥で常時点灯が絵素欠
陥の常時不点灯に軽減されるが無欠陥とはならない、た
だし、1絵素2トランジスタ構成にすることにより無欠
陥にすることができる。
FIGS. 3 and 4 show examples of defects in which a vertical short circuit 14 occurs between the counter electrode 12 and the scanning line 1. To correct this, the bridge portions 10a and 10b are cut by the laser beam 15, thereby making the defective portion independent. At this time, a display image free of defects can be obtained by applying input voltages from both sides of the scanning line. Similarly, short circuits at intersections and defects in thin film transistors can be corrected by selecting and cutting the scanning lines and signal lines according to the defect mode. Note that correction of thin film transistor defects ÷ means that constant lighting due to line defects or pixel defects is reduced to constant non-lighting due to pixel defects, but it does not mean that there are no defects. However, by making the configuration 1 pixel and 2 transistors, Can be defective.

以上のように本実施例によれば、l絵素に対して走査線
と信号線に1箇所以上のブリッジ部を設けることにより
、パネル化した状態でも容易に欠陥部を独立して走査線
および信号線より切り離すことができる。
As described above, according to this embodiment, by providing one or more bridge portions in the scanning line and the signal line for each pixel, defective portions can be easily isolated from the scanning line and the signal line even in a paneled state. Can be separated from the signal line.

以下本発明の第2の実施例の薄膜トランジスタアレイに
ついて図面を参照しながら説明する。
A thin film transistor array according to a second embodiment of the present invention will be described below with reference to the drawings.

第5図は本発明の第2の実施例を示す薄膜トランジスタ
アレイの部分平面構成図である。第6図は等価回路図で
ある。
FIG. 5 is a partial plan view of a thin film transistor array showing a second embodiment of the present invention. FIG. 6 is an equivalent circuit diagram.

同図において、1は走査線、2は信号線、3は絶縁膜、
4は絵素電極、5はドレイン電橋、6はソース電極、8
は半導体膜および絶縁膜、9は信号線ブリッジ部、10
は走査線ブリッジ部で、以上は第1図の構成と同様なも
のである。第1図の構成と異なるのはゲート電極7と走
査電極との接続部を2箇所有しその接続部の間にブリッ
ジ部を設けた点である。
In the figure, 1 is a scanning line, 2 is a signal line, 3 is an insulating film,
4 is a picture element electrode, 5 is a drain bridge, 6 is a source electrode, 8
9 is a semiconductor film and an insulating film, 9 is a signal line bridge portion, and 10 is a semiconductor film and an insulating film.
1 is a scanning line bridge section, and the above structure is similar to that shown in FIG. The difference from the configuration shown in FIG. 1 is that there are two connecting portions between the gate electrode 7 and the scanning electrode, and a bridge portion is provided between the connecting portions.

上記のように構成された薄膜トランジスタアレイについ
て以下その修正方法について説明する。
A method for modifying the thin film transistor array configured as described above will be described below.

第1図における第1の実施例では走査&1)とゲート電
極7との接続部の両側にブリッジ部があり、そのブリッ
ジ部間で対向電極とのショートが生じた欠陥部を切り離
した場合、ゲート電圧が印加できなくなり絵素欠陥とな
る。第2の実施例においては第5図B点で対向電極との
シe−トが発生した場合でも、ゲート電極とブリッジ部
A点を切断することにより両側給電でゲート電極に電圧
を印加することが可能となる。同様に0点で欠陥が発生
した時も切断箇所を選択することによりゲート電極に電
圧が印加できる状態で修正ができる。
In the first embodiment shown in FIG. 1, there are bridge parts on both sides of the connection part between scan &1) and the gate electrode 7, and when a defective part where a short circuit with the counter electrode occurs between the bridge parts is separated, the gate No voltage can be applied, resulting in a pixel defect. In the second embodiment, even if a sheet with the opposing electrode occurs at point B in FIG. 5, voltage can be applied to the gate electrode with power supply on both sides by disconnecting the gate electrode and point A of the bridge part. becomes possible. Similarly, even when a defect occurs at the 0 point, it can be corrected by selecting the cutting location while voltage can be applied to the gate electrode.

以上のようにゲート電極と走査線との接続部を2箇所設
けその接続部間に走査線ブリッジ部を設けることにより
、対向電極とのシ茸−ト箇所が走査線のどの部分で発生
しても、薄膜トランジスタの機能を損なわず修正できる
As described above, by providing two connection parts between the gate electrode and the scanning line and providing a scanning line bridge part between the connection parts, it is possible to determine at which part of the scanning line the seat with the counter electrode occurs. can also be modified without impairing the functionality of the thin film transistor.

以下本発明の第3め実施例の薄膜トランジスタアレイに
ついて図面を参照しなが゛ら説明する。
A thin film transistor array according to a third embodiment of the present invention will be described below with reference to the drawings.

第7図は本発明の第3の実施例を示すfil膜トランジ
スタアレイの部分平面構成図である。
FIG. 7 is a partial plane configuration diagram of a fil film transistor array showing a third embodiment of the present invention.

同図において、1は走査線、10はブリッジ部でゲート
電極あるいはソース電極と接続されている。
In the figure, 1 is a scanning line, and 10 is a bridge portion connected to a gate electrode or a source electrode.

上記のように構成された薄膜トランジスタアレイについ
てその動作を説明する。
The operation of the thin film transistor array configured as described above will be explained.

第2の実施例での修正方法と同様に欠陥箇所を切り離す
が、切断箇所Aをブリッジ部とゲート電極あるいはソー
ス電極との接続部の右左片側を選択することによって第
2の実施例と同じ効果が得られる。
The defective part is cut off in the same way as the repair method in the second embodiment, but the same effect as in the second embodiment can be obtained by selecting the cutting part A on the right or left side of the connection part between the bridge part and the gate electrode or source electrode. is obtained.

以上のように、走査線のブリッジ部とゲート電極あるい
はソース電極とが接続されており、接続部の両側のブリ
ッジ部に切断部分を設けたことによって切断箇所を少な
くして欠陥の修正ができる。
As described above, the bridge portion of the scanning line is connected to the gate electrode or the source electrode, and by providing cut portions in the bridge portions on both sides of the connection portion, defects can be repaired by reducing the number of cut portions.

発明の効果 以上のように本発明は薄膜トランジスタアレイのl絵素
に対して走査線と信号線に1箇所以上のブリッジ部を設
けることにより、ライン抵抗を高くすることなく薄膜ト
ランジスタの欠陥による画像表示不良の軽減や、クロス
ショート、対向電極シッートによる不良を無くすること
ができる。
Effects of the Invention As described above, the present invention provides one or more bridge portions in the scanning line and signal line for each pixel of a thin film transistor array, thereby eliminating image display failures caused by defects in thin film transistors without increasing line resistance. It is possible to reduce defects caused by cross shorts and opposing electrode sheets.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例における薄膜トランジス
タの平面構成図、第2図は第1図の斜視図、第3図は薄
膜トランジスタアレイをパネル化した後、走査線中央部
から長手方向に切断した断固、第8図は従来のIII)
ランジスタアレイの平面構成図である。 l・・・・・・走査線、2・・・・・・信号線、3・・
・・・・絶縁膜、4・・・・・・絵素電極、5・・・・
・・ドレイン電極、6・・・・・・ソース電極、7・・
・・・・ゲート電極、8・・・・・・半導体膜および絶
縁膜、9・・・・・・信号線ブリッジ部、10・・・・
・・走査線プリフジ部、1)・・・・・・基板、12・
・・・・・対向電極、13・・・・・・液晶。 代理人の氏名 弁理士 中尾敏男 はか1名f−−−之
itI!1( クー一−4に9紫に 第1図     3−虻株R笈 4−饋素實厭 5−−リドレ斗ソ貢ジ理版 6−、ノース ゲ 7−−−プ°−k17 δ−−4 *sbp ぴ* **y+xδ   7 第2図 13−シ娼 派                派転
FIG. 1 is a plan configuration diagram of a thin film transistor according to a first embodiment of the present invention, FIG. 2 is a perspective view of FIG. 1, and FIG. Determined disconnection, Figure 8 is the conventional III)
FIG. 2 is a plan configuration diagram of a transistor array. l...Scanning line, 2...Signal line, 3...
... Insulating film, 4 ... Picture element electrode, 5 ...
...Drain electrode, 6...Source electrode, 7...
... Gate electrode, 8 ... Semiconductor film and insulating film, 9 ... Signal line bridge portion, 10 ...
・・Scanning line pre-fuji part, 1)・・・・Substrate, 12・
...Counter electrode, 13...Liquid crystal. Name of agent: Patent attorney Toshio Nakao 1 (Ku 1 - 4 to 9 purple Fig. 1 3 - Horse stock R 笈 4 - 饋本實厭 5 - Ridley Doo Soo Kuji Rippan 6 - North Ge 7 - pu° - k17 δ - -4 *sbp pi* **y+xδ 7 Figure 2 13-Shi prostitute faction change

Claims (4)

【特許請求の範囲】[Claims] (1)アクティブマトリクス方式表示装置用薄膜トラン
ジスタアレイであって、1絵素に対して走査線と信号線
に1箇所以上のブリッジ部を設けたことを特徴とする薄
膜トランジスタアレイ。
(1) A thin film transistor array for an active matrix display device, characterized in that one or more bridge portions are provided in a scanning line and a signal line for one picture element.
(2)走査線あるいは信号線のブリッジ部をレーザ光線
によって切断できる出力が、走査線および信号線を切断
できる出力より小さいことを特徴とする特許請求の範囲
第(1)項記載の薄膜トランジスタアレイ。
(2) The thin film transistor array according to claim (1), wherein the output power that can cut the bridge portion of the scanning line or the signal line with the laser beam is smaller than the output power that can cut the scanning line or the signal line.
(3)走査線あるいは信号線と薄膜トランジスタのゲー
ト電極あるいはソース電極との接続部が1トランジスタ
に対して2箇所有し、前記2箇所の接続部の間に走査線
あるいは信号線のブリッジ部を設けたことを特徴とする
特許請求の範囲第(1)項または第(2)項記載の薄膜
トランジスタアレイ。
(3) Each transistor has two connection points between the scanning line or signal line and the gate electrode or source electrode of the thin film transistor, and a bridge portion of the scanning line or signal line is provided between the two connection points. The thin film transistor array according to claim (1) or (2), characterized in that:
(4)走査線あるいは信号線のブリッジ部と薄膜トラン
ジスタのゲート電極あるいはソース電極とが接続されて
おり、前記接続部のブリッジ部両側に、切断部分を設け
たことを特徴とする特許請求の範囲第(1)項または第
(2)項記載の薄膜トランジスタアレイ。
(4) A bridge portion of a scanning line or a signal line is connected to a gate electrode or a source electrode of a thin film transistor, and cutting portions are provided on both sides of the bridge portion of the connection portion. The thin film transistor array according to item (1) or item (2).
JP62074671A 1987-03-27 1987-03-27 Thin film transistor array Pending JPS63240527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62074671A JPS63240527A (en) 1987-03-27 1987-03-27 Thin film transistor array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62074671A JPS63240527A (en) 1987-03-27 1987-03-27 Thin film transistor array

Publications (1)

Publication Number Publication Date
JPS63240527A true JPS63240527A (en) 1988-10-06

Family

ID=13553926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62074671A Pending JPS63240527A (en) 1987-03-27 1987-03-27 Thin film transistor array

Country Status (1)

Country Link
JP (1) JPS63240527A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09265113A (en) * 1996-03-28 1997-10-07 Nec Corp Active matrix type liquid crystal display device and its production
JP2003177682A (en) * 2001-09-05 2003-06-27 Konica Corp Display panel and its manufacturing method
JP2011107260A (en) * 2009-11-13 2011-06-02 Seiko Epson Corp Substrate for semiconductor device and method for manufacturing the same, and semiconductor device and electronic equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09265113A (en) * 1996-03-28 1997-10-07 Nec Corp Active matrix type liquid crystal display device and its production
JP2003177682A (en) * 2001-09-05 2003-06-27 Konica Corp Display panel and its manufacturing method
JP2011107260A (en) * 2009-11-13 2011-06-02 Seiko Epson Corp Substrate for semiconductor device and method for manufacturing the same, and semiconductor device and electronic equipment

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