JPS63225229A - Thin-film transistor array - Google Patents

Thin-film transistor array

Info

Publication number
JPS63225229A
JPS63225229A JP62060603A JP6060387A JPS63225229A JP S63225229 A JPS63225229 A JP S63225229A JP 62060603 A JP62060603 A JP 62060603A JP 6060387 A JP6060387 A JP 6060387A JP S63225229 A JPS63225229 A JP S63225229A
Authority
JP
Japan
Prior art keywords
film transistor
thin film
thin
electrode
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62060603A
Other languages
Japanese (ja)
Inventor
Yoshitake Hayashi
祥剛 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62060603A priority Critical patent/JPS63225229A/en
Publication of JPS63225229A publication Critical patent/JPS63225229A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To reduce the man-hours required for the correcting operation in cutting off a thin-film transistor by arranging in parallel the connection between a scanning line and the gate electrode of each thin-film transistor and the connection between each picture element and the drain electrode of each thin-film transistor or the connection between a signal conductor and the source electrode of each thin-film transistor to separately and independently cut off each transistor. CONSTITUTION:The connection 9 between the scanning line 1 and the gate electrode 8 of the thin-film transistor connected to the line 1 and the connection 10 between each picture element electrode 3 and the drain electrode 7 of the thin-film transistor connected to the electrode 3 or the connection between the signal conductor and the source electrode of the thin-film transistor connected to the signal conductor are arranged in parallel, and the respective connections can be cut on a straight line. As a result, the correcting operation in cutting off the thin-film transistor can be carried out by one positioning and one laser irradiation in a certain straight-line range.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はアクティブマトリクス方式液晶表示装置に用い
られる薄膜トランジスタ(T P T)アレイに関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film transistor (TPT) array used in an active matrix liquid crystal display device.

従来の技術 近年、従来のCRTに代わる新しい表示装置の開発が盛
んに行なわれるようになってきた。その中でも液晶表示
装置はI膜で低電力動作が可能であるため、自動車3時
計、家電と市場での期待は大きいものがある。
2. Description of the Related Art In recent years, new display devices to replace conventional CRTs have been actively developed. Among them, liquid crystal display devices have high expectations in the market for automobiles, watches, and home appliances because they are capable of low-power operation using an I film.

従来、液晶表示装置は単純駆動方式で小型のものが多か
ったが、コントラストが悪く、高密度化。
Conventionally, liquid crystal display devices used a simple drive method and were often small, but the contrast was poor and the density was high.

大型化が難しいため、各絵素を独立で駆動させるアクテ
ィブマトリクス方式の表示装置が有望となってきている
。中でも薄膜トランジスタによる駆動方式の液晶表示装
置として高密度な1〜5インチサイズの小型テレビなど
市場が拡大されている。
Because it is difficult to increase the size, active matrix display devices, in which each picture element is driven independently, are becoming promising. Among them, the market for liquid crystal display devices driven by thin film transistors, such as high-density compact televisions of 1 to 5 inches in size, is expanding.

しかしながらアクティブマトリクス方式を深川した市販
品のポケット型液晶テレビにおいても、数点の絵素欠陥
が含まれているのが実情である。
However, the reality is that even commercially available pocket-type LCD TVs based on the active matrix system contain several pixel defects.

現在10〜20インチサイズのアクティブマトリクス方
式表示装置や、小型サイズを拡大投映する液晶ライトバ
ルブを利用した投写型テレビなど将来的に有望な商品の
研究開発が進んでいるが、拡大表示や、大面積化により
一層絵素数が多くなり、それにともない欠陥が増加し歩
留りを極端に低下させることとなる。この欠陥を救済す
る手段としてレーザなどによって欠陥トランジスタを切
断し、クロスショートによるライン欠陥を無くしたり、
常時点灯状態である絵素欠陥を常時非点灯状態にする技
術や特開昭61−121034号公報にあるように、1
絵素に対して2個以上の薄膜トランジスタを設けて欠陥
トランジスタ側を切断することによって欠陥を無くする
か、サブトランジスタによって隣接する絵素信号を印加
することにより、見掛は上問題のない表示画像が得られ
る技術などが知られている。
Currently, research and development is progressing on promising products such as 10- to 20-inch active matrix display devices and projection televisions that use liquid crystal light valves to enlarge and project small images. As the area increases, the number of picture elements increases, and the number of defects increases accordingly, resulting in an extremely low yield. As a means of remediating this defect, the defective transistor is cut using a laser or the like to eliminate line defects caused by cross shorts.
As described in Japanese Unexamined Patent Application Publication No. 121034/1986, there is a technique for turning a pixel defect that is always on into a non-lighting state.
By providing two or more thin film transistors for each pixel and cutting off the defective transistor side to eliminate the defect, or by applying adjacent pixel signals using sub-transistors, it is possible to create a display image that appears to have no problems. Techniques for obtaining this are known.

以下図面を参照しながら、上述した従来の薄膜トランジ
スタアレイの一例について説明する。
An example of the conventional thin film transistor array mentioned above will be described below with reference to the drawings.

第3図(alは薄膜トランジスタアレイの等価回路、第
3図(blは一絵素に対して2個の薄膜トランジスタで
構成したアレイの等価回路、第4図は従来の薄膜トラン
ジスタアレイの平面構成図、第5図は断面図を示すもの
である。第4図、第5図において、8はゲート電極で走
査線1に接続されている。
Figure 3 (al is an equivalent circuit of a thin film transistor array, Figure 3 (bl is an equivalent circuit of an array composed of two thin film transistors per pixel, Figure 4 is a plan view of a conventional thin film transistor array, Figure 5 shows a cross-sectional view.In Figures 4 and 5, 8 is a gate electrode connected to the scanning line 1.

6はソース電極で信号、%II8および半導体膜4aに
接続されている。7はドレイン電極で、半導体膜4aお
よび接続部9の対向側で絵素電極3に接続されている。
6 is a source electrode connected to the signal, %II8 and the semiconductor film 4a. A drain electrode 7 is connected to the picture element electrode 3 on the opposite side of the semiconductor film 4a and the connection portion 9.

以上のように構成された薄膜トランジスタアレイについ
て以下欠陥モードについて説明する。
The defect modes of the thin film transistor array configured as described above will be described below.

絶縁膜4bにピンホールが生じた場合、ゲート電極とソ
ース電極あるいはゲート電極とドレイン電極との短絡が
生じたり、マスク欠陥やエツチング不良による膜残りが
生じソース電極とドレイン電極の短絡が生じ薄膜トラン
ジスタの欠陥となる。
If a pinhole occurs in the insulating film 4b, a short circuit may occur between the gate electrode and the source electrode or between the gate electrode and the drain electrode, or a film may remain due to mask defects or poor etching, resulting in a short circuit between the source electrode and the drain electrode, resulting in damage to the thin film transistor. It becomes a defect.

発明が解決しようとする問題点 しかしながら上記のような構成では、薄膜トランジスタ
の大面積化あるいは絵素の小型化に伴い、欠陥トランジ
スタの切断に際してより高精度の位置制御技術が必要な
うえ、各欠陥トランジスタ単位で2箇所の切断を行うた
め1箇所切断後、(第4図におけるA−A)アレイまた
はレーザ照射口を移動させ2箇所目の切断箇所(第4図
におけるB−B)に位置合わせするので時間が多くかか
るという問題点を有していた。
Problems to be Solved by the Invention However, with the above configuration, as the area of thin film transistors increases or picture elements become smaller, more precise position control technology is required when cutting defective transistors, and Since cutting is performed at two locations per unit, after cutting one location, move the array or laser irradiation port (A-A in Figure 4) and align it with the second cutting location (B-B in Figure 4). Therefore, there was a problem that it took a lot of time.

本発明は上記問題点に鑑み、欠陥の薄膜トランジスタを
1切断単位で(1回の位置め、1回の切断)で切り離し
修正できる薄膜トランジスタアレイを提供するものであ
る。
In view of the above-mentioned problems, the present invention provides a thin film transistor array in which defective thin film transistors can be separated and corrected in one cutting unit (one position, one cut).

問題点を解決するための手段 上記問題点を解決するために本発明の薄膜トランジスタ
アレイは、走査線とこれに接続された薄膜トランジスタ
のゲート電極との接続部と、各絵素電極とこれに接続さ
れた薄膜トランジスタのドレイン電極との接続部あるい
は、信号線とこれに接続された薄膜トランジスタのソー
ス電極との接続部とが並列に配置され、それぞれの接続
部を一直線上に切断できるという構成を備えたものであ
る。
Means for Solving the Problems In order to solve the above problems, the thin film transistor array of the present invention has a connecting part between the scanning line and the gate electrode of the thin film transistor connected thereto, and a connection part between each pixel electrode and the gate electrode of the thin film transistor connected thereto. A device having a configuration in which the connecting portion with the drain electrode of a thin film transistor or the connecting portion between a signal line and the source electrode of the thin film transistor connected thereto is arranged in parallel, and each connecting portion can be cut in a straight line. It is.

作用 本発明は上記した構成によってゲート電極とドレイン電
極あるいはゲート電極とソース電極とを一直線上に切断
できるため、1切断単位で欠陥修正ができることとなる
Operation The present invention allows the gate electrode and the drain electrode or the gate electrode and the source electrode to be cut in a straight line with the above-described configuration, so that defects can be repaired in units of one cut.

実施例 以下本発明の一実施例の薄膜トランジスタアレイについ
て図面を参照しながら説明する。
EXAMPLE Hereinafter, a thin film transistor array according to an example of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例における薄膜トランジスタア
レイの等価回路、第2図は平面構成図を示すものである
。第2図において9は走査線1とゲート電極8との接続
部、10は絵素電極3とドレイン電極7との接続部で接
続部9と接続部10は並列に配置されている。
FIG. 1 shows an equivalent circuit of a thin film transistor array according to an embodiment of the present invention, and FIG. 2 shows a planar configuration diagram. In FIG. 2, 9 is a connection between the scanning line 1 and the gate electrode 8, 10 is a connection between the picture element electrode 3 and the drain electrode 7, and the connection 9 and the connection 10 are arranged in parallel.

以上のように構成された薄膜トランジスタアレイについ
て欠陥モードと修正方法について説明する。
Defect modes and correction methods for the thin film transistor array configured as described above will be explained.

薄膜トランジスタの絶縁膜4bにピンホールが発生しゲ
ート電極とソース電極との眉間短絡が生じた場合薄膜ト
ランジスタを介して走査線と信号線が短絡しそのライン
上のトランジスタが正常動作せず線欠陥が生じる。同様
にゲート電極とドレイン電極との眉間短絡が生じた場合
は常時点灯状態になる。この欠陥を修正するため接続部
9゜10をYAGレーザにより一直線上に切断(第2図
中A−A)L、走査線1および信号線2より欠陥トラン
ジスタを切り離すことにより無欠陥化あるいは欠陥の軽
減ができる。
If a pinhole occurs in the insulating film 4b of the thin film transistor and a short circuit occurs between the gate electrode and the source electrode, the scanning line and the signal line are shorted through the thin film transistor, and the transistor on that line does not operate normally, resulting in a line defect. . Similarly, if a short circuit occurs between the gate electrode and the drain electrode, the lamp will be in a constantly lit state. To correct this defect, the connecting portion 9°10 is cut in a straight line with a YAG laser (A-A in Figure 2), and the defective transistor is separated from the scanning line 1 and signal line 2, thereby eliminating the defect or eliminating the defect. It can be reduced.

以上のように本実施例によれば、走査線とこれに接続さ
れた薄膜トランジスタのゲート電極との接続部と、絵素
電極とこれに接続された薄膜トランジスタのドレインを
掻との接続部とを並列に配置することにより、薄膜トラ
ンジスタを切り離す修正作業が1回の位置決めとある直
線範囲における1回のレーザ照射によって行なえること
ができる。
As described above, according to this embodiment, the connection between the scanning line and the gate electrode of the thin film transistor connected thereto is parallel to the connection between the pixel electrode and the drain of the thin film transistor connected thereto. By arranging the thin film transistor in a straight line, the modification work of separating the thin film transistor can be performed by one positioning and one laser irradiation in a certain linear range.

なお、本実施例において薄膜トランジスタの切断箇所を
ゲート電極接続部9とドレイン電極接続部10としたが
ドレイン電極10の替わりにソース電極に枝配線を設け
、ゲート電極と並列配置させ切断するように構成しても
よい。
In this embodiment, the thin film transistor is cut at the gate electrode connection part 9 and the drain electrode connection part 10, but instead of the drain electrode 10, a branch wiring is provided at the source electrode, and the branch wiring is placed in parallel with the gate electrode and cut. You may.

また、第3図(blに示すような1絵素2トランジスタ
構成であれば、ゲート電極とドレイン電極間の眉間短絡
および、ソース電極とドレイン電極間の隣接短絡も含め
て完全に無欠陥化が可能となる。
In addition, in the case of a one-pixel two-transistor configuration as shown in Figure 3 (bl), it is completely defect-free, including short-circuits between the eyebrows between the gate electrode and drain electrodes, and adjacent short-circuits between the source and drain electrodes. It becomes possible.

また、本実施例において薄膜トランジスタの切断方法を
YAGレーザとしたが、その他の方法でもかまわない。
Further, in this embodiment, the thin film transistor is cut using a YAG laser, but other methods may be used.

発明の効果 以上のように本発明は、薄膜トランジスタアレイにおい
て走査線とこれに接続されたyl薄膜トランジスタゲー
ト電極との接続部と、各絵素とこれに接続された薄膜ト
ランジスタのドレイン電極との接続部あるいは、信号線
とこれに接続された薄膜トランジスタのソース電極とが
並列に配!されていることにより、薄膜トランジスタを
切り離す修正作業が1回の位置決めとある直線範囲にお
ける1回のレーザ照射によって行なえるため大幅に修正
に要する工数を低減することができる。
Effects of the Invention As described above, the present invention provides a connection portion between a scanning line and the yl thin film transistor gate electrode connected thereto in a thin film transistor array, a connection portion between each picture element and the drain electrode of the thin film transistor connected thereto, or , the signal line and the source electrode of the thin film transistor connected to it are arranged in parallel! By doing so, the correction work to separate the thin film transistor can be performed by one positioning and one laser irradiation in a certain linear range, so that the number of man-hours required for the correction can be significantly reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における薄膜トランジスタア
レイの等価回路図、第2図は第1図の平面構成図、第3
図(alは従来の概念における薄膜トランジスタの等価
回路図、第3図(blは一絵素に対して2個の薄膜トラ
ンジスタで構成したアレイの等価回路図、第4図は第3
図(alの平面構成図、第5図は従来の薄膜トランジス
タプレイの断面図である。 1・・・・・・走査線、2・・・・・・信号線、3・・
・・・・絵素電極、4a・・・・・・半導体膜、4b、
5・・・・・・絶縁膜、6・・・・・・ソース電極、7
・・・・・・ドレイン電極、8・・・・・・ゲート電極
、9,10・・・・・・接続部、11・・・・・・液晶
、12・・・・・・対向電極。 代理人の氏名 弁理士 中尾敏男 ほか1名第1図 +−1tL%(x+  xtノ 2−1s号’jlff+γ!ノ
FIG. 1 is an equivalent circuit diagram of a thin film transistor array according to an embodiment of the present invention, FIG. 2 is a plan configuration diagram of FIG. 1, and FIG.
(al is an equivalent circuit diagram of a thin film transistor according to the conventional concept, Figure 3 is an equivalent circuit diagram of an array composed of two thin film transistors for one pixel, and Figure 4 is an equivalent circuit diagram of an array composed of two thin film transistors for one picture element.
FIG. 5 is a cross-sectional view of a conventional thin film transistor play. 1...Scanning line, 2...Signal line, 3...
...Picture element electrode, 4a...Semiconductor film, 4b,
5... Insulating film, 6... Source electrode, 7
......Drain electrode, 8...Gate electrode, 9, 10...Connection portion, 11...Liquid crystal, 12...Counter electrode. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1+-1tL% (x+xtノ2-1s'jlff+γ!ノ

Claims (1)

【特許請求の範囲】[Claims] アクティブマトリクス方式表示装置用薄膜トランジスタ
アレイにおいて、走査線とこれに接続された各薄膜トラ
ンジスタのゲート電極との接続部と、各絵素とこれに接
続された各薄膜トランジスタのドレイン電極との接続部
あるいは、信号線とこれに接続された各薄膜トランジス
タのソース電極との接続部とが並列に配置され、かつ前
記2箇所の接続部を一直線上に熱的、化学的、電気的あ
るいは機械的手段によって、各トランジスタ個々に独立
で切断できるように構成したことを特徴とする薄膜トラ
ンジスタアレイ。
In a thin film transistor array for an active matrix display device, the connection part between a scanning line and the gate electrode of each thin film transistor connected thereto, the connection part between each picture element and the drain electrode of each thin film transistor connected to it, or the signal The line and the connection part between the source electrode of each thin film transistor connected thereto are arranged in parallel, and each transistor is connected to the line by thermal, chemical, electrical or mechanical means. A thin film transistor array characterized by being configured so that each individual can be cut independently.
JP62060603A 1987-03-16 1987-03-16 Thin-film transistor array Pending JPS63225229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62060603A JPS63225229A (en) 1987-03-16 1987-03-16 Thin-film transistor array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62060603A JPS63225229A (en) 1987-03-16 1987-03-16 Thin-film transistor array

Publications (1)

Publication Number Publication Date
JPS63225229A true JPS63225229A (en) 1988-09-20

Family

ID=13146990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62060603A Pending JPS63225229A (en) 1987-03-16 1987-03-16 Thin-film transistor array

Country Status (1)

Country Link
JP (1) JPS63225229A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298333U (en) * 1989-01-23 1990-08-06
JPH0416929A (en) * 1990-05-11 1992-01-21 Sharp Corp Active matrix type display device
JPH0437823A (en) * 1990-06-04 1992-02-07 Sharp Corp Active matrix type display device
JPH0445426A (en) * 1990-06-12 1992-02-14 Nec Corp Thin-film transistor and production thereof
JPH0445425A (en) * 1990-06-12 1992-02-14 Nec Corp Production of liquid crystal panel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677887A (en) * 1979-11-30 1981-06-26 Citizen Watch Co Ltd Liquid crystal display unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677887A (en) * 1979-11-30 1981-06-26 Citizen Watch Co Ltd Liquid crystal display unit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298333U (en) * 1989-01-23 1990-08-06
JPH0416929A (en) * 1990-05-11 1992-01-21 Sharp Corp Active matrix type display device
JPH0437823A (en) * 1990-06-04 1992-02-07 Sharp Corp Active matrix type display device
JPH0445426A (en) * 1990-06-12 1992-02-14 Nec Corp Thin-film transistor and production thereof
JPH0445425A (en) * 1990-06-12 1992-02-14 Nec Corp Production of liquid crystal panel

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