JPS63240128A - 論理回路 - Google Patents
論理回路Info
- Publication number
- JPS63240128A JPS63240128A JP62071874A JP7187487A JPS63240128A JP S63240128 A JPS63240128 A JP S63240128A JP 62071874 A JP62071874 A JP 62071874A JP 7187487 A JP7187487 A JP 7187487A JP S63240128 A JPS63240128 A JP S63240128A
- Authority
- JP
- Japan
- Prior art keywords
- output
- potential
- signal
- section
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
- H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/088—Transistor-transistor logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62071874A JPS63240128A (ja) | 1987-03-27 | 1987-03-27 | 論理回路 |
| US07/173,668 US4877975A (en) | 1987-03-27 | 1988-03-25 | Logic circuit having an output signal with a gentle leading edge |
| KR1019880003320A KR910001383B1 (ko) | 1987-03-27 | 1988-03-26 | 논리회로 |
| EP88104986A EP0285068A3 (en) | 1987-03-27 | 1988-03-28 | Logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62071874A JPS63240128A (ja) | 1987-03-27 | 1987-03-27 | 論理回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63240128A true JPS63240128A (ja) | 1988-10-05 |
| JPH0519328B2 JPH0519328B2 (cg-RX-API-DMAC7.html) | 1993-03-16 |
Family
ID=13473097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62071874A Granted JPS63240128A (ja) | 1987-03-27 | 1987-03-27 | 論理回路 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4877975A (cg-RX-API-DMAC7.html) |
| EP (1) | EP0285068A3 (cg-RX-API-DMAC7.html) |
| JP (1) | JPS63240128A (cg-RX-API-DMAC7.html) |
| KR (1) | KR910001383B1 (cg-RX-API-DMAC7.html) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000101370A (ja) * | 1998-09-24 | 2000-04-07 | Nec Shizuoka Ltd | トランジスタ回路 |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2635805B2 (ja) * | 1990-07-31 | 1997-07-30 | 株式会社東芝 | 低ノイズ型出力バッファ回路 |
| US5218243A (en) * | 1991-11-20 | 1993-06-08 | National Semiconductor Corporation | Bicmos ttl output buffer circuit with reduced power dissipation |
| JP3142018B2 (ja) * | 1992-03-12 | 2001-03-07 | 日本テキサス・インスツルメンツ株式会社 | 負荷駆動回路 |
| US5343092A (en) * | 1992-04-27 | 1994-08-30 | International Business Machines Corporation | Self-biased feedback-controlled active pull-down signal switching |
| US9018986B2 (en) * | 2013-01-21 | 2015-04-28 | Via Technologies, Inc. | Output buffers |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5720027A (en) * | 1980-06-25 | 1982-02-02 | Nec Corp | Logical gate circuit |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4409498A (en) * | 1980-12-30 | 1983-10-11 | International Business Machines Corporation | Transient controlled current switch |
| US4605870A (en) * | 1983-03-25 | 1986-08-12 | Ibm Corporation | High speed low power current controlled gate circuit |
| US4567378A (en) * | 1984-06-13 | 1986-01-28 | International Business Machines Corporation | Driver circuit for controlling signal rise and fall in field effect transistor processors |
| US4737665A (en) * | 1985-01-15 | 1988-04-12 | Texas Instruments Incorporated | Adjustable speed up circuit for TTL-type gates |
| JPH0720060B2 (ja) * | 1985-08-14 | 1995-03-06 | 株式会社東芝 | 出力回路装置 |
| US4622482A (en) * | 1985-08-30 | 1986-11-11 | Motorola, Inc. | Slew rate limited driver circuit which minimizes crossover distortion |
| US4746817A (en) * | 1987-03-16 | 1988-05-24 | International Business Machines Corporation | BIFET logic circuit |
-
1987
- 1987-03-27 JP JP62071874A patent/JPS63240128A/ja active Granted
-
1988
- 1988-03-25 US US07/173,668 patent/US4877975A/en not_active Expired - Lifetime
- 1988-03-26 KR KR1019880003320A patent/KR910001383B1/ko not_active Expired
- 1988-03-28 EP EP88104986A patent/EP0285068A3/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5720027A (en) * | 1980-06-25 | 1982-02-02 | Nec Corp | Logical gate circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000101370A (ja) * | 1998-09-24 | 2000-04-07 | Nec Shizuoka Ltd | トランジスタ回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0285068A3 (en) | 1990-06-13 |
| US4877975A (en) | 1989-10-31 |
| KR910001383B1 (ko) | 1991-03-04 |
| KR880012011A (ko) | 1988-10-31 |
| JPH0519328B2 (cg-RX-API-DMAC7.html) | 1993-03-16 |
| EP0285068A2 (en) | 1988-10-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080316 Year of fee payment: 15 |