JPS63236135A - Timer interruption system - Google Patents

Abstract

PURPOSE:To secure a time point even in case a CPU does not always given an answer to a timer interruption by adding a readable timer interruption counter which counts the timer start frequency to a timer circuit. CONSTITUTION:The value of a timer interruption counter 8 which is read out by a counter reading means 9 is usually set at 1 each time as long as a timer interruption is requested to a central processing unit CPU3' and a timer interruption process is always started by a timer interruption signal produced by a timer interruption signal production means 7. If the preceding timer interruption is not accepted by the CPU3', the value of the counter 8 read out by the means 9 is equal to 2 since the counter 8 is counting the timer interruption signals as long as the current timer interruption is accepted and a timer interruption process is started. Then the value 2 of the counter 8 is added to the time point information stored in a memory 4 by a time point count means 11 for counting time points.

Description

DETAILED DESCRIPTION OF THE INVENTION Overview A timer interrupt method in a processor system including a CPU, memory, I10 interface, etc., characterized in that a timer circuit is provided with a readable timer interrupt counter for counting the number of times the timer is activated. As a result, even if the CPU does not necessarily respond to timer interrupts,
Time can be guaranteed.

INDUSTRIAL APPLICATION FIELD The present invention relates to a timer interrupt method for a processor system including a CPU, memory, I10 interface, etc.

Processor systems such as microcomputers are widely applied from home appliances such as microwave ovens to industrial products such as industrial robots. Control of communication devices, 0Δ equipment, etc. is efficiently achieved by this processor system,
Efforts are being made to improve the functionality and miniaturize the device. These processor systems generally employ a timer interrupt method using a timer circuit, and also use the timer circuit to perform time counting.

2. Description of the Related Art In the conventional timer interrupt system, a timer interrupt signal generated at fixed time intervals is input to the CPU and flip-flop circuit of a processor, and time is counted based on the number of interrupt activations of the processor. This is shown in FIG. A clock a generated by an oscillator 1 is divided into an appropriate frequency by a frequency divider 2 to form a timer interrupt signal having an interval of, for example, one second.

The timer interrupt signal from the frequency divider 2 is input to the CPU 3 for timer interrupt, and is also input to the flip-flop 5. When the CPU 3 starts the timer interrupt routine, it sends a read signal C to the data bus driver 6, reads the content d of the flip-flop 5 by the data bus driver 6, and then clears the flip-flop 5 under the control of the CP LJ 3. The contents e of the flip-flop 5 read out by the data bus driver 6 are added to the time information on the memory 4 to perform time counting.

In the hydraulic type, the processor had to always respond to timer interrupts that occurred at regular intervals. The reason for this is that if the processor does not always respond to a timer interrupt, there will be a drop in time counting, resulting in a time lag.

Problems to be Solved by the Invention However, in the above-described conventional timer interrupt method, if an interrupt is not accepted due to processor processing, the interrupt is not activated and exits once. This is because the timer circuit uses the flip-flop 5, and if the interrupt is not activated, the contents of the flip-flop 5 will not be read out, even if the next timer interrupt signal is input to the flip-flop 5. This is because the output of flip-flop 5 is still 1. As described above, the conventional timer interrupt method has the disadvantage that, for example, if the interrupt is exited once without being activated, a time lag occurs.

The case where the interrupt is not accepted here means (a)
If the processing of another interrupt handling routine takes a long time, (b)
This applies to cases where interrupts are programmed to be disabled only during a certain period of time for processing reasons.

The present invention has been made in view of these points, and its purpose is to provide a timer interrupt method that can guarantee time even if the processor does not always respond to timer interrupts. be.

Means for Solving the Problems Figure 1 shows a block diagram of the principle of the present invention.
a timer interrupt counter 8 that is incremented by one by a timer interrupt signal generated at regular intervals; and a counter read means 9 that causes the central processing unit 3' to read the value of the timer interrupt counter 8 when accepting a timer interrupt.
Time counting means 1 which adds the read value of the timer interrupt counter 8 to the time information stored in the memory 4 and counts the time by t.
1, and a counter clearing means 10 for reading the value of the timer interrupt counter 8 by the counter reading means 10 and then clearing the value of the timer interrupt counter 8.

The counter read means 9, the counter clear means 10, and the time counting means 11 are derived from the functions of the central processing unit 3' which are programmed in advance.

Normally, the timer interrupt is generated by the timer interrupt signal generated by the timer interrupt signal generating means 7, and the timer interrupt is generated by the central processing unit 3.
If the timer interrupt processing is always started as requested by ', the value of the timer interrupt counter 8 read by the counter read means 9 will be 1 every time. If the previous timer interrupt was not accepted by the central processing unit 3', the timer interrupt counter 8 is counting the timer interrupt signals, so if the current timer interrupt is accepted and timer interrupt processing is started, the counter Lead means 9
The value of the timer interrupt counter 8 read out is 2, and this value is added to the time information on the memory 4 by the time counting means 11 to perform time counting.

That is, according to the timer interrupt method of the present invention, the timer interrupt counter 8 guarantees time information that is missed because the timer interrupt is not activated.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail based on embodiments shown in the drawings.

FIG. 2 shows a block diagram of an embodiment of the present invention, which is characterized in that a timer interrupt counter 8 is provided in place of the flip-flop 5 of the conventional example shown in FIG. Second
In the illustrated embodiment, the counter read means 9, counter clear means 10, and time counting means 11 shown in the principle diagram of FIG. Please note that.

The clock a oscillated by the oscillator 1 is divided into an appropriate frequency by the frequency divider 2S2 to form a timer interrupt signal every second, for example. Timer interrupt signal CPU3
, and at the same time as requesting an interrupt to the CPU 47, it is also input to the timer interrupt counter 8, and the timer interrupt counter 8 is incremented by one from 0 to 1. When the CPU 3 performs timer interrupt processing, the timer interrupt counter 8 is set by the data bus driver 6.
The value f of the counter is read out, and the value of this counter is added to the time information on the memory 4 managed by the CPU 3 to perform time counting.

On the other hand, if the CPU 3 does not perform timer interrupt processing, the timer interrupt counter 8 is further incremented by one to 2 when the next timer interrupt signal is generated. If the timer interrupt routine is activated at this time, the CP
tJ3 is the counter read signal C to the data bus driver 6.
and read the value 2 of timer interrupt counter 8,
This 2 is added to the time information on the memory 4 to perform time counting.

Even if the timer interrupt routine is not activated by CPLJ3, the number of timer interrupt signals is counted by the timer interrupt counter 8, so the next time the timer interrupt processing is activated, the timer interrupt counter 8 will be counted. The contents can be read out and added to the time information in the memory 4 to perform correct time counting.

Needless to say, it is assumed that the CPU 3 is programmed to read the contents of the timer interrupt counter 8 in each timer interrupt routine, and then clear the timer interrupt counter 8.

Next, the operation of the above-described embodiment will be explained with reference to the flowchart shown in FIG.

First, in step 101, the timer interrupt counter 8 is cleared as an initial setting, and in step 102, it is determined whether or not a timer interrupt has occurred. When a timer interrupt occurs, the timer interrupt counter 8 is incremented by one, and a timer interrupt signal is transmitted to CPtJ3 in step 104. Then step 1
05, it is determined whether or not an interrupt has been processed within the timer period. If the interrupt has been processed, the process proceeds to step 106, where the value of the timer interrupt counter 8 is read, and in step 107, the read counter value and the memory 4 are stored. The timer interrupt counter 8 is cleared in step 108.

On the other hand, if the interrupt processing is not activated within the timer cycle in step 105, the value of the timer interrupt counter 8 is roughly incremented by one to 2 in step 103. In this way, if the timer interrupt routine is not activated within the timer period, the value of the timer interrupt counter 8 increases by 1 each time a timer interrupt signal is generated, and the next time the timer interrupt routine is activated, The value of the timer interrupt counter 8 is read out (step 106), and the read counter value and internal time information are added in step 107.

Effects of the Invention Since the present invention is configured as described in detail above, the number of timer interrupts can be counted by the timer interrupt counter and this counted value can be added to the internal R clock information. This has the effect that the time can be guaranteed even if the terminal does not necessarily respond.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a flowchart showing the operation of the embodiment of the present invention, and Fig. 4 is the configuration of a conventional timer interrupt method. FIG. 1... Oscillator, 2... Frequency divider, 3...
CPU, 4...Memory, 5...Flip-flop, 6...Data bus driver, 7...Timer interrupt signal generation means, 8...Timer interrupt counter, 9...Counter read means, 10 ... Counter clearing means, 11... Time counting means. This crab moon principle diagram Fig. 1 I - Kyu ε Ooki Ita 1 J Fig. 2 Flow of father and hand row + dart Conventional example Fig. 4

Claims (1)

[Claims] At least a central processing unit (3'), a memory (4),
A processor system comprising a timer interrupt signal generating means (7) that generates a timer interrupt signal at regular time intervals, a timer interrupt counter (8) that is incremented by 1 by the timer interrupt signal, and the central processing unit (3'). ) reads the value of the timer interrupt counter (8) when the timer interrupt counter (8) is received by the timer interrupt counter;
4) A time counting means (11) that performs time counting by adding to the above time information, and a timer interrupt counter value read out by the counter reading means (9) and then reading the timer interrupt counter value (
8) A timer interrupt method characterized by comprising a counter clearing means (10) for clearing the counter clearing means (10).