JPS632353B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a time interval measuring method, and more particularly to a method for measuring pulse time intervals of a pulse signal to be measured using a microprocessor.

(Prior art) Figure 3 is a block diagram showing the conventional technology.
It measures time intervals with a resolution higher than the number of parallel processing bits of the microprocessor 4. In FIG. 3, two counters 30 and 31 are provided. The clock pulse 4a of the microprocessor 4 is connected to the clock input terminals 30c, 31c of the counters 30, 31, so that each counter constantly counts up or down the clock pulse 4a. Since the overflow output terminal 30b of the counter 30 is connected to the carry input terminal 31b of the counter 31, the count value 31a of the counter 31 represents the upper part of the overall count value, and the count value 30a of the counter 30 represents the lower part. Become. Count values 30a and 31a are normally separated from data bus 9 by gates 70 and 71, respectively. The address signal 4c from the microprocessor 4 and the signal 4d indicating that the address is valid are input to the address decoder 12, and when the address indicating the selection of each gate is output from the microprocessor 4, the address decoder 12 A gate signal 12a or 12b is supplied from the gate to the corresponding gate, and only then the gate is opened and the corresponding count value is led to the data bus 9.

Next, the operation will be explained. The microprocessor 4 first monitors the level of the pulse train 1 to be measured at the 1-bit input terminal 4b. Now, when the rise of the start pulse 1a is confirmed, the microprocessor 4 outputs an address signal 4c indicating selection of the gate 70, and the address decoder 12 decodes this address signal 4c to generate a gate signal 12a. This gate signal 12a is applied to the gate enable input terminal 70a of the gate 70, and the gate 70
0 opens and the microprocessor 4 starts the counter 30.
The count value 30a is read out through the data bus 9 and stored in the RAM 11 as data 11a.
Next, the microprocessor 4 outputs an address signal 4c indicating selection of the gate 71, and the address decoder 12 generates a gate signal 12b. The gate signal 12b is applied to the gate enable input terminal 71a to open the gate 71, and the microprocessor 4 reads out the count value 31a and stores it in the RAM 11 as data 11b. Thereafter, the microprocessor 4 monitors the 1-bit input terminal 4b, and when it recognizes the rising edge of the end pulse 1b, it moves to a program that reads the count value again, and opens the gates 70 and 71 in sequence in the same way as described above to read the lower count value. Read out 30a' and upper count value 31a',
The lower count value 30a' to RAM11 is data 1
1c, the upper count value 31a' is data 1.
Store as 1d.

The desired pulse time interval is determined by the microprocessor 4.
For example, it is calculated according to the calculation formula shown in FIG. That is, the microprocessor 4 converts the data 11a representing the lower count value 30a read in response to the rise of the start pulse 1a to the time difference T1 required to read the next higher count value 31a (normal microprocessor The instruction execution time is constant, so the time difference
T1 is constant) is added to obtain data 11a',
Furthermore, for the same reason, a time difference T2 is added to the data 11c representing the lower count value 31a read in response to the rising edge of the end pulse 1b, resulting in data 11c', and at the rising edge of the end pulse 1b composed of data 11d and 11c'. Data from time 11
By subtracting the rising time of the start pulse 1a consisting of 11b and 11a', data 11f and 11e representing the pulse time interval are obtained and stored in the RAM 11.
Thereafter, the microprocessor 4 performs processing using the data 11f and 11e as pulse time intervals.
Note that after reading the lower count value 30a or 30a', the lower counter 30 receives a carry signal (when counting up) or a borrow signal (when counting down) before the microprocessor 4 reads the respective upper count value 31a or 31a'. ) may occur, but this can be corrected by a program, for example, by examining the lower count value at the time of reading. Further, although there are only two counters in FIG. 3, it is possible to further increase the number of counters if necessary.

In this way, time intervals can be measured with a resolution higher than the number of parallel processing bits (for example, 8 bits) of the microprocessor 4, but there is a drawback that only one system of time intervals can be measured.

(Problems to be Solved by the Invention) An object of the present invention is to provide a method that can efficiently measure the interval between two types of pulses using the same counter.

(Means for solving the problem) A count value of a free-running counter means that constantly counts clock pulses of a constant frequency at the measurement start time and measurement end time synchronized with the first pulse train input to the microprocessor. are output to the data bus of the microprocessor via gate means, and the first and second free run counters are output by the microprocessor to the data bus at the measurement start time and end time, respectively. In the time interval measuring method, the time interval of the first pulse train is measured by determining a difference between second count values, wherein the gate means has a gate circuit with a latch, and the first pulse train When the microprocessor outputs an instruction signal indicating that no input is being input to the microprocessor, a second pulse is input to the latch gate circuit to determine the current third count value of the free run counter. is output to the data bus, and when the second pulse train is no longer input to the latch gate circuit, the current fourth count value of the free run counter is temporarily stored in the latch gate circuit, and the second pulse train is no longer input to the latch gate circuit. The third and fourth
The time interval of the second pulse train is also measured by determining the difference between the count values shown in the figure.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention, in which a set of counters is used to measure the time interval of two systems. Compared to the prior art shown in FIG. 3, the configuration shown in FIG. 1 is different from the prior art shown in FIG.
0 and 81 are used, and the second measured pulse train 17 generated from the pulse generation circuit 100 is connected to the latch strobe input terminals 80b and 81b of the gate with a latch. Gate with latch 80, 81
is the gate 70 in FIG. 3 while the input signals to the latch strobe input terminals 80b and 81b are at high level.
Exactly the same operation as 71 is performed. Note that the terminal 80a,
81a corresponds to the gate valid input terminals 70a and 71a of the gates 70 and 71. When the input signal to the latch strobe input terminals 80b, 81b changes from high level to low level, in response to the fall of this label, the latch gates 80, 81 change the count value 30a of the counters 30, 31 at that time, 31
Latch a. While the latch strobe input terminal is at a low level, the count value latched at the previous fall continues to be held. In this state, when a signal is applied to the gate valid input terminals 80a, 81a, the held count value appears on the data bus 9.

As an example of the pulse generation circuit 100 that generates the second pulse train to be measured, FIG. . The operation of the pulse generating circuit 100 shown in FIG.
The switch means 19 is closed by a control signal from the capacitor 13, and the capacitor 13 is completely discharged. At this time, the inverting input terminal (-) of the comparator 15 becomes the ground level, so the output level of the comparator 15, that is, the second
The level of the measured pulse 17 becomes high level.
Next, the 1-bit output terminal 4 of the microprocessor 4
When the level of the control signal from e is inverted, the switch means 19 is opened. Then, the charging voltage of the capacitor 13, that is, the potential of the connection point 13a increases with a time constant determined by the values of the capacitor 13 and the resistor 14. At this time, the output level of the comparator 15 remains at a high level, but when the charging voltage of the capacitor 13 exceeds the unknown voltage input from the input terminal 16 to the non-inverting input terminal (+) of the comparator 15, the comparator 1
The output of 5 is inverted to low level. This is because the pulse width of the second measured pulse train 17 output from the comparator 15 has a certain relationship with the unknown voltage.

First regarding the operation of the embodiment of the present invention having the above configuration.
This will be explained with reference to the figures and FIG.

In FIG. 6, the microprocessor 4 activates the switch means 19 as described above by the control signal from the 1-bit output terminal 4e before the start pulse 1a appears at the 1-bit input terminal 4b, so that the second
As shown by 17a in FIG. b, the second pulse train 17 to be measured is set to a high level. When the pulse train 17 reaches a high level, the latched gates 80 and 81 are activated as described above.
acts as a normal gate, so the microprocessor 4 detects the rising edge 1 of this second measured pulse 17.
The count values 30a, 31a of the counters 30, 31 representing the time 7a can be read and stored in the RAM 11 as husband data 11g, 11h. Next, the microprocessor 4 monitors the first measured pulse train 1 at the 1-bit input terminal 4b according to the program. As shown in FIG. 7a, when a start pulse 1a is input to the 1-bit input terminal 4b, data regarding the rise time of the start pulse 1a is stored in the RAM 11 in the manner described above.
Thereafter, as shown at 17b in FIG. 7b, a second measured pulse train 17 is generated with a pulse width corresponding to the value of the unknown voltage.
falls. This falling time is gate 8 with latch.
It is latched by 0,81. For example, the microprocessor 4 receives the count value 30a of the counter 30.
The falling edge 17b of the second pulse to be measured 17 can be detected by reading out continuously or by directly monitoring the second pulse to be measured 17 with another 1-bit input terminal 4f as shown by the broken line in FIG. Check and
After recognizing the falling edge 17b of the second measured pulse 17, the microprocessor 4 reads out the count values latched in the latched gates 80 and 81 at a convenient time and stores them in the RAM 11 as data 11i and 11j. do. After that, the microprocessor 4 outputs the end pulse 1 according to the program.
2b, the switch means 19 of the pulse generating circuit 100 is operated to set the second measured pulse 17 to a high level as shown at 17a' in FIG. 2b. As a result, the latch gates 80 and 81 return to their normal gate functions, so the microprocessor 4
By monitoring the bit input terminal 4b and recognizing the rise of the end pulse 1b as shown in FIG. 2a, the rise time can be read out as described above.

By adjusting the phase relationship between the first and second pulses to be measured in this way, when the second pulse to be measured 17 is at a high level, that is, when the gate with a latch does not perform the latch function, the first pulse to be measured is adjusted. By allowing one start pulse and one end pulse to arrive, it is possible to measure the time interval between the two systems using one set of counters.

(Effect) In the present invention, a gate with a latch is used.
This has the advantage that different types of pulse intervals can be efficiently measured using the same counter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a timing diagram showing the order in which count values are read in the embodiment of FIG. 1.
FIG. 3 is a block diagram showing a conventional time interval measuring method. FIG. 4 is an explanatory diagram showing a time interval calculation method in the method of FIG. 3. 1... Time interval pulse to be measured, 3... Counter, 4... Microprocessor, 7, 70, 71
...gate, 30...lower counter, 31...
Upper counters, 80, 81...gates with latches.

Claims (1)

[Claims] 1. A counter value of a free-running counter means that constantly counts clock pulses of a constant frequency is gated at the measurement start time and measurement end time synchronized with the first pulse train input to the microprocessor. the first and second free-run counters are output to the data bus of the microprocessor via means, and are output to the data bus by the microprocessor at the measurement start time and end time, respectively. In the time interval measuring method, the time interval of the first pulse train is measured by determining a difference between counter values, wherein the gate means has a gate circuit with a latch, and the first pulse train is connected to the microprocessor. When the microprocessor outputs an instruction signal indicating that the data is not input, a second pulse is input to the latch gate circuit to convert the current third count value of the free run counter to the data. When the second pulse train is no longer input to the latch gate circuit, the fourth count value of the free run counter at that time is temporarily stored in the latch gate circuit, and the microprocessor outputs the second pulse train to the latch gate circuit. A time interval measuring method characterized in that the time interval of the second pulse train is also measured by determining the difference between the third and fourth count values. 2. A patent characterized in that the second pulse train is generated by comparing a voltage signal that changes at a constant rate after the generation of the instruction signal from the microprocessor with a separately input voltage signal. The time interval measuring method according to claim 1.